Test trimming circuit with single input port

Abstract

The utility model discloses a test trimming circuit with a single input port. The test trimming circuit comprises an identification circuit, a register and a latch. The test trimming circuit comprises a first circuit, a second circuit, a third circuit, a fourth circuit and a fifth circuit, the input end of the first circuit is only provided with one input interface to realize the input of a test code and a burning code, and the output end of the first circuit is connected with the input ends of the third circuit, the fourth circuit and the fifth circuit; the output end of the third circuit and the output end of the fourth circuit are connected with the input end of the fifth circuit, and the output end of the fifth circuit is connected with a module to be trimmed. According to the single-input port test trimming circuit provided by the utility model, only one port of an integrated circuit finished product is needed to realize trimming of the integrated circuit finished product, the integration level of the circuit is improved, the test difficulty of the circuit is reduced, and the single-input port test trimming circuit is suitable for integrated chips which have no standard communication ports, have fewer ports, but have various versions and higher precision.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit design, in particular to a test and adjustment circuit with a single input port. Background Art

[0002] Finished product trimming technology is used to modify high-precision parameters in integrated circuits and solidify the functionality of various finished product versions. The electronics market's pursuit of intelligent, sophisticated, and miniaturized systems is driving ever-higher precision in integrated circuit performance parameters, increasing the number of parameters requiring adjustment and the complexity of package pinouts. Utility Model Content

[0003] In view of the above-mentioned deficiencies in current integrated circuit design, the present invention provides a test and adjustment circuit with a single input port. By utilizing only one port of the finished integrated circuit, the finished integrated circuit can be adjusted, thereby improving the circuit integration, reducing the difficulty of circuit testing, and making the packaging pins simpler.

[0004] In order to achieve the above-mentioned purpose, the embodiments of the present invention adopt the following technical solutions:

[0005] A single-input test and adjustment circuit is used for testing and adjusting a module to be adjusted. The test and adjustment circuit includes an identification circuit, a register, and a latch. The test and adjustment circuit is characterized in that the test and adjustment circuit includes a first circuit, a second circuit, a third circuit, a fourth circuit, and a fifth circuit. The input end of the first circuit has only one input interface for inputting a test code and a burn-in adjustment code. The output end of the first circuit is connected to the input ends of the third circuit, the fourth circuit, and the fifth circuit. The output ends of the third circuit and the fourth circuit are connected to the input end of the fifth circuit. The output end of the fifth circuit is connected to the module to be adjusted. The first circuit realizes the recognition of burn-in adjustment completion and burn-in adjustment enablement, the second circuit realizes the recognition of reset signal, the third circuit realizes the recognition of pulse width, the fifth circuit realizes the burn-in adjustment code storage function, and the sixth circuit realizes the address bit burn-in adjustment code decoding and the burn-in adjustment enable switch function.

[0006] According to one aspect of the present invention, the input interface serially inputs the control code, and the code type and code value are distinguished by the code signal level value, code signal pulse width, and the number of code square waves.

[0007] According to one aspect of the present invention, the circuit performs time-sharing adjustment on multiple adjustment parameters without power failure, and each adjustment includes a complete adjustment control process.

[0008] According to one aspect of the present invention, the first circuit comprises a burn-in adjustment completion identification circuit and a burn-in adjustment enable identification circuit. One end of a resistor in the first circuit is connected to the input end of a field-effect transistor and a capacitor, respectively, to form a negative voltage comparator, and negative voltage is detected in this manner. The output end of the negative voltage comparator is further connected to the input end of a reset signal register to implement burn-in adjustment completion and burn-in adjustment enable identification functions. Based on the complete adjustment status of the integrated chip, the output logic of the first circuit is determined to be controlled by the input signal or the output logic is locked and not controlled by the input signal.

[0009] According to one aspect of the present invention, the second circuit is a reset signal recognition circuit, and the trim input signal from the first circuit detects the start bit after being delayed by the low-pass filter signal; the output logic is determined by the input power-on reset signal and the single trim completion reset signal, and a high-level code is input after the power-on reset is completed or the single trim is completed to lock the output signal logic.

[0010] According to one aspect of the present invention, the third circuit is a pulse width recognition circuit and an address bit storage circuit. The adjusted input signal is filtered by a latch and a rising edge-triggered low-pass filter and then enters the shift register, so that the address code as a whole shifts one position to the right; the address bit circuit latches the input signal to determine the input of the address code or locks the address bit register.

[0011] According to one aspect of the present invention, the fourth circuit is a latch and burn-in code register circuit, wherein the trimming input signal and the burn-in code circuit latch input signal are input into the burn-in code register after passing through the latch; the high and low levels of the trimming circuit reset signal are determined according to the start code state; the burn-in code input is determined or the burn-in code register is locked by the burn-in code circuit latch input signal; and the square wave input in the trimming input signal is used as a clock trigger signal of the burn-in code register to trigger the logic flip of the register.

[0012] According to one aspect of the present invention, the burn-in code register adopts a binary divider structure, which outputs a fixed code value after the reset signal of the trimming circuit is initialized; when triggered by the input square wave in the trimming input signal, the binary divider performs multiple flipping actions, and the output code value increases by the number of flipping actions, and the output binary code result corresponds to the number of input square waves in the input signal.

[0013] According to one aspect of the present invention, the fifth circuit is a field-effect transistor matrix column, in which field-effect transistors are used to replace switches, and a field-effect transistor array is used to replace a switch array. The fuse burning and adjustment action is completed by the field-effect transistors and the field-effect transistor array being turned on simultaneously through control signals, and the fuse status can be read at the power-on reset stage and the burning and adjustment stage.

[0014] According to one aspect of the present invention, the test and adjustment circuit has a single input interface with multiplexed output or is dedicated to adjustment.

[0015] The advantages of the implementation of the present invention are as follows: by connecting the first circuit, the second circuit, the third circuit, the fourth circuit and the fifth circuit, only one pin of the integrated circuit product is needed to realize the adjustment of the integrated circuit product and the correction control of the internal parameter matrix to be adjusted, thereby improving the integration of the circuit and reducing the difficulty of circuit testing. The utility model is suitable for integrated chips that do not have a standard communication port, have fewer ports, but have various versions and higher precision. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 This is a structural diagram of a test and adjustment circuit with a single input port according to the present invention;

[0018] Figure 2 This is a structural diagram of the first circuit described in the present utility model;

[0019] Figure 3 This is a structural diagram of the second circuit described in the present utility model;

[0020] Figure 4 This is a schematic structural diagram of the third circuit described in the present utility model;

[0021] Figure 5 This is a structural diagram of the fourth circuit described in the present utility model;

[0022] Figure 6 This is a structural diagram of the fifth circuit described in the present utility model; DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0024] Example 1:

[0025] like Figure 1A test and adjustment circuit with a single input port is shown, comprising an identification circuit, a memory, and a latch. The test and adjustment circuit is characterized in that the first circuit input end of the test and adjustment circuit has only one input interface for inputting a test code and a burn-in code, the first circuit output end is connected to the third circuit, fourth circuit, and fifth circuit input ends, the third circuit and fourth circuit output ends are connected to the fifth circuit input end, and the fifth circuit output end is connected to the module to be adjusted; the first circuit implements identification of burn-in completion and burn-in enable, the second circuit implements identification of a reset signal, the third circuit implements identification of a pulse width, the fifth circuit implements a burn-in code register function, and the sixth circuit implements address bit burn-in code decoding and a burn-in enable switch function.

[0026] In this embodiment, the single input interface of the test and adjustment circuit is multiplexed for output or dedicated for adjustment; the input interface serially inputs the control code, and the code category and code value are distinguished by the code signal level value, code signal pulse width, and number of code square waves; multiple adjustment parameters are adjusted in a time-sharing manner without power failure, and each adjustment includes a complete adjustment control process.

[0027] like Figure 2 As shown, the first circuit includes a trim completion identification circuit and a trim enable identification circuit. The input signal 'Trim_end' comes from the dedicated trim status identification fuse state logic output: before the integrated chip completes all trimming, this input logic is '1', and the output logic in circuit 1 is controlled by the input signals 'Trim_code_input' and 'Reset_Trim'. After the integrated chip completes all trimming, this input logic is '0', and the output logic in circuit 1 is locked and no longer controlled by the input signals 'Trim_code_input' and 'Reset_Trim'.

[0028] 'R1', 'NM1', 'NM2', 'NM3', 'NM4', 'PM1', 'PM2', 'PM3', and 'cap1' form a negative voltage comparator. If 'Trim_code_input' is at -0.3V, a logic '0' output will be obtained at the top plate node of cap1. The output will be filtered by the cap1 capacitor and current sink NM3 to eliminate glitch interference.

[0029] The input signal 'Reset_Trim' is the reset signal for the entire trimming circuit. Before the start code is valid, 'Reset_Trim' is low level. After the start code is valid and before the trimming enable code ends, 'Reset_Trim' is high level.

[0030] like Figure 3As shown, the second circuit includes a reset signal recognition circuit. The input signal 'POR' is a power-on reset signal. During power-on reset, the output is logic '0', and after the power-on reset is completed, the output is logic '1'. The input signal 'ReN_Cr' is a single trimming completion reset signal. During a single trimming, the output is logic '0', and after the single trimming is completed, the output is logic '1'. After the power-on reset is completed or the single trimming is completed, 'Trim_code_input' inputs a high-level code with a duration greater than 1ms. This circuit will set the output signal 'Reset_Trim' to logic '1' and lock it until 'Reset_Trim' is set to '0' after the current trimming is completed.

[0031] like Figure 4 As shown, the third circuit includes a pulse width recognition circuit and an n-bit address bit memory circuit. The input signal 'Lock_addcodein' is the latch input signal for the address bit circuit. When the input pulse width of the input signal 'Trim_code_input' is ≥0.4ms, it is filtered by a rising edge-triggered low-pass filter, inputting a logic '1' to the shift register 'DF0' and shifting the address code as a whole one position to the right. When the input pulse width of the input signal 'Trim_code_input' is ≤0.1ms, it is filtered by a rising edge-triggered low-pass filter, inputting a logic '0' to the shift register 'DF0' and shifting the address code as a whole one position to the right. The input signal 'Reset_Trim' is the reset signal for the entire trimming circuit. Before the start code is valid, 'Reset_Trim' is low, and after the start code is valid and before the trimming enable code ends, 'Reset_Trim' is high.

[0032] like Figure 5 As shown, the fourth circuit includes a latch and a u-bit trim code register circuit. The input signal 'Reset_Trim' is the reset signal of the entire trimming circuit. Before the start code is valid, 'Reset_Trim' is low level. After the start code is valid and before the trim enable code ends, 'Reset_Trim' is high level. The input signal 'Lock_trimcodein' is the latch input signal of the u-bit trim code circuit. When the logic is '0', the input of the trim code is allowed. When the logic is '1', the trim code register is locked. In this example, the input signal 'Trim_code_input' inputs a square wave, and the input square wave serves as the clock trigger signal of the u-bit trim code register to trigger the logic flip of this register. In this example, the u-bit trim code register adopts a binary divider structure. Its output binary code is 'Cr …Cr <1> Cr <0> After the input signal 'Reset_Trim' completes initialization, the output code value is '0…00'. Triggered by the input square wave signal 'Trim_code_input', the divider performs a 2x flip operation, and the output code value increases from '0' to '2x'. The output binary code result corresponds to the number of square waves of the input signal 'Trim_code_input'.

[0033] like Figure 6 As shown, the fifth circuit is Ar in the example circuit matrix <r>Column, that is, the circuit corresponding to the address code value r. This example implements the address bit r burn-in code decoding circuit, fuse array, burn-in enable switch, pre-scan and burn-in code memory circuit functions. In this example, the switch 'KrP' is replaced by the PMOS transistor 'PMr', and the switch 'KrN' array is replaced by the NMOS transistor array 'NMr1<0,u>'. In this example, the fuse burn-in action is completed by the PMOS transistor 'PMr' and the NMOS transistor array 'NMr1<0,u>' being turned on simultaneously by the control signal 'EnN_Trim'. When the NMOS transistor 'NMr1<0,u>' of a certain x-way in the r array is turned on <x>' is turned on, then there is a large enough current to blow the fuse Fr <x>The current flows through the fuse Fr <x>Burned. The r array is selected by the address code. For example, in this example, if the address code value is 'r', the r array is selected. The NMOS tube 'NMr1 of a certain x bit in the r array <x>'Whether it is turned on or not is determined by the trim code Trim_code<0,u>. For example, if the trim code value is 'xtr', the corresponding trim step number is 'xtr', and the corresponding NMOS transistor 'NMr1' in the NMOS transistor array 'NMr1<0,u>' is <x>The NMOS transistor array 'NMr2' is controlled by the input signal 'En_read' to read the fuse status during the power-on reset stage and the burn-in stage.

[0034] The advantages of the implementation of the present invention are as follows: by connecting the first circuit, the second circuit, the third circuit, the fourth circuit and the fifth circuit, only one pin of the integrated circuit product is needed to realize the adjustment of the integrated circuit product and the correction control of the internal parameter matrix to be adjusted, thereby improving the integration of the circuit and reducing the difficulty of circuit testing. The utility model is suitable for integrated chips that do not have a standard communication port, have fewer ports, but have various versions and higher precision.

[0035] Example 2:

[0036] like Figure 1 A test and adjustment circuit with a single input port is shown, comprising an identification circuit, a memory, and a latch. The test and adjustment circuit is characterized in that the first circuit input end of the test and adjustment circuit has only one input interface for inputting a test code and a burn-in code, the first circuit output end is connected to the third circuit, fourth circuit, and fifth circuit input ends, the third circuit and fourth circuit output ends are connected to the fifth circuit input end, and the fifth circuit output end is connected to the module to be adjusted; the first circuit implements identification of burn-in completion and burn-in enable, the second circuit implements identification of a reset signal, the third circuit implements identification of a pulse width, the fifth circuit implements a burn-in code register function, and the sixth circuit implements address bit burn-in code decoding and a burn-in enable switch function.

[0037] In this embodiment, the single input interface of the test and adjustment circuit is multiplexed for output or dedicated for adjustment; the input interface serially inputs the control code, and the code category and code value are distinguished by the code signal level value, code signal pulse width, and number of code square waves; multiple adjustment parameters are adjusted in a time-sharing manner without power failure, and each adjustment includes a complete adjustment control process.

[0038] like Figure 2 As shown, the burn-in completion identification circuit and the burn-in enable identification circuit of the first circuit are replaced with a high-voltage identification circuit, which generates a burn-in enable logic signal by applying high voltage. By replacing the circuit modules in this embodiment, the same results can be achieved in this embodiment.

[0039] like Figure 3 As shown, the second circuit includes a reset signal recognition circuit. The input signal 'POR' is a power-on reset signal. During power-on reset, the output is logic '0', and after the power-on reset is completed, the output is logic '1'. The input signal 'ReN_Cr' is a single trimming completion reset signal. During a single trimming, the output is logic '0', and after the single trimming is completed, the output is logic '1'. After the power-on reset is completed or the single trimming is completed, 'Trim_code_input' inputs a high-level code with a duration greater than 1ms. This circuit will set the output signal 'Reset_Trim' to logic '1' and lock it until 'Reset_Trim' is set to '0' after the current trimming is completed.

[0040] like Figure 4 As shown, the third circuit includes a pulse width recognition circuit and an n-bit address bit memory circuit. The input signal 'Lock_addcodein' is the latch input signal for the address bit circuit. When the input pulse width of the input signal 'Trim_code_input' is ≥0.4ms, it is filtered by a rising edge-triggered low-pass filter, inputting a logic '1' to the shift register 'DF0' and shifting the address code as a whole one position to the right. When the input pulse width of the input signal 'Trim_code_input' is ≤0.1ms, it is filtered by a rising edge-triggered low-pass filter, inputting a logic '0' to the shift register 'DF0' and shifting the address code as a whole one position to the right. The input signal 'Reset_Trim' is the reset signal for the entire trimming circuit. Before the start code is valid, 'Reset_Trim' is low, and after the start code is valid and before the trimming enable code ends, 'Reset_Trim' is high.

[0041] like Figure 5 As shown, the fourth circuit includes a latch and a u-bit trim code register circuit. The input signal 'Reset_Trim' is the reset signal of the entire trimming circuit. Before the start code is valid, 'Reset_Trim' is low level. After the start code is valid and before the trim enable code ends, 'Reset_Trim' is high level. The input signal 'Lock_trimcodein' is the latch input signal of the u-bit trim code circuit. When the logic is '0', the input of the trim code is allowed. When the logic is '1', the trim code register is locked. In this example, the input signal 'Trim_code_input' inputs a square wave, and the input square wave serves as the clock trigger signal of the u-bit trim code register to trigger the logic flip of this register. In this example, the u-bit trim code register adopts a binary divider structure. Its output binary code is 'Cr …Cr <1> Cr <0> After the input signal 'Reset_Trim' completes initialization, the output code value is '0…00'. Triggered by the input square wave signal 'Trim_code_input', the divider performs a 2x flip operation, and the output code value increases from '0' to '2x'. The output binary code result corresponds to the number of square waves of the input signal 'Trim_code_input'.

[0042] like Figure 6 As shown, the fifth circuit is Ar in the example circuit matrix <r>Column, that is, the circuit corresponding to the address code value r. This example implements the address bit r burn-in code decoding circuit, fuse array, burn-in enable switch, pre-scan and burn-in code memory circuit functions. In this example, the PMOS transistor 'PMr' replaces the switch 'KrP', and the NMOS transistor array 'NMr1<0,u>' replaces the switch 'KrN' array. In this example, the fuse burn-in action is completed by the PMOS transistor 'PMr' and the NMOS transistor array 'NMr1<0,u>' being turned on simultaneously by the control signal 'EnN_Trim'. When a certain x-way NMOS transistor 'NMr1<0,u>' in the r array is turned on <x>' is turned on, then there is a large enough current to blow the fuse Fr <x>The current flows through the fuse Fr <x>Burned. The r array is selected by the address code. For example, in this example, if the address code value is 'r', the r array is selected. The NMOS tube 'NMr1 of a certain x bit in the r array <x>'Whether it is turned on or not is determined by the trim code Trim_code<0,u>. For example, if the trim code value is 'xtr', the corresponding trim step number is 'xtr', and the corresponding NMOS transistor 'NMr1' in the NMOS transistor array 'NMr1<0,u>' is <x>The NMOS transistor array 'NMr2' is controlled by the input signal 'En_read' to read the fuse status during the power-on reset stage and the burn-in stage.

[0043] The advantages of the implementation of the present invention are as follows: by connecting the first circuit, the second circuit, the third circuit, the fourth circuit and the fifth circuit, only one pin of the integrated circuit product is needed to realize the adjustment of the integrated circuit product and the correction control of the internal parameter matrix to be adjusted, thereby improving the integration of the circuit and reducing the difficulty of circuit testing. The utility model is suitable for integrated chips that do not have a standard communication port, have fewer ports, but have various versions and higher precision.

[0044] By changing the circuit structure in the above embodiment, the same result and function can be obtained.

[0045] Example 3:

[0046] like Figure 1 A test and adjustment circuit with a single input port is shown, comprising an identification circuit, a memory, and a latch. The test and adjustment circuit is characterized in that the first circuit input end of the test and adjustment circuit has only one input interface for inputting a test code and a burn-in code, the first circuit output end is connected to the third circuit, fourth circuit, and fifth circuit input ends, the third circuit and fourth circuit output ends are connected to the fifth circuit input end, and the fifth circuit output end is connected to the module to be adjusted; the first circuit implements identification of burn-in completion and burn-in enable, the second circuit implements identification of a reset signal, the third circuit implements identification of a pulse width, the fifth circuit implements a burn-in code register function, and the sixth circuit implements address bit burn-in code decoding and a burn-in enable switch function.

[0047] In this embodiment, the single input interface of the test and adjustment circuit is multiplexed for output or dedicated for adjustment; the input interface serially inputs the control code, and the code category and code value are distinguished by the code signal level value, code signal pulse width, and number of code square waves; multiple adjustment parameters are adjusted in a time-sharing manner without power failure, and each adjustment includes a complete adjustment control process.

[0048] like Figure 2 As shown, the first circuit includes a trim completion identification circuit and a trim enable identification circuit. The input signal 'Trim_end' comes from the dedicated trim status identification fuse state logic output: before the integrated chip completes all trimming, this input logic is '1', and the output logic in circuit 1 is controlled by the input signals 'Trim_code_input' and 'Reset_Trim'. After the integrated chip completes all trimming, this input logic is '0', and the output logic in circuit 1 is locked and no longer controlled by the input signals 'Trim_code_input' and 'Reset_Trim'.

[0049] 'R1', 'NM1', 'NM2', 'NM3', 'NM4', 'PM1', 'PM2', 'PM3', and 'cap1' form a negative voltage comparator. If 'Trim_code_input' is at -0.3V, a logic '0' output will be obtained at the top plate node of cap1. The output will be filtered by the cap1 capacitor and current sink NM3 to eliminate glitch interference.

[0050] The input signal 'Reset_Trim' is the reset signal for the entire trimming circuit. Before the start code is valid, 'Reset_Trim' is low level. After the start code is valid and before the trimming enable code ends, 'Reset_Trim' is high level.

[0051] like Figure 3 As shown, the reset signal recognition circuit of the second circuit is replaced with a pulse duty cycle recognition circuit or a pulse number recognition circuit to achieve signal recognition. By replacing the circuit modules in this embodiment, the same result can be achieved in the embodiment.

[0052] like Figure 4 As shown, the third circuit includes a pulse width recognition circuit and an n-bit address bit memory circuit. The input signal 'Lock_addcodein' is the latch input signal for the address bit circuit. When the input pulse width of the input signal 'Trim_code_input' is ≥0.4ms, it is filtered by a rising edge-triggered low-pass filter, inputting a logic '1' to the shift register 'DF0' and shifting the address code as a whole one position to the right. When the input pulse width of the input signal 'Trim_code_input' is ≤0.1ms, it is filtered by a rising edge-triggered low-pass filter, inputting a logic '0' to the shift register 'DF0' and shifting the address code as a whole one position to the right. The input signal 'Reset_Trim' is the reset signal for the entire trimming circuit. Before the start code is valid, 'Reset_Trim' is low, and after the start code is valid and before the trimming enable code ends, 'Reset_Trim' is high.

[0053] like Figure 5 As shown, the fourth circuit includes a latch and a u-bit trim code register circuit. The input signal 'Reset_Trim' is the reset signal of the entire trimming circuit. Before the start code is valid, 'Reset_Trim' is low level. After the start code is valid and before the trim enable code ends, 'Reset_Trim' is high level. The input signal 'Lock_trimcodein' is the latch input signal of the u-bit trim code circuit. When the logic is '0', the input of the trim code is allowed. When the logic is '1', the trim code register is locked. In this example, the input signal 'Trim_code_input' inputs a square wave, and the input square wave serves as the clock trigger signal of the u-bit trim code register to trigger the logic flip of this register. In this example, the u-bit trim code register adopts a binary divider structure. Its output binary code is 'Cr …Cr <1> Cr <0> After the input signal 'Reset_Trim' completes initialization, the output code value is '0…00'. Triggered by the input square wave signal 'Trim_code_input', the divider performs a 2x flip operation, and the output code value increases from '0' to '2x'. The output binary code result corresponds to the number of square waves of the input signal 'Trim_code_input'.

[0054] like Figure 6 As shown, the fifth circuit is Ar in the example circuit matrix <r>Column, that is, the circuit corresponding to the address code value r. This example implements the address bit r burn-in code decoding circuit, fuse array, burn-in enable switch, pre-scan and burn-in code memory circuit functions. In this example, the PMOS transistor 'PMr' replaces the switch 'KrP', and the NMOS transistor array 'NMr1<0,u>' replaces the switch 'KrN' array. In this example, the fuse burn-in action is completed by the PMOS transistor 'PMr' and the NMOS transistor array 'NMr1<0,u>' being turned on simultaneously by the control signal 'EnN_Trim'. When a certain x-way NMOS transistor 'NMr1<0,u>' in the r array is turned on <x>' is turned on, then there is a large enough current to blow the fuse Fr <x>The current flows through the fuse Fr <x>Burned. The r array is selected by the address code. For example, in this example, if the address code value is 'r', the r array is selected. The NMOS tube 'NMr1 of a certain x bit in the r array <x>'Whether it is turned on or not is determined by the trim code Trim_code<0,u>. For example, if the trim code value is 'xtr', the corresponding trim step number is 'xtr', and the corresponding NMOS transistor 'NMr1' in the NMOS transistor array 'NMr1<0,u>' is <x>The NMOS transistor array 'NMr2' is controlled by the input signal 'En_read' to read the fuse status during the power-on reset stage and the burn-in stage.

[0055] The advantages of the implementation of the present invention are as follows: by connecting the first circuit, the second circuit, the third circuit, the fourth circuit and the fifth circuit, only one pin of the integrated circuit product is needed to realize the adjustment of the integrated circuit product and the correction control of the internal parameter matrix to be adjusted, thereby improving the integration of the circuit and reducing the difficulty of circuit testing. The utility model is suitable for integrated chips that do not have a standard communication port, have fewer ports, but have various versions and higher precision.

[0056] By changing the circuit structure in the above embodiment, the same result and function can be obtained.

[0057] Example 4:

[0058] like Figure 1 A test and adjustment circuit with a single input port is shown, comprising an identification circuit, a memory, and a latch. The test and adjustment circuit is characterized in that the first circuit input end of the test and adjustment circuit has only one input interface for inputting a test code and a burn-in code, the first circuit output end is connected to the third circuit, fourth circuit, and fifth circuit input ends, the third circuit and fourth circuit output ends are connected to the fifth circuit input end, and the fifth circuit output end is connected to the module to be adjusted; the first circuit implements identification of burn-in completion and burn-in enable, the second circuit implements identification of a reset signal, the third circuit implements identification of a pulse width, the fifth circuit implements a burn-in code register function, and the sixth circuit implements address bit burn-in code decoding and a burn-in enable switch function.

[0059] In this embodiment, the single input interface of the test and adjustment circuit is multiplexed for output or dedicated for adjustment; the input interface serially inputs the control code, and the code category and code value are distinguished by the code signal level value, code signal pulse width, and number of code square waves; multiple adjustment parameters are adjusted in a time-sharing manner without power failure, and each adjustment includes a complete adjustment control process.

[0060] like Figure 2 As shown, the first circuit includes a trim completion identification circuit and a trim enable identification circuit. The input signal 'Trim_end' comes from the dedicated trim status identification fuse state logic output: before the integrated chip completes all trimming, this input logic is '1', and the output logic in circuit 1 is controlled by the input signals 'Trim_code_input' and 'Reset_Trim'. After the integrated chip completes all trimming, this input logic is '0', and the output logic in circuit 1 is locked and no longer controlled by the input signals 'Trim_code_input' and 'Reset_Trim'.

[0061] 'R1', 'NM1', 'NM2', 'NM3', 'NM4', 'PM1', 'PM2', 'PM3', and 'cap1' form a negative voltage comparator. If 'Trim_code_input' is at -0.3V, a logic '0' output will be obtained at the top plate node of cap1. The output will be filtered by the cap1 capacitor and current sink NM3 to eliminate glitch interference.

[0062] The input signal 'Reset_Trim' is the reset signal for the entire trimming circuit. Before the start code is valid, 'Reset_Trim' is low level. After the start code is valid and before the trimming enable code ends, 'Reset_Trim' is high level.

[0063] like Figure 3 As shown, the second circuit includes a reset signal recognition circuit. The input signal 'POR' is a power-on reset signal. During power-on reset, the output is logic '0', and after the power-on reset is completed, the output is logic '1'. The input signal 'ReN_Cr' is a single trimming completion reset signal. During a single trimming, the output is logic '0', and after the single trimming is completed, the output is logic '1'. After the power-on reset is completed or the single trimming is completed, 'Trim_code_input' inputs a high-level code with a duration greater than 1ms. This circuit will set the output signal 'Reset_Trim' to logic '1' and lock it until 'Reset_Trim' is set to '0' after the current trimming is completed.

[0064] like Figure 4 As shown, replacing the pulse width identification circuit of the third circuit with a pulse number identification circuit can achieve the pulse duty cycle identification effect at a fixed frequency. By replacing the circuit modules in this embodiment, the embodiment can also achieve the same result.

[0065] like Figure 5 As shown, the fourth circuit includes a latch and a u-bit trim code register circuit. The input signal 'Reset_Trim' is the reset signal of the entire trimming circuit. Before the start code is valid, 'Reset_Trim' is low level. After the start code is valid and before the trim enable code ends, 'Reset_Trim' is high level. The input signal 'Lock_trimcodein' is the latch input signal of the u-bit trim code circuit. When the logic is '0', the input of the trim code is allowed. When the logic is '1', the trim code register is locked. In this example, the input signal 'Trim_code_input' inputs a square wave, and the input square wave serves as the clock trigger signal of the u-bit trim code register to trigger the logic flip of this register. In this example, the u-bit trim code register adopts a binary divider structure. Its output binary code is 'Cr …Cr <1> Cr <0> After the input signal 'Reset_Trim' completes initialization, the output code value is '0…00'. Triggered by the input square wave signal 'Trim_code_input', the divider performs a 2x flip operation, and the output code value increases from '0' to '2x'. The output binary code result corresponds to the number of square waves of the input signal 'Trim_code_input'.

[0066] like Figure 6 As shown, the fifth circuit is Ar in the example circuit matrix <r>Column, that is, the circuit corresponding to the address code value r. This example implements the address bit r burn-in code decoding circuit, fuse array, burn-in enable switch, pre-scan and burn-in code memory circuit functions. In this example, the switch 'KrP' is replaced by the PMOS transistor 'PMr', and the switch 'KrN' array is replaced by the NMOS transistor array 'NMr1<0,u>'. In this example, the fuse burn-in action is completed by the PMOS transistor 'PMr' and the NMOS transistor array 'NMr1<0,u>' being turned on simultaneously by the control signal 'EnN_Trim'. When the NMOS transistor 'NMr1<0,u>' of a certain x-way in the r array is turned on <x>' is turned on, then there is a large enough current to blow the fuse Fr <x>The current flows through the fuse Fr <x>Burned. The r array is selected by the address code. For example, in this example, if the address code value is 'r', the r array is selected. The NMOS tube 'NMr1 of a certain x bit in the r array <x>'Whether it is turned on or not is determined by the trim code Trim_code<0,u>. For example, if the trim code value is 'xtr', the corresponding trim step number is 'xtr', and the corresponding NMOS transistor 'NMr1' in the NMOS transistor array 'NMr1<0,u>' is <x>The NMOS transistor array 'NMr2' is controlled by the input signal 'En_read' to read the fuse status during the power-on reset stage and the burn-in stage.

[0067] The advantages of the implementation of the present invention are as follows: by connecting the first circuit, the second circuit, the third circuit, the fourth circuit and the fifth circuit, only one pin of the integrated circuit product is needed to realize the adjustment of the integrated circuit product and the correction control of the internal parameter matrix to be adjusted, thereby improving the integration of the circuit and reducing the difficulty of circuit testing. The utility model is suitable for integrated chips that do not have a standard communication port, have fewer ports, but have various versions and higher precision.

[0068] By changing the circuit structure in the above embodiment, the same result and function can be obtained.

[0069] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.< / x> < / x> < / x> < / x> < / x> < / r> < / x> < / x> < / x> < / x> < / x> < / r> < / x> < / x> < / x> < / x> < / x> < / r> < / x> < / x> < / x> < / x> < / x> < / r>

Claims

1. A single-input test and adjustment circuit for testing and adjusting a module to be adjusted, the test and adjustment circuit comprising an identification circuit, a register, and a latch, characterized in that: The test and adjustment circuit includes a first circuit, a second circuit, a third circuit, a fourth circuit, and a fifth circuit. The input end of the first circuit has only one input interface for inputting a test code and a burn-in adjustment code. The output end of the first circuit is connected to the input ends of the third circuit, the fourth circuit, and the fifth circuit. The output ends of the third circuit and the fourth circuit are connected to the input end of the fifth circuit. The output end of the fifth circuit is connected to the module to be adjusted. The first circuit realizes the recognition of burn-in adjustment completion and burn-in adjustment enablement. The second circuit realizes the recognition of reset signal. The third circuit realizes the recognition of pulse width. The fifth circuit realizes the burn-in adjustment code storage function. The first circuit, the second circuit, the third circuit, the fourth circuit, and the fifth circuit cooperate to realize the adjustment of the finished integrated circuit through a single input port.

2. The single-input test and adjustment circuit according to claim 1, wherein: The test adjustment circuit adjusts multiple adjustment parameters in a time-sharing manner without power failure, and each adjustment includes a complete adjustment control process.

3. The single-input test and adjustment circuit according to claim 1, wherein: The input interface serially inputs the control code, and the code type and code value of the control code are distinguished by the code signal level value, code signal pulse width, and the number of code square waves.

4. The single-input test and adjustment circuit according to claim 1, wherein: The first circuit comprises a burn-in adjustment completion identification circuit and a burn-in adjustment enable identification circuit. One end of a resistor in the first circuit is connected to the input end of a field-effect transistor and a capacitor, respectively, to form a negative voltage comparator, thereby detecting negative voltage. The output end of the negative voltage comparator is further connected to the input end of a reset signal register to implement burn-in adjustment completion and burn-in adjustment enable identification functions. Based on the complete adjustment status of the integrated chip, the output logic of the first circuit is determined to be controlled by the input signal or the output logic is locked and not controlled by the input signal.

5. The single-input test and adjustment circuit according to claim 1, wherein: The second circuit is a reset signal recognition circuit. The trim input signal from the first circuit detects the start bit after being delayed by a low-pass filter signal. The output logic is determined by the input power-on reset signal and the single trim completion reset signal, and a high-level code is input after the power-on reset is completed or the single trim is completed to lock the output signal logic.

6. The single-input test and adjustment circuit according to claim 5, characterized in that: The third circuit is a pulse width recognition circuit and an address bit memory circuit. The adjusted input signal is filtered by a latch and a rising edge-triggered low-pass filter and then enters the shift register, causing the address code to shift one position to the right as a whole. The address bit circuit latches the input signal to determine the input of the address code or lock the address bit register.

7. The single-input test and adjustment circuit according to claim 5, characterized in that: The fourth circuit is a latch and burn-in code register circuit. The trimming input signal and the burn-in code circuit latch input signal are input into the burn-in code register after passing through the latch. The high and low levels of the trimming circuit reset signal are determined according to the start code state. The burn-in code input is determined or the burn-in code register is locked by the burn-in code circuit latch input signal. The square wave input in the trimming input signal is used as the clock trigger signal of the burn-in code register to trigger the logic flip of the register.

8. The single-input test and adjustment circuit according to claim 7, wherein: The burn-in code register adopts a binary divider structure and outputs a fixed code value after the reset signal of the trimming circuit is initialized. When triggered by a square wave input in the trimming input signal, the binary divider performs multiple flipping actions, and the output code value increases by the number of flipping actions. The output binary code result corresponds to the number of input square waves in the input signal.

9. The single-input test and adjustment circuit according to claim 1, wherein: The fifth circuit is a field-effect transistor matrix array, in which field-effect transistors are used to replace switches, and a field-effect transistor array is used to replace a switch array. The fuse burning and adjustment action is completed by the field-effect transistors and the field-effect transistor array being turned on simultaneously through control signals, and the fuse status can be read at the power-on reset stage and the burning and adjustment stage.

10. The single-input test and adjustment circuit according to any one of claims 1 to 9, characterized in that: The input interface of the test and adjustment circuit is also used as an output, or the input interface of the test and adjustment circuit is also used for adjustment.

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