Electronic equipment reset management circuit

Abstract

The utility model belongs to the technical field of equipment management, and particularly relates to an electronic equipment reset management circuit. The electronic equipment comprises a voltage stabilizing chip U1 and a single chip microcomputer U2 connected to the output end of the voltage stabilizing chip U1, an input pin VIN of the voltage stabilizing chip U1 is connected with a voltage input end, an enabling pin EN of the voltage stabilizing chip U1 is connected with the voltage input end through a resistor R3, the electronic equipment reset management circuit comprises a reset key SW1, and the reset key SW1 is connected between the enabling pin EN of the voltage stabilizing chip U1 and a grounding end; the grid electrode of the field effect transistor Q1 is connected to the enabling pin EN of the voltage stabilizing chip U1, the source electrode of the field effect transistor Q1 is connected to the output end of the voltage stabilizing chip U1, and the drain electrode of the field effect transistor Q1 is grounded through a resistor R5. The reset efficiency, reliability and stability are improved, thorough reset is ensured, and the user experience is improved.

Description

Technical Field

[0001] The present application belongs to the field of device management technology, and in particular relates to a reset management circuit for an electronic device. Background Art

[0002] Reset circuits are an integral part of the development, debugging, and use of electronic devices. Their primary function is to restore core system components (such as processors and memory) to their initial states during device startup, troubleshooting, or user requests, ensuring the device operates consistently and in a predetermined state. With the continuous advancement of electronic technology, the design and application of reset circuits have become increasingly complex and diverse. Reset circuits are crucial components of electronic circuits, especially those incorporating microprocessors or system-on-chip (SoC) designs. Their primary function is to reset the chip upon power-up or under specific conditions, ensuring it starts operating from a known state. This helps avoid unpredictable behavior and ensures system reliability and stability. In traditional reset circuit designs, a simple RC delay circuit or a dedicated reset IC may be used to generate the required reset signal. These circuits typically maintain the reset signal for a period of time after the power supply stabilizes to ensure the system is fully booted.

[0003] The existing reset circuit design has the following problems:

[0004] 1. Low reset efficiency: After power is removed, traditional reset circuits must wait for the voltage-stabilizing capacitors in the circuit to discharge naturally. This time-consuming process results in low reset efficiency. During rapid development and debugging, this waiting time can seriously impact work efficiency.

[0005] 2. Incomplete reset: If the power is turned on again without fully discharging the capacitor, the reset may not be complete. The internal circuit and register status may not be completely cleared, which may lead to problems such as device startup failure, abnormal operation, or download failure.

[0006] 3. Poor user experience: For end users, if the device cannot respond quickly when it needs to be reset, it will directly affect user satisfaction and usage experience. Especially in emergency situations, fast reset is particularly important.

[0007] 4. Circuit complexity and cost: In order to implement more complex reset functions (such as software reset, watchdog reset, etc.), the circuit design often becomes more complicated, increasing the cost and maintenance difficulty.

[0008] 5. Reliability and stability issues: In some cases, improper reset circuit design or component aging may cause reset failure or circuit damage, thus affecting the reliability and stability of the device. Utility Model Content

[0009] In order to solve the above technical problems, the present application provides an electronic device reset management circuit to solve problems such as incomplete reset, power-on failure, abnormal device startup or unstable operation caused by the slow discharge speed of the voltage-stabilizing capacitor after power failure.

[0010] The present application provides an electronic device reset management circuit, wherein the electronic device includes a voltage regulator chip U1 and a single-chip microcomputer U2 connected to the output end of the voltage regulator chip U1, the input pin VIN of the voltage regulator chip U1 is connected to the voltage input end, and the enable pin EN is connected to the voltage input end through a resistor R3. The electronic device reset management circuit includes:

[0011] A reset button SW1 is connected between the enable pin EN of the voltage regulator chip U1 and the ground terminal;

[0012] The field effect transistor Q1 has a gate connected to the enable pin EN of the voltage regulator chip U1 , a source connected to the output end of the voltage regulator chip U1 , and a drain connected to the ground via a resistor R5 .

[0013] Preferably, the voltage input end is connected to a Type-C power supply interface, and the Type-C power supply interface provides a 5V input voltage.

[0014] Preferably, the voltage stabilizing chip U1 is used to convert the input 5V voltage into a stable 3.3V voltage output.

[0015] Preferably, the output end of the voltage stabilizing chip U1 is grounded to the microcontroller U2 via a plurality of capacitors.

[0016] Preferably, the field effect transistor Q1 is a PMOS transistor.

[0017] Preferably, the voltage stabilizing chip U1 adopts a DC to DC voltage stabilizer of model ETA3425S2F.

[0018] This application improves reset efficiency, reliability, and stability, ensures a thorough reset, and enhances user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the interconnection between a voltage stabilizing chip and an electronic device reset management circuit in a preferred embodiment of the electronic device reset management circuit of the present application.

[0020] Figure 2 This is a schematic diagram of the Type-C power supply interface circuit.

[0021] Figure 3 This is the circuit diagram of the microcontroller U2. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the implementation of this application clearer, the technical solutions in the implementation of this application will be described in more detail below in conjunction with the drawings in the implementation of this application. In the drawings, the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. The described implementation is a part of the implementation of this application, not all of the implementations. The implementation described below with reference to the drawings is exemplary and is intended to be used to explain this application, and should not be understood as a limitation on this application. Based on the implementation in this application, all other implementations obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The implementation of this application is described in detail below in conjunction with the drawings.

[0023] The present application provides an electronic device reset management circuit, the electronic device includes Figure 1 The voltage regulator chip U1 and Figure 3 The microcontroller U2 is connected to the output end of the voltage regulator chip U1, the input pin VIN of the voltage regulator chip U1 is connected to the voltage input end, and the enable pin EN is connected to the voltage input end through the resistor R3, wherein, Figure 1 As shown, the electronic device reset management circuit includes:

[0024] A reset button SW1 is connected between the enable pin EN of the voltage regulator chip U1 and the ground terminal;

[0025] The field effect transistor Q1 has a gate connected to the enable pin EN of the voltage regulator chip U1 , a source connected to the output end of the voltage regulator chip U1 , and a drain connected to the ground via a resistor R5 .

[0026] refer to Figure 1 In normal working state, when the reset button SW1 is not pressed, the voltage input end pulls up pin 1 (enable pin EN) of the voltage regulator chip U1 through the resistor R3, and the voltage regulator chip U1 works normally and outputs a stable voltage (marked as 3V3) to the outside.

[0027] In this state, the gate of the field effect transistor Q1 is also pulled high, and the field effect transistor Q1 is in the off state, so it will not affect the operation of the voltage regulator chip U1. The voltage 3V3 output by the voltage regulator chip U1 is normally supplied to the microcontroller U2 and other loads. The microcontroller U2 here can be, for example, an MCU of model HC32L130F8UAQ, which is powered by the voltage 3V3 and performs control tasks.

[0028] When the reset button SW1 is pressed, pin 1 (enable pin EN) of the voltage regulator chip U1 is pulled low, causing the voltage regulator chip U1 to stop operating and stop outputting the 3V3 voltage. Simultaneously, the reset button SW1 pulls down the gate voltage of the field-effect transistor Q1, turning it on. Once turned on, the field-effect transistor Q1 rapidly discharges the charge in the capacitor in the 3V3 voltage network to ground through its drain and resistor R5.

[0029] When the reset button SW1 is released, the voltage input terminal pulls up pin 1 (enable pin EN) of the voltage regulator chip U1 again through the resistor R3, and the voltage regulator chip U1 continues to provide stable power to the microcontroller U2.

[0030] In some optional implementations, the voltage input terminal is connected to a Type-C power supply interface, and the Type-C power supply interface provides a 5V input voltage, such as Figure 2 As shown, the Type-C power supply interface J1 provides an input voltage, which is usually 5V.

[0031] In some optional embodiments, the voltage stabilizing chip U1 is used to convert the input 5V voltage into a stable 3.3V output voltage. In some optional embodiments, the voltage stabilizing chip U1 is a DC-to-DC voltage regulator of model ETA3425S2F.

[0032] In some optional implementations, the output end of the voltage regulator chip U1 is grounded to the microcontroller U2 via multiple capacitors, such as Figure 1 The capacitors C5 and C6 shown in FIG. Figure 3 As shown in the figure, capacitor C8 and capacitor C9, when field effect tube Q1 is turned on, the charge in these four capacitors is mainly released.

[0033] In some optional implementations, the field effect transistor Q1 is a PMOS transistor, model DC3415E.

[0034] This application adopts a special reset circuit design, which uses a combination of PMOS tube Q1 and resistor R5 to achieve rapid discharge of the voltage-stabilizing capacitor, solving the problem of slow discharge speed in the prior art. In addition, the reset button is not only used to trigger the reset process, but also promotes the rapid discharge of the capacitor by controlling the gate voltage of the PMOS tube. The selection of the PMOS tube and the resistor and their combination are crucial to achieving rapid discharge. This specific combination ensures that the capacitor can be discharged in the shortest possible time, thereby improving the response speed of the entire system. Rapid discharge ensures that the device can start from a completely power-off state every time it is restarted.

[0035] This application simplifies the user's operation steps and improves reset efficiency by integrating power-off control with reset operations.

[0036] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A reset management circuit for an electronic device, comprising a voltage regulator chip U1 and a microcontroller U2 connected to the output terminal of the voltage regulator chip U1, wherein the input pin VIN of the voltage regulator chip U1 is connected to the voltage input terminal, and the enable pin EN is connected to the voltage input terminal via a resistor R3, characterized in that: The electronic device reset management circuit includes: A reset button SW1 is connected between the enable pin EN of the voltage regulator chip U1 and the ground terminal; The field effect transistor Q1 has a gate connected to the enable pin EN of the voltage regulator chip U1 , a source connected to the output end of the voltage regulator chip U1 , and a drain connected to the ground via a resistor R5 .

2. The electronic device reset management circuit according to claim 1, wherein: The voltage input end is connected to the Type-C power supply interface, and the Type-C power supply interface provides a 5V input voltage.

3. The electronic device reset management circuit according to claim 2, wherein: The voltage regulator chip U1 is used to convert the input 5V voltage into a stable 3.3V voltage output.

4. The electronic device reset management circuit according to claim 1, wherein: The output end of the voltage stabilizing chip U1 is grounded to the microcontroller U2 via a plurality of capacitors.

5. The electronic device reset management circuit according to claim 1, wherein: The field effect tube Q1 is a PMOS tube.

6. The electronic device reset management circuit according to claim 1, wherein: The voltage stabilizing chip U1 adopts a DC to DC voltage stabilizer of model ETA3425S2F.

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