Power supply control circuit, power supply circuit and chip

Abstract

The utility model discloses a power supply control circuit, a power supply circuit and a chip, the power supply control circuit comprises a first stage differential mode processing circuit, a second stage differential mode processing circuit and a common mode processing circuit, the input end of the first stage differential mode processing circuit receives a power supply signal and is used for carrying out differential mode filtering on the power supply signal; the second-stage differential mode processing circuit is coupled with the first output end of the first-stage differential mode processing circuit and is used for performing differential mode filtering on the power supply signal, and the output end of the second-stage differential mode processing circuit serves as the first output end of the power supply control circuit; the common-mode processing circuit is coupled with the second output end of the first-stage differential-mode processing circuit and is used for carrying out common-mode filtering on the power supply signal, and the output end of the common-mode processing circuit serves as the second output end of the power supply control circuit; therefore, the influence of surge on the circuit can be effectively prevented, the damage probability of devices in the circuit is reduced, and the service life of the power supply is prolonged.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a power control circuit, a power circuit, and a chip. Background Art

[0002] In the application of power electronics, a power supply is usually used, and multiple circuits need to be powered.

[0003] During actual operation, the researchers of this application found that the power supply of the programmable logic controller in the current technology mainly supplies power to four circuits: the DIDO circuit (Digital Input Digital Output), the AIAO circuit (Analog input, analog output), the CPU circuit (Central Processing Unit), and the isolated communication circuit. In the current technology, the main interference sources of the power supply circuit solution are the MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) of the switching power supply and the subsequent BUCK circuit. In addition, the number of capacitors is large and the cost is high. When testing the conducted emission, the high-frequency common-mode noise generated by the MOS tube will be collected by the receiver, resulting in excessive high-frequency common-mode noise emission. In addition, the DIDO circuit requires an external load, and the length of the external line is long, which is prone to introducing external interference or being damaged by large transient surge power, affecting the performance of the power supply. Utility Model Content

[0004] The main technical problem solved by this application is to provide a power supply control circuit, a power supply circuit and a chip, which can effectively prevent the impact of surges on the circuit, reduce the probability of damage to components in the circuit, and increase the service life of the power supply.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a power supply control circuit, including: a first-stage differential mode processing circuit, a second-stage differential mode processing circuit and a common mode processing circuit; the input end of the first-stage differential mode processing circuit receives the power supply signal, and is used to perform differential mode filtering on the power supply signal; the second-stage differential mode processing circuit is coupled to the first output end of the first-stage differential mode processing circuit, and is used to perform differential mode filtering on the power supply signal, wherein the output end of the second-stage differential mode processing circuit serves as the first output end of the power supply control circuit; the common mode processing circuit is coupled to the second output end of the first-stage differential mode processing circuit, and is used to perform common mode filtering on the power supply signal, wherein the output end of the common mode processing circuit serves as the second output end of the power supply control circuit.

[0006] In order to solve the above technical problems, another technical solution adopted in this application is: providing a power supply circuit, including the above power supply control circuit.

[0007] In order to solve the above technical problems, another technical solution adopted in this application is: providing a chip including the above power control circuit.

[0008] Different from the current technology, the power control circuit provided by the present application includes a first-stage differential mode processing circuit, a second-stage differential mode processing circuit, and a common mode processing circuit; the input end of the first-stage differential mode processing circuit receives the power signal and is used to perform differential mode filtering on the power signal; the second-stage differential mode processing circuit is coupled to the first output end of the first-stage differential mode processing circuit and is used to perform differential mode filtering on the power signal, wherein the output end of the second-stage differential mode processing circuit serves as the first output end of the power control circuit; the common mode processing circuit is coupled to the second output end of the first-stage differential mode processing circuit and is used to perform common mode filtering on the power signal, wherein the output end of the common mode processing circuit serves as the second output end of the power control circuit. That is, the technical solution of the present application performs different filtering corresponding to different output ends, which can effectively prevent the impact of surges on the circuit, reduce the probability of damage to components in the circuit, and increase the service life of the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0010] Figure 1 It is a structural diagram of the first embodiment of the power control circuit in this application;

[0011] Figure 2 It is a structural diagram of the second embodiment of the power control circuit in this application;

[0012] Figure 3 is a schematic diagram of the circuit structure of the interference transmission path in this application;

[0013] Figure 4 Schematic diagram of the circuit structure of the differential mode surge transmission path in this application;

[0014] Figure 5 It is a structural diagram of an embodiment of a power supply circuit in this application;

[0015] Figure 6 It is a structural diagram of a chip embodiment in this application.

[0016] In the accompanying drawings, the power control device 1, the chip 2, the power control circuit 10, the first differential mode processing circuit 100, the second differential mode processing circuit 200, the common mode processing circuit 300, the common mode filter circuit 310, the first common mode filter circuit 311, the second common mode filter circuit 312, the differential mode inductor L1, the first capacitor unit C1, the first capacitor C11, the second capacitor C12, the second capacitor unit C2, the third capacitor C21, the fourth capacitor C22, the first TVS tube D1, the second TVS tube D2, the first common mode inductor L2, the second common mode inductor L 3. Third capacitor unit C3, fifth capacitor C31, fourth capacitor unit C4, sixth capacitor C41, seventh capacitor C42, fifth capacitor unit C5, eighth capacitor C51, ninth capacitor C52, sixth capacitor unit C6, tenth capacitor C61, eleventh capacitor C62, seventh capacitor unit C7, twelfth capacitor C71, thirteenth capacitor C72, eighth capacitor unit C8, fourteenth capacitor C81, ninth capacitor unit C9, fifteenth capacitor C91, third TVS tube D3, power input module 400, sixteenth capacitor C10. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0018] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0019] The steps in the embodiments of the present application do not necessarily have to be processed in the order of the described steps. The steps can be selectively rearranged as needed, or the steps in the embodiments can be deleted, or the steps in the embodiments can be added. The step descriptions in the embodiments of the present application are only optional sequence combinations and do not represent all step sequence combinations in the embodiments of the present application. The order of the steps in the embodiments cannot be considered as a limitation of the present application.

[0020] The term "and / or" in the embodiments of the present application refers to any and all possible combinations of one or more of the associated listed items. It should also be noted that when used in this specification, "include / comprise" specifies the presence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements and / or components and / or groups thereof.

[0021] The terms "first," "second," and the like in this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0022] In current technology, in programmable logic-controlled power supply circuits, the first-stage CLC filtering solution has a large number of Y capacitors, resulting in high costs. The high-frequency common-mode noise generated by the MOS tube of the switching power supply flows through to the power port and is then detected by the receiver during conducted emission testing, causing the programmable logic controller's high-frequency common-mode noise emissions to exceed the standard. When differential-mode surges are present in the environment, components in the power supply circuit will be damaged because the rated transient surge power is less than the maximum transient surge power in the circuit, affecting the performance of the power supply circuit and reducing its service life.

[0023] Therefore, a power supply control circuit is provided, which can effectively prevent the impact of surges on the circuit, reduce the probability of damage to components in the circuit, and increase the service life of the power supply.

[0024] See also Figure 1 , Figure 1 It is a structural diagram of the first embodiment of the power control circuit in this application.

[0025] like Figure 1As shown, the power control circuit 10 in the present application includes: a first-stage differential mode processing circuit 100, a second-stage differential mode processing circuit 200 and a common mode processing circuit 300; wherein, the input end of the first-stage differential mode processing circuit 100 receives the power signal and is used to perform differential mode filtering on the power signal; the second-stage differential mode processing circuit 200 is coupled to the first output end of the first-stage differential mode processing circuit 100, and is used to perform differential mode filtering on the power signal, and the output end of the second-stage differential mode processing circuit serves as the first output end of the power control circuit 10; the common mode processing circuit 300 is coupled to the second output end of the first-stage differential mode processing circuit 100, and is used to perform common mode filtering on the power signal, and the output end of the common mode processing circuit 300 serves as the second output end of the power control circuit 10.

[0026] Among them, power is supplied to different parts of the circuit, and different types of filtering are performed according to the needs of each part of the circuit. For example, the first output end of the power control circuit 10 can be connected to the DIDO circuit, and the second output end of the power control circuit 10 can be connected to the AIAI circuit, the CPU circuit, the isolated communication circuit, etc.

[0027] Therefore, the first-stage differential mode processing circuit 100 is set to perform differential mode filtering, the second-stage differential mode processing circuit 200 is set to perform differential mode filtering, and the common mode processing circuit 300 performs common mode filtering on the power signal after the differential mode filtering of the second-stage differential mode processing circuit 200, thereby completing the filtering of each circuit.

[0028] In this embodiment, in order to meet the power supply needs of the programmable logic controller to supply power to some circuits with different requirements, the input power signal is filtered according to different requirements. For example, the first output end for differential mode filtering can correspond to the DIDO circuit, and the second output end for differential mode filtering and common mode filtering can correspond to the remaining circuits. This can effectively prevent the impact of surges on the circuit, reduce the probability of damage to devices in the circuit, and improve the service life of the power supply.

[0029] See Figure 2 , Figure 2 It is a structural diagram of the second embodiment of the power control circuit in this application.

[0030] like Figure 2As shown, the power control circuit 10 includes: a first-stage differential mode processing circuit 100, a second-stage differential mode processing circuit 200, and a common mode processing circuit 300. The input terminal of the first-stage differential mode processing circuit 100 receives a power signal and is used to perform differential mode filtering on the power signal. The second-stage differential mode processing circuit 200 is coupled to the first output terminal of the first-stage differential mode processing circuit 100 and is used to perform differential mode filtering on the power signal. The output terminal of the second-stage differential mode processing circuit serves as the first output terminal of the power control circuit 10. The common mode processing circuit 300 is coupled to the second output terminal of the first-stage differential mode processing circuit 100 and is used to perform common mode filtering on the power signal. The output terminal of the common mode processing circuit 300 serves as the second output terminal of the power control circuit 10.

[0031] In which, the first-stage differential mode processing circuit 100 includes a differential mode inductor L1, a first capacitor unit C1, and a second capacitor unit C2. The input end of the differential mode inductor L1 receives a power supply signal, the first capacitor unit C1 is coupled to the output end of the differential mode inductor L1, and the second end of the first capacitor unit C1 serves as the first output end of the first-stage differential mode processing circuit 100; the first end of the second capacitor unit C2 is coupled to the second end of the first capacitor unit C1, and the second end of the second capacitor unit C2 serves as the second output end of the first-stage differential mode processing circuit.

[0032] Placing the differential-mode inductor L1 at the front end can decouple and divide the differential-mode surge signal, thereby reducing the surge voltage distributed to the DIDO circuit. Furthermore, first-stage differential-mode filtering and second-stage differential-mode filtering are performed by the first-stage differential-mode processing circuit and the second-stage differential-mode processing circuit, effectively preventing damage to the subsequent third TVS diode D3 and improving the reliability of the power control circuit.

[0033] In some embodiments, the first capacitor unit C1 includes at least two capacitors connected in parallel, and the second capacitor unit C2 includes at least two capacitors connected in parallel.

[0034] For example, the first capacitor unit C1 includes a first capacitor C11 and a second capacitor C12, and the second capacitor unit includes a third capacitor C21 and a fourth capacitor C22. Then, the first capacitor C11 and the second capacitor C12 are connected in parallel. The first capacitor C11 is coupled to the output end of the differential mode inductor. The second capacitor C12 serves as the second end of the first capacitor unit C1 and also as the first output end of the first-stage differential mode processing circuit 100, for outputting the power signal after the first-stage differential mode filtering to the subsequent second-stage differential mode processing circuit 200. The third capacitor C21 and the fourth capacitor C22 are connected in parallel. The third capacitor C21 is coupled to the second capacitor C12, that is, coupled to the second end of the first capacitor unit C1. The fourth capacitor C22 serves as the second end of the second capacitor unit C2, and also serves as the second output end of the first-stage differential mode processing circuit 100. It also serves as the first output end of the power control circuit 10, and is used to output the power signal after the first-stage differential mode filtering to other subsequent partial circuits, so that the power control circuit of the present application can perform filtering processing on partial circuits with different requirements, and then supply power to partial circuits with different requirements, thereby improving the utilization rate of the power control circuit.

[0035] In some embodiments, the common-mode processing circuit 300 includes: a common-mode filter circuit 310 and a TVS tube D; the input end of the common-mode filter circuit 310 is coupled to the second output end of the first-stage differential-mode processing circuit 100, that is, coupled to the fourth capacitor C22, and the TVS tube is coupled to the output end of the common-mode filter circuit 310; the connection point between the common-mode filter circuit 310 and the TVS tube serves as the output end of the common-mode filter circuit 310, for outputting the power signal after common-mode filtering.

[0036] The power control circuit 10 also includes a third output terminal. The first TVS diode D1 is coupled to the output terminal of the first common-mode filter circuit 311 and is coupled as the second output terminal of the power control circuit 10. The second TVS diode D2 is coupled to the output terminal of the second common-mode filter circuit 312 and is coupled as the third output terminal of the power control circuit 10.

[0037] The common-mode filter circuit 310 includes a first common-mode filter circuit 311 and a second common-mode filter circuit 312; the TVS diode includes a first TVS diode D1 and a second TVS diode D2; the input end of the first common-mode filter circuit 311 is coupled to the second output end of the first-stage differential-mode processing circuit 100, that is, coupled to the fourth capacitor C22; the first TVS diode D1 is coupled to the output end of the first common-mode filter circuit 311, and the coupling point between the first TVS diode D1 and the first common-mode filter circuit 311 serves as the second output end of the power control circuit; the input end of the second common-mode filter circuit 312 is coupled to the second output end of the first-stage differential-mode processing circuit 100, that is, coupled to the fourth capacitor C22; the second TVS diode D2 is coupled to the output end of the second common-mode filter circuit 312, and the coupling point between the second TVS diode D2 and the second common-mode filter circuit 312 serves as the third output end of the power control circuit 10.

[0038] The second output terminal of the power control circuit 10 is coupled to the subsequent isolated communication circuit, thereby transmitting the power signal after common-mode filtering by the first common-mode filter circuit 311 to the isolated communication circuit; the third output terminal of the power control circuit 10 is coupled to the subsequent AIAO circuit and / or CPU circuit, thereby transmitting the power signal after common-mode filtering by the second common-mode filter circuit 312 to the AIAO circuit and / or CPU circuit.

[0039] The first common-mode filter circuit 311 includes a first common-mode inductor L2, a third capacitor unit C3, and a fourth capacitor unit C4. The first input end of the first common-mode inductor L2 is coupled to the second output end of the first-stage differential-mode processing circuit 100, and the first output end of the first common-mode inductor L2 is coupled to the first TVS diode D1; the third capacitor unit C3 is coupled to both ends of the first TVS diode D1; the first end of the fourth capacitor unit C4 is coupled to the second input end of the first common-mode inductor L2, and the second end of the fourth capacitor unit C4 is grounded.

[0040] The third capacitor unit C3 includes at least one capacitor, and the fourth capacitor unit C4 includes at least two capacitors connected in series.

[0041] Taking the third capacitor unit C3 including the fifth capacitor C31 and the fourth capacitor unit C4 including the sixth capacitor C41 and the seventh capacitor C42 as an example for explanation: the first input terminal and the second input terminal of the first common-mode inductor L2 are coupled to the two ends of the fourth capacitor C22, and are used to receive the power supply signal after the first-stage differential mode filtering by the first-stage differential mode processing circuit 100, the first TVS tube D1 is coupled to the first output terminal and the second output terminal of the first common-mode inductor L2, the fifth capacitor C31 is coupled to the two ends of the first TVS tube D1, the sixth capacitor C41 and the seventh capacitor C42 are connected in series, one end of the sixth capacitor C41 is coupled to the second input terminal of the first common-mode inductor L2, and the other end of the sixth capacitor C41 is coupled to the seventh capacitor C42 and grounded.

[0042] The coupling point between the first TVS diode D1 and the fifth capacitor C31 serves as the second output terminal of the power control circuit 10 , and is used to provide a power signal requiring common-mode filtering to a subsequent isolated communication circuit.

[0043] The second common-mode filtering circuit 312 includes a second common-mode inductor L3, a fifth capacitor unit C5, and a sixth capacitor unit C6; a first input end of the second common-mode inductor L3 is coupled to the second output end of the first-stage differential-mode processing circuit 100, and a first output end of the second common-mode inductor L3 is coupled to the second TVS diode D3; a first end of the fifth capacitor unit C5 is coupled to the second input end of the second common-mode inductor L3, and a second end of the fifth capacitor unit C5 is grounded; a first end of the sixth capacitor unit C6 is coupled to the second output end of the second common-mode inductor L3, and a second end of the sixth capacitor unit C6 is grounded.

[0044] The fifth capacitor unit C5 includes at least two capacitors connected in series, such as an eighth capacitor C51 and a ninth capacitor C52 connected in series; the sixth capacitor unit C6 includes at least two capacitors connected in series, such as a tenth capacitor C61 and an eleventh capacitor C62 connected in series.

[0045] Furthermore, the second common-mode filter circuit 312 also includes: a seventh capacitor unit C7 and an eighth capacitor unit C8; a first end of the seventh capacitor unit C7 is coupled to the first output end of the second common-mode inductor L3, and a second end of the seventh capacitor unit C7 is coupled to the second output end of the second common-mode inductor L3; the eighth capacitor unit C8 is connected in parallel to both ends of the second TVS tube D3.

[0046] The seventh capacitor unit C7 includes at least two capacitors connected in parallel, such as a twelfth capacitor C71 and a thirteenth capacitor C72 connected in parallel; the eighth capacitor unit C8 includes at least one capacitor, such as a fourteenth capacitor C81.

[0047] Specifically, the fifth capacitor unit C5 includes an eighth capacitor C51 and a ninth capacitor C52, the sixth capacitor unit C6 includes a tenth capacitor C61 and an eleventh capacitor C62, the seventh capacitor unit C7 includes a twelfth capacitor C71 and a thirteenth capacitor C72, and the eighth capacitor unit C8 includes a fourteenth capacitor C81 as an example for description: the first input terminal and the second input terminal of the second common-mode inductor L3 are coupled to both ends of the fourth capacitor C22, one end of the eighth capacitor C51 is coupled to the second input terminal of the second common-mode inductor L3, and the other end of the eighth capacitor C51 is coupled to the ninth capacitor C52 and grounded; one end of the tenth capacitor C61 is coupled to the second output terminal of the second common-mode inductor L3, and the other end of the tenth capacitor C61 is coupled to the eleventh capacitor C62 and grounded; the twelfth capacitor C71 and the thirteenth capacitor C72 are connected in parallel and in parallel to the first output terminal and the second output terminal of the second common-mode inductor L3; the second TVS diode D3 is coupled to both ends of the thirteenth capacitor C72, and the fourteenth capacitor C81 is coupled to both ends of the second TVS diode D3.

[0048] In some embodiments, the fifth capacitor unit C5 can be shared with the fourth capacitor unit C4, that is, the fifth capacitor unit C5 can be the fourth capacitor unit C4, the sixth capacitor C41 can be the eighth capacitor C51, and the seventh capacitor C42 can be the ninth capacitor C52. Only one capacitor unit C5 can be used.

[0049] The coupling point between the second TVS diode D3 and the fourteenth capacitor C81 serves as the third output terminal of the power control circuit 10 , for providing a power signal with higher filtering requirements to the subsequent AIAO circuit and / or CPU circuit.

[0050] The second-stage differential mode processing circuit 200 includes a ninth capacitor unit C9 and a third TVS diode D3. The first end of the ninth capacitor unit C9 is coupled to the first output end of the first-stage differential mode processing circuit 100, and the second end of the ninth capacitor unit C9 is coupled to the loop. The third TVS diode D3 is connected in parallel with the ninth capacitor unit C9, and the connection point between the ninth capacitor unit C9 and the third TVS diode serves as the first output end of the power control circuit 10.

[0051] The ninth capacitor unit C9 includes at least one capacitor, such as a fifteenth capacitor C91.

[0052] Specifically, the ninth capacitor unit C9 includes the fifteenth capacitor C91 as an example for explanation: one end of the fifteenth capacitor C91 is coupled to the first output end of the first-stage differential mode processing circuit 100, that is, the fifteenth capacitor C91 is coupled to the second capacitor C12, and the other end of the fifteenth capacitor C91 is coupled to the loop. The third TVS tube D3 is connected in parallel at both ends of the fifteenth capacitor C91, and the connection point between the third TVS tube D3 and the fifteenth capacitor C91 serves as the first output end of the power control circuit 10, which is used to output the power signal after the second-stage differential mode processing circuit 200 performs the second-stage differential mode processing, and output it to the subsequent DIDO circuit.

[0053] That is, the first output end of the power control circuit 10 corresponds to the DIDO circuit 24V1, the second output end of the power control circuit 10 corresponds to the isolated communication circuit 24V4, and the third output end of the power control circuit 10 corresponds to the AIAO circuit 24V2 and the CPU circuit 24V3.

[0054] Among them, DIDO circuit 24V1 not only identifies the power output port of the DIDO circuit, but also identifies its voltage as 24V; isolated communication circuit 24V4 not only identifies the power output port of the isolated communication circuit, but also identifies its voltage as 24V; AIAO circuit 24V2 not only identifies the power output port of the AIAO circuit, but also identifies its voltage as 24V; CPU circuit 24V3 not only identifies the power output port of the CPU circuit, but also identifies its voltage as 24V.

[0055] Furthermore, the power control circuit 10 further includes a resistor R, which is coupled to the input end of the first-stage differential mode processing circuit and is configured to suppress the differential mode surge signal.

[0056] The resistor R may be a varistor, which plays a primary role in preventing differential-mode surges, and the third TVS diode D3 plays a secondary role in preventing differential-mode surges for the subsequent DIDO circuit.

[0057] In some embodiments, a power input module 400 may be further included for inputting a power signal.

[0058] Specifically, one end of the resistor R is coupled to the output end of the power input module 400, and the other end of the resistor R is coupled to the loop to the power input module. One end of the differential mode inductor L1 is coupled to the output end of the power input module 400, and the other end of the differential mode inductor L1 is coupled to the input end of the first-stage differential mode processing circuit 100, and the first-stage differential mode processing circuit 100 is coupled to the loop to the power input module 400; the second input end of the first common mode inductor L2 is coupled to the loop to the power input module 400, and the second input end of the second common mode inductor L3 is coupled to the loop to the power input module 400.

[0059] In this embodiment, the power supply signal is first subjected to differential-mode filtering, and then different filtering processes are set according to the filtering requirements of subsequent partial circuits. For example, the partial circuits that require differential-mode filtering are then set to the second-stage differential-mode filtering, and the partial circuits that require common-mode filtering are then set to the common-mode filtering, so as to filter out the clutter interference caused by the power supply of the power grid in the front-end power supply, so that the power supply control circuit can effectively prevent the impact of surges on the circuit, reduce the probability of damage to the components in the circuit, and improve the service life of the power supply.

[0060] See Figure 3 , Figure 3 It is a schematic diagram of the circuit structure of the interference transmission path in this application.

[0061] like Figure 3 As shown, in Figure 2 On the basis of FIG, a BUCK chip is added, wherein the BUCK chip is coupled to both ends of the first TVS tube D1, and the BUCK chip is coupled to the sixteenth capacitor C10 and grounded.

[0062] The first interference path is as follows: the interference source starts from the buck chip, passes through the sixteenth capacitor C10 on the ground line PE (Protecting Earth), reaches the eleventh capacitor C62 and the tenth capacitor C61 on the ground line PE, then to the thirteenth capacitor C72 and the twelfth capacitor C71, and returns to the buck chip. The second interference path is as follows: the interference source starts from the buck chip, passes through the sixteenth capacitor C10 on the ground line PE (Protecting Earth), reaches the ninth capacitor C52 and the eighth capacitor C51 on the ground line PE, then to the first capacitor C11 and the second capacitor C12, then to the first common-mode inductor L2, and returns to the buck chip.

[0063] The power control circuit of the present application simply and effectively solves the technical problems that the 24V isolated power input to ground Y capacitor of the traditional programmable logic controller introduces the common-mode noise of the switching power supply MOS tube into the LISN, resulting in excessive emission and differential-mode surge damage to the subsequent TVS tube.

[0064] refer to Figure 4 , Figure 4 Schematic diagram of the circuit structure of the differential mode surge transmission path in this application.

[0065] like Figure 4 As shown, based on Figure 3 The differential-mode surge signal enters the power control circuit 10 from the power input module, forming a large differential-mode surge signal. The differential-mode inductor of the first-stage differential-mode processing circuit plays a decoupling and voltage-dividing role, reducing the stress of the subsequent circuit, simplifying the circuit and control, improving the reliability of the power supply, and reducing the failure rate caused by a single fault in the power control circuit.

[0066] The present application also provides a power supply circuit 1 , which includes the above-mentioned power supply control circuit 10 .

[0067] See Figure 5 , Figure 5 It is a structural diagram of an embodiment of a power supply circuit in this application.

[0068] The present application also provides a chip 2 , which includes the above-mentioned power control circuit 10 .

[0069] See Figure 6 , Figure 6 It is a structural diagram of a chip embodiment in this application.

[0070] Compared with the 24V isolated power supply of the traditional programmable logic controller in the current technology, the present application provides an anti-interference circuit used in a 24V DC power supply control system. The network transformer is omitted from the circuit, the interference source MOS tube is removed, and only the interference source BUCK chip is retained. This solves the technical problems that the Y capacitor to ground at the front end of the 24V isolated power supply input of the traditional programmable logic controller will introduce interference into the LISN and the differential mode surge will damage the TVS tube in the DIDO circuit; and the entire 24V power supply circuit is greatly simplified, thereby reducing the PCB area and improving the system power density; the circuit is simplified, so the reliability is higher, and the failure rate caused by a single fault in the control circuit is reduced.

[0071] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0072] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0073] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A power supply control circuit, characterized in that: The power control circuit includes: a first-stage differential mode processing circuit, wherein an input end of the first-stage differential mode processing circuit receives a power supply signal and is configured to perform differential mode filtering on the power supply signal; a second-stage differential mode processing circuit, coupled to the first output terminal of the first-stage differential mode processing circuit, for performing differential mode filtering on the power signal, wherein the output terminal of the second-stage differential mode processing circuit serves as the first output terminal of the power control circuit; A common mode processing circuit is coupled to the second output terminal of the first differential mode processing circuit and is used to perform common mode filtering on the power signal, wherein the output terminal of the common mode processing circuit serves as the second output terminal of the power control circuit.

2. The power supply control circuit according to claim 1, wherein: The first-stage differential mode processing circuit includes: a differential mode inductor, wherein an input end of the differential mode inductor receives the power signal; a first capacitor unit, the first capacitor unit being coupled to the output end of the differential mode inductor, the second end of the first capacitor unit serving as the first output end of the first-stage differential mode processing circuit, wherein the first capacitor unit includes at least two capacitors connected in parallel; A second capacitor unit, wherein the first end of the second capacitor unit is coupled to the second end of the first capacitor unit, and the second end of the second capacitor unit serves as the second output end of the first differential mode processing circuit, wherein the second capacitor unit includes at least two capacitors in parallel.

3. The power supply control circuit according to claim 1, wherein: The common mode processing circuit includes: a common-mode filtering circuit, wherein an input terminal of the common-mode filtering circuit is coupled to the second output terminal of the first-stage differential-mode processing circuit; A TVS tube coupled to the output end of the common-mode filter circuit; The connection point between the common-mode filtering circuit and the TVS tube serves as the output end of the common-mode processing circuit, and is used to output the power signal after common-mode filtering.

4. The power supply control circuit according to claim 3, wherein: The common-mode filter circuit includes a first common-mode filter circuit and a second common-mode filter circuit; the power control circuit further includes a third output terminal; the TVS tube includes a first TVS tube and a second TVS tube; The input end of the first common-mode filter circuit is coupled to the second output end of the first differential-mode processing circuit; the first TVS diode is coupled to the output end of the first common-mode filter circuit, which is coupled as the second output end of the power control circuit; The input end of the second common-mode filter circuit is coupled to the second output end of the first differential-mode processing circuit; the second TVS tube is coupled to the output end of the second common-mode filter circuit, which is coupled to the third output end of the power control circuit.

5. The power supply control circuit according to claim 4, wherein: The first common-mode filtering circuit includes: a first common-mode inductor, wherein a first input end of the first common-mode inductor is coupled to the second output end of the first-stage differential-mode processing circuit, and a first output end of the first common-mode inductor is coupled to the first TVS diode; a third capacitor unit, coupled to both ends of the first TVS tube, wherein the third capacitor unit includes at least one capacitor; A fourth capacitor unit, wherein a first end of the fourth capacitor unit is coupled to the second input end of the first common-mode inductor, and a second end of the fourth capacitor unit is grounded, wherein the fourth capacitor unit includes at least two capacitors connected in series.

6. The power supply control circuit according to claim 4, wherein: The second common-mode filtering circuit includes: a second common-mode inductor, wherein a first input end of the second common-mode inductor is coupled to the second output end of the first-stage differential-mode processing circuit, and a first output end of the second common-mode inductor is coupled to the second TVS diode; a fifth capacitor unit, wherein a first end of the fifth capacitor unit is coupled to the second input end of the second common-mode inductor, and a second end of the fifth capacitor unit is grounded, wherein the fifth capacitor unit includes at least two capacitors connected in series; A sixth capacitor unit, wherein a first end of the sixth capacitor unit is coupled to the second output end of the second common-mode inductor, and a second end of the sixth capacitor unit is grounded, wherein the sixth capacitor unit includes at least two capacitors connected in series.

7. The power supply control circuit according to claim 6, wherein: The second common-mode filtering circuit further includes: a seventh capacitor unit, wherein a first end of the seventh capacitor unit is coupled to the first output end of the second common-mode inductor, and a second end of the seventh capacitor unit is coupled to the second output end of the second common-mode inductor, wherein the seventh capacitor unit includes at least two capacitors connected in parallel; An eighth capacitor unit is connected in parallel to both ends of the second TVS tube, wherein the eighth capacitor unit includes at least one capacitor.

8. The power supply control circuit according to claim 3, wherein: The second-stage differential mode processing circuit includes: a ninth capacitor unit, wherein a first end of the ninth capacitor unit is coupled to the first output end of the first-stage differential mode processing circuit, a second end of the ninth capacitor unit is coupled to the loop, and the ninth capacitor unit includes at least one capacitor; a third TVS tube, connected in parallel with the ninth capacitor unit; Wherein, the connection point between the ninth capacitor unit and the third TVS tube serves as the first output end of the power control circuit.

9. The power control circuit according to claim 1, wherein: Also includes: The resistor is coupled to the input end of the first-stage differential mode processing circuit and is configured to suppress the differential mode surge signal.

10. A power supply circuit, characterized in that: The invention comprises the power supply control circuit according to any one of claims 1 to 9.

11. A chip, characterized in that: The invention comprises the power supply control circuit according to any one of claims 1 to 9.

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