Modulation circuit
By introducing a delay control and digitally controlled dead zone module into the modulation circuit of the GaN power amplifier, the problem of simultaneous conduction of the power tube and the pull-down tube is solved, the safe operation of the circuit is achieved, and damage to the circuit structure is avoided.
Patent Information
- Application Number
- CN202422278797.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-18
- Publication Date
- 2025-09-16
- Estimated Expiration
- 2034-09-18
AI Technical Summary
In existing GaN power amplifier modulation circuits, the power transistor and the pull-down transistor are easily turned on at the same time, resulting in a large current to ground, which may cause the circuit structure to burn out.
By designing a modulation circuit, including a power tube, a pull-down tube, a power control module, a first AND gate, a high-voltage to low-voltage module and a pull-down control module, a delay measure is used to control the on and off of the power tube and the pull-down tube to prevent them from being turned on at the same time, and the dead zone time is adjusted through the dead zone module and the digital control tube to adapt to different load changes.
It effectively prevents the power tube and the pull-down tube from being turned on at the same time, avoids a large current to ground, protects the circuit structure from being burned, and realizes safe and reliable circuit operation.
Smart Images
Figure CN223348662U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of circuits, and in particular to a modulation circuit. Background Art
[0002] Gallium nitride (GaN), an inorganic compound with the chemical formula GaN, is a compound of nitrogen and gallium. It is a direct bandgap semiconductor and has been widely used in communications, radar, base stations, and semiconductors. GaN-based power amplifiers are already able to meet basic communication needs. However, to further achieve wide bandgap and high efficiency, the modulation circuits connected to the GaN power amplifiers require higher standards. This can be achieved by carefully selecting the power transistors in the modulation circuits.
[0003] However, in the existing solution, different power tubes have different load capacities, resulting in different corresponding equivalent parasitic capacitances. The equivalent parasitic capacitance of the pull-down tube is relatively small, and it is easy for the power tube and the pull-down tube to be turned on at the same time, which will generate a large current to the ground, causing the circuit structure to be burned due to the heat accumulation generated by the large current. Utility Model Content
[0004] An embodiment of the present application provides a modulation circuit for preventing a power transistor and a pull-down transistor from being turned on at the same time.
[0005] A first aspect of an embodiment of the present application provides a modulation circuit, comprising: a power tube, a pull-down tube, a power control module, a first AND gate, a high-voltage to low-voltage module, and a pull-down control module;
[0006] The input end of the power control module is the total input end of the circuit, and the first output end of the power control module is connected to the control end of the power tube and the input end of the high-voltage to low-voltage conversion module respectively. The power control module is used to adjust the level value of the control end of the power tube according to the voltage value of the total input end;
[0007] The output end of the high-voltage to low-voltage module is connected to the first input end of the first AND gate, the total input end is connected to the second input end of the first AND gate via the pull-down control module, the output end of the first AND gate is connected to the control end of the pull-down tube, and the non-control end of the power tube is grounded via the non-control end of the pull-down tube, so as to control the on and off of the pull-down tube according to the voltage value and the level value, thereby ensuring that the power tube and the pull-down tube are not turned on at the same time.
[0008] Optionally, the circuit further includes: a first inverter and a dead zone module;
[0009] The first inverter is connected in series with the dead zone module, and the output end of the high-voltage-to-low-voltage conversion module is connected to the first input end of the first AND gate via the first inverter and the dead zone module, so that the level value of the first input end of the first AND gate is consistent with the level value of the output end of the high-voltage-to-low-voltage conversion module.
[0010] Optionally, the dead zone module includes: a first Pmos transistor, a first Nmos transistor and a first capacitor;
[0011] The gate of the first Pmos transistor is connected to the gate of the first Nmos transistor, and the gate of the first Pmos transistor and the gate of the first Nmos transistor both serve as input ends of the dead zone module;
[0012] The source of the first Pmos transistor is connected to the positive power supply terminal, the drain of the first Pmos transistor is respectively connected to the drain of the first Nmos transistor and the first end of the first capacitor, the source of the first Nmos transistor and the second end of the first capacitor are both grounded, and the first end of the first capacitor serves as the output end of the dead zone module.
[0013] Optionally, the dead zone module further includes: a second PMOS tube and at least one digital control tube;
[0014] The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the source of the second PMOS transistor is connected to the positive power supply terminal, so that the first PMOS transistor is connected to the positive power supply terminal via the second PMOS transistor;
[0015] The control end of each digital control tube is connected to a different external chip port, and the two non-control ends of the at least one digital control tube are connected in parallel to the source and drain of the second PMOS tube. Under the premise of a fixed power supply, the current provided by each digital control tube is different.
[0016] Optionally, the power control module includes: a low voltage to high voltage submodule and a selection submodule;
[0017] The input end of the low-voltage to high-voltage submodule is the total input end, the output end of the low-voltage to high-voltage submodule is connected to the input end of the selection submodule, and the output end of the selection submodule is connected to the control end of the power tube. The selection submodule is used to determine the level value of the control end of the power tube according to the output signal of the low-voltage to high-voltage submodule.
[0018] Optionally, the pull-down control module includes: a second inverter;
[0019] The input terminal of the second inverter serves as the total input terminal, and the output terminal of the second inverter is connected to the second input terminal of the first AND gate.
[0020] Optionally, the power control module includes: a selection submodule;
[0021] The input end of the selection submodule serves as the main input end, and the output end of the selection submodule is connected to the control end of the power tube.
[0022] Optionally, the pull-down control module includes: a second inverter and a high-voltage to low-voltage sub-module;
[0023] The second inverter and the high-voltage-to-low-voltage submodule are connected in series, and the total input end is connected to the second input end of the first AND gate via the second inverter and the high-voltage-to-low-voltage submodule.
[0024] Optionally, the selection submodule includes: a non-overlapping clock unit, a third Pmos transistor and a second Nmos transistor;
[0025] The input end of the non-overlapping clock unit serves as the input end of the selection submodule, the first output end of the non-overlapping clock unit is connected to the gate of the third Pmos tube, the source of the third Pmos tube is connected to the positive electrode of the power supply, the drain of the third Pmos tube is respectively connected to the control end of the power tube, the input end of the high-voltage to low-voltage module and the drain of the second Nmos tube, the second output end of the non-overlapping clock unit is connected to the gate of the second Nmos tube, and the source of the second Nmos tube is connected to the negative electrode of the power supply.
[0026] Optionally, the non-overlapping clock unit includes: a first branch and a second branch;
[0027] The first branch includes a first OR gate and a branch inverters, wherein the first input end of the first OR gate serves as the input end of the non-overlapping clock unit, the first OR gate and the a branch inverters are sequentially connected in series, and the output end of the last branch inverter of the first branch serves as the first output end of the non-overlapping clock unit;
[0028] The second branch includes a first AND gate and b branch inverters, wherein the first input end of the first AND gate serves as the input end of the non-overlapping clock unit, the first AND gate and the b branch inverters are sequentially connected in series, and the output end of the last branch inverter of the second branch serves as the second output end of the non-overlapping clock unit;
[0029] The output end of the cth branch inverter in the first branch close to the first OR gate is connected to the second input end of the first AND gate, and the output end of the dth branch inverter in the second branch close to the first AND gate is connected to the second input end of the first OR gate, where a, b, c and d are all positive even numbers, and a≥c, b≥d.
[0030] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:
[0031] When the voltage at the total input changes, causing the second input of the first AND gate to be high, the voltage at the control terminal of the power transistor is also required to determine the voltage level. After the voltage determines the voltage level, if the voltage level is 1 (i.e., high), the voltage signal is converted and delayed by the high-voltage-to-low-voltage converter and reaches the first input of the first AND gate. The first AND gate then outputs a high voltage. However, this high voltage has been delayed by the high-voltage-to-low-voltage converter and is slower than the signal at the control terminal of the power transistor. Therefore, the power transistor and the pull-down transistor are not turned on at the same time. Because the number of components from the total input to the second input of the first AND gate is smaller and simpler than the number from the total input to the control terminal of the power transistor, the power control module has a greater delay than the pull-down control module. If the voltage at the total input changes, causing the second input of the first AND gate to be low, the pull-down transistor will operate faster than the power transistor, so the power transistor and the pull-down transistor are not turned on at the same time. When the power transistor is turned on, the pull-down transistor is turned off, and when the power transistor is turned off, the pull-down transistor is turned on. This prevents the generation of large ground currents and prevents excessive heat from damaging the circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 A schematic diagram of an embodiment of a modulation circuit disclosed in this application;
[0033] Figure 2 This is a schematic diagram of another embodiment of a modulation circuit disclosed in this application;
[0034] Figure 3 This is a schematic diagram of an embodiment of a dead zone module disclosed in this application;
[0035] Figure 4 This is a schematic diagram of an embodiment of a non-overlapping clock unit disclosed in this application;
[0036] Figure 5 This is a dead time simulation schematic diagram disclosed in this application;
[0037] Figure 6 This is a simulation diagram of a dead time digital control disclosed in this application. DETAILED DESCRIPTION
[0038] The present application is further described in detail below with reference to the accompanying drawings.
[0039] An embodiment of the present application provides a modulation circuit for preventing a power transistor and a pull-down transistor from being turned on at the same time.
[0040] Gallium nitride-based power amplifiers have been widely used in various industries. In order to further achieve the effects of wide bandgap and high efficiency, this can be achieved through a modulation circuit. However, in existing solutions, the power tube and the pull-down tube in the modulation circuit are prone to being turned on at the same time. When the power tube and the pull-down tube are turned on at the same time, a large current to the ground will be generated, thereby burning the device. In order to solve the above problem, the present application provides a modulation circuit that can take delay measures for some signals, so that the power tube and the pull-down tube will not be turned on at the same time, preventing the generation of a large current to the ground, and not causing the device to burn, thereby ensuring safety.
[0041] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0042] The terms "first," "second," "third," "fourth," and so forth, in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments described herein can be practiced in an order other than that illustrated or described herein. Furthermore, the terms "including," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions.
[0043] The following describes a modulation circuit of the present application. Figure 1 , an embodiment of a modulation circuit of the present application includes: a power tube, a pull-down tube, a power control module, a first AND gate, a high-voltage to low-voltage module and a pull-down control module;
[0044] The input end of the power control module is the total input end of the circuit, and the first output end of the power control module is connected to the control end of the power tube and the input end of the high-voltage to low-voltage conversion module respectively. The power control module is used to adjust the level value of the control end of the power tube according to the voltage value of the total input end;
[0045] The output end of the high-voltage to low-voltage module is connected to the first input end of the first AND gate, the total input end is connected to the second input end of the first AND gate via the pull-down control module, the output end of the first AND gate is connected to the control end of the pull-down tube, and the non-control end of the power tube is grounded via the non-control end of the pull-down tube, so as to control the on and off of the pull-down tube according to the voltage value and the level value, thereby ensuring that the power tube and the pull-down tube are not turned on at the same time.
[0046] In the embodiment of the present application, when the voltage at the total input changes, causing the second input of the first AND gate to be high, the voltage at the control terminal of the power transistor is also required to determine the voltage level. After the voltage value determines the voltage level, when the voltage level is 1 (i.e., high), the voltage signal is converted and delayed by the high-voltage-to-low-voltage module and reaches the first input of the first AND gate. The first AND gate then outputs a high voltage. However, this high voltage has been delayed by the high-voltage-to-low-voltage module and is slower than the signal at the control terminal of the power transistor. Therefore, the power transistor and the pull-down transistor are not turned on at the same time. Because the number of components from the total input to the second input of the first AND gate is smaller and simpler than the number of components from the total input to the control terminal of the power transistor, the power control module has a greater delay than the pull-down control module. If the voltage at the total input changes, causing the second input of the first AND gate to be low, the pull-down transistor will operate faster than the power transistor, so the power transistor and the pull-down transistor are not turned on at the same time. When the power transistor is turned on, the pull-down transistor is turned off, and when the power transistor is turned off, the pull-down transistor is turned on. This prevents the generation of large ground currents and prevents the circuit structure from being damaged by excessive heat.
[0047] It is understandable that the power tube of the present application can be a Pmos tube, or an Nmos tube or other tube, which can be selected according to actual needs and is not limited here. The pull-down tube can be an Nmos tube or a Pmos tube and other types, which are not limited here. For the convenience of explanation, the following describes another embodiment of the modulation circuit of the present application by taking the power tube as a Pmos tube and the pull-down tube as an Nmos tube as an example. Figures 2 to 4 Another embodiment of a modulation circuit in the embodiment of the present application includes: a power tube P, a pull-down tube X, a power control module, a first AND gate A1, a high-voltage to low-voltage module, a pull-down control module first inverter I1 and a dead zone module;
[0048] The input end of the power control module serves as the total input end of the circuit. The first output end of the power control module is connected to the control end of the power tube P and the input end of the high-voltage-to-low-voltage conversion module, respectively. The power control module is configured to adjust the voltage level of the control end of the power tube P based on the voltage value of the total input end. Specifically, the first output end of the power control module is connected to the gate of the power tube P, the source of the power tube P is connected to the positive power supply AVDD, and the drain of the power tube P serves as the total output end of the circuit. The voltage at the total input end can affect the voltage level of the gate of the power tube P.
[0049] The output end of the high-voltage to low-voltage conversion module is connected to the first input end of the first AND gate A1, the total input end is connected to the second input end of the first AND gate A1 via the pull-down control module, the output end of the first AND gate A1 is connected to the control end of the pull-down tube X, and the non-control end of the power tube P is grounded via the non-control end of the pull-down tube X, so that the on and off of the pull-down tube X is controlled according to the voltage value and the level value, thereby ensuring that the power tube P and the pull-down tube X are not turned on at the same time.
[0050] The first inverter I1 is connected in series with the dead-zone module. The output of the high-voltage-to-low-voltage conversion module is connected to the first input of the first AND gate A1 via the first inverter I1 and the dead-zone module, such that the voltage level at the first input of the first AND gate A1 is consistent with the voltage level at the output of the high-voltage-to-low-voltage conversion module. In this embodiment, specifically, the gate of the power transistor P is connected to the first input of the first AND gate A1 via the high-voltage-to-low-voltage conversion module, the first inverter I1, and the dead-zone module. The drain of the pull-down transistor X is connected to the drain of the power transistor P. The gate of the pull-down transistor X is the output of the first AND gate A1, and the source of the pull-down transistor X is grounded.
[0051] The dead zone module includes: a first Pmos transistor Q1, a first Nmos transistor Q2, a first capacitor C, a second Pmos transistor Q3 and at least one digital control transistor;
[0052] The gate of the first PMOS transistor Q1 is connected to the gate of the first NMOS transistor Q2, and both the gate of the first PMOS transistor Q1 and the gate of the first NMOS transistor Q2 serve as the input of the dead zone module. In this embodiment, the input of the dead zone module is connected to the output of the first inverter I1, and the output of the dead zone module is connected to the first input of the first AND gate A1.
[0053] The source of the first Pmos transistor Q1 is connected to the positive power supply terminal, the drain of the first Pmos transistor Q1 is connected to the drain of the first Nmos transistor Q2 and the first end of the first capacitor C respectively, the source of the first Nmos transistor Q2 and the second end of the first capacitor C are both grounded, and the first end of the first capacitor C serves as the output end of the dead zone module.
[0054] In the existing technical solution, a traditional non-overlapping clock is used for delay. However, the corresponding dead time is fixed and cannot be adjusted accordingly according to changes in the load. To solve this problem, the dead time module of the present application can adaptively adjust the dead time according to the power tubes P of different sizes, which is achieved by the newly added second Pmos tube Q3 and the digital control tube. Specifically, the gate of the second Pmos tube Q3 is connected to the gate of the first Pmos tube Q1, the source of the first Pmos tube Q1 is connected to the drain of the second Pmos tube Q3, and the source of the second Pmos tube Q3 is connected to the positive power supply terminal, so that the first Pmos tube Q1 is connected to the positive power supply terminal through the second Pmos tube Q3. The control terminal of each digital control tube is connected to a different external chip port, and the two non-control terminals of the at least one digital control tube are connected in parallel to the source and drain of the second PMOS transistor Q3. Under the premise of a fixed power supply, each digital control tube provides a different current, resulting in a different total current charging the first capacitor C, thereby affecting the charging speed of the first capacitor C and the voltage rise rate of the output terminal of the dead zone module. Furthermore, the number of digital control tubes can be set according to actual needs and is not specifically limited here. For ease of understanding, this embodiment illustrates three digital control tubes.
[0055] The voltage at the total input terminal is high or low, and the situation is slightly different. If the voltage value of the total input terminal is low voltage, the power control module includes: a low voltage to high voltage submodule and a selection submodule, and the pull-down control module includes: a second inverter I2;
[0056] The input end of the low-voltage-to-high-voltage submodule is the total input end, the output end of the low-voltage-to-high-voltage submodule is connected to the input end of the selection submodule, and the output end of the selection submodule is connected to the control end of the power tube P. The selection submodule is used to determine the voltage level of the control end of the power tube P based on the output signal of the low-voltage-to-high-voltage submodule. The low-voltage-to-high-voltage module is used to convert the low voltage at the total input end into a high voltage that can be used by the selection submodule and the power tube P. Specifically, the positive pole of the power supply is used to power both the low-voltage-to-high-voltage module and the selection submodule, and the output end of the selection submodule is connected to the gate of the power tube P.
[0057] An input terminal of the second inverter I2 serves as the total input terminal, and an output terminal of the second inverter I2 is connected to the second input terminal of the first AND gate A1.
[0058] If the voltage value of the total input terminal is high voltage, the power control module includes: a selection submodule, and the pull-down control module includes: a second inverter I2 and a high voltage to low voltage submodule;
[0059] The input end of the selection submodule serves as the main input end, and the output end of the selection submodule is connected to the control end of the power tube P.
[0060] The second inverter I2 and the high-voltage-to-low-voltage submodule are connected in series, and the total input end is connected to the second input end of the first AND gate A1 via the second inverter I2 and the high-voltage-to-low-voltage submodule.
[0061] In this embodiment, the case where the total input terminal is at a low voltage is described.
[0062] The selection submodule in the power control module includes: a non-overlapping clock unit, a third Pmos transistor Q4 and a second Nmos transistor Q5;
[0063] The input of the non-overlapping clock unit serves as the input of the selection submodule. The first output of the non-overlapping clock unit is connected to the gate of the third PMOS transistor Q4. The source of the third PMOS transistor Q4 is connected to the positive power supply AVDD. The drain of the third PMOS transistor Q4 is connected to the control terminal of the power transistor P, the input of the high-voltage-to-low-voltage module, and the drain of the second NMOS transistor Q5. The second output of the non-overlapping clock unit is connected to the gate of the second NMOS transistor Q5, and the source of the second NMOS transistor Q5 is connected to the negative power supply VL. Specifically, the positive power supply provides power to the non-overlapping clock unit. The drain of the third PMOS transistor Q4 is connected to the drain of the second NMOS transistor Q5 and the gate of the power transistor P. The non-overlapping clock unit can implement a time delay, so that the third PMOS transistor Q4 and the second NMOS transistor Q5 are not turned on at the same time, thus preventing device burnout.
[0064] Wherein, the non-overlapping clock unit includes: a first branch and a second branch;
[0065] The first branch includes a first OR gate and a branch inverters, wherein the first input end of the first OR gate serves as the input end of the non-overlapping clock unit, the first OR gate and the a branch inverters are sequentially connected in series, and the output end of the last branch inverter of the first branch serves as the first output end of the non-overlapping clock unit;
[0066] The second branch includes a first AND gate A1 and b branch inverters, wherein the first input end of the first AND gate A1 serves as the input end of the non-overlapping clock unit, the first AND gate A1 and the b branch inverters are sequentially connected in series, and the output end of the last branch inverter of the second branch serves as the second output end of the non-overlapping clock unit;
[0067] The output terminal of the cth inverter in the first branch, which is close to the first OR gate, is connected to the second input terminal of the first AND gate A1. The output terminal of the dth inverter in the second branch, which is close to the first AND gate A1, is connected to the second input terminal of the first OR gate. Here, a, b, c, and d are all positive even numbers, and a ≥ c and b ≥ d. In this embodiment, a and b are 4, and c and d are 2.
[0068] The working principle of the power control module of this embodiment is described below. Figures 2 to 6 If the voltage at the total input drops from a high level to a low level, the output of the low-voltage to high-voltage submodule also drops to a low level. In the non-overlapping clock unit, since the second branch contains the second AND gate A2 and the first branch contains the first OR gate, the second AND gate A2 immediately activates and outputs a low level when the input of the non-overlapping clock unit is low. Meanwhile, the first OR gate still has one input at a high level, so the first OR gate outputs a high level. Only when the inverter output of the second branch, which is close to the second AND gate A2, drops to a low level does the first OR gate output a low level. As a result, the output of the second branch drops from a high level to a low level faster than that of the first branch. Therefore, the gate of the second NMOS transistor Q5 drops to a low level first, turning off the second NMOS transistor Q5. Then, the gate of the third PMOS transistor Q4 drops to a low level, turning on the third PMOS transistor Q4. After the third PMOS transistor Q4 turns on, the gate voltage of the power transistor P is pulled up to near AVDD, turning off the power transistor P and the total output voltage is zero. If the voltage at the total input end rises from a low level to a high level, the output end of the low-voltage to high-voltage sub-module is also a high level. In the non-overlapping clock unit, the first OR gate outputs a high level as long as one of its input ends is high, while the second AND gate A2 requires both input ends to be high to output a high level. Therefore, the first OR gate outputs a high level first, while the second AND gate A2 still outputs a low level. When the output end of the second branch inverter of the first branch close to the first OR gate is high, the second AND gate A2 outputs a high level. It can be seen that the third Pmos tube Q4 is turned off first, and the second Nmos tube Q5 is turned on. The gate of the power tube P is pulled down to a low level, the power tube P is turned on, and the voltage at the total output end is a high level.
[0069] The following describes the digital control principle of the dead zone module. When the total input jumps from a high level to a low level, the gate of the power tube P is at a high level. After the action of the first inverter I1, the input of the dead zone module is at a low level, and the first PMOS tube Q1 and the second PMOS tube Q3 are turned on. At this time, the external digital control tube can be controlled to adjust the charging current of the first capacitor C. Figure 3Counting from left to right in the figure, the size ratio of the digital control tube is 1:2:4, and the currents they can provide are 0x, 1x, 2x, 3x, 4x, 5x, 6x, and 7x (3-bit control), respectively. The greater the charging current of the first capacitor C, the faster the charging speed of the first capacitor C, the faster the voltage at the output of the dead zone module rises, the faster the gate voltage of the pull-down tube X rises, and the shorter the dead zone time. The smaller the charging current of the first capacitor C, the slower the charging speed of the first capacitor C, the slower the voltage at the output of the dead zone module rises, the slower the gate voltage of the pull-down tube X rises, and the longer the dead zone time.
[0070] The operating principle of this embodiment is described below. Because the number of components from the total input to the second input of the first AND gate A1 is smaller and simpler than the number of components from the total input to the gate of the power transistor P, the signal speed at the second input of the first AND gate A1 is faster than the signal speed at the gate of the power transistor P. Furthermore, the number of components from the total input to the gate of the power transistor P is smaller and simpler than the number of components from the total input to the gate of the power transistor P, so the signal speed at the gate of the power transistor P is faster than the signal speed at the first input of the first AND gate A1. Therefore, when the total input changes from a high level to a low level, although the second input of the first AND gate A1 reaches a high level before the gate of the power transistor P, the gate of the power transistor P reaches a high level before the first input of the first AND gate A1. Since the high-level output of the first AND gate A1 is determined by both high-level inputs, the power transistor P is turned off first, and the pull-down transistor X is turned on later. When the total input terminal changes from a low level to a high level, the second input terminal of the first AND gate A1 is first at a low level. As long as one of the input terminals of the first AND gate A1 is at a low level, the output terminal of the first AND gate A1 will immediately output a low level. Therefore, no matter what the level of the first input terminal of the first AND gate A1 is, the output terminal of the first AND gate A1 will change to a low level before the gate of the power tube P. The pull-down tube X will be turned off first, and the power tube P will be turned on later.
[0071] In this embodiment, the power tube P and the pull-down tube X can be turned on at different times through delay, thereby preventing the devices from being burned out. In addition, the dead time can be adjusted based on digital control, which brings great convenience to users.
[0072] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.
[0073] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.
[0074] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0075] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A modulation circuit, characterized in that: include: Power tube, pull-down tube, power control module, first AND gate, high-voltage to low-voltage module and pull-down control module; The input end of the power control module is the total input end of the circuit, and the first output end of the power control module is connected to the control end of the power tube and the input end of the high-voltage to low-voltage conversion module respectively. The power control module is used to adjust the level value of the control end of the power tube according to the voltage value of the total input end; The output end of the high-voltage to low-voltage module is connected to the first input end of the first AND gate, the total input end is connected to the second input end of the first AND gate via the pull-down control module, the output end of the first AND gate is connected to the control end of the pull-down tube, and the non-control end of the power tube is grounded via the non-control end of the pull-down tube, so as to control the on and off of the pull-down tube according to the voltage value and the level value, thereby ensuring that the power tube and the pull-down tube are not turned on at the same time.
2. The modulation circuit according to claim 1, wherein: The circuit further includes: a first inverter and a dead zone module; The first inverter is connected in series with the dead zone module, and the output end of the high-voltage-to-low-voltage conversion module is connected to the first input end of the first AND gate via the first inverter and the dead zone module, so that the level value of the first input end of the first AND gate is consistent with the level value of the output end of the high-voltage-to-low-voltage conversion module.
3. The modulation circuit according to claim 2, wherein: The dead zone module includes: a first Pmos transistor, a first Nmos transistor and a first capacitor; The gate of the first Pmos transistor is connected to the gate of the first Nmos transistor, and the gate of the first Pmos transistor and the gate of the first Nmos transistor both serve as input ends of the dead zone module; The source of the first Pmos transistor is connected to the positive power supply terminal, the drain of the first Pmos transistor is respectively connected to the drain of the first Nmos transistor and the first end of the first capacitor, the source of the first Nmos transistor and the second end of the first capacitor are both grounded, and the first end of the first capacitor serves as the output end of the dead zone module.
4. The modulation circuit according to claim 3, wherein: The dead zone module further includes: a second Pmos tube and at least one digital control tube; The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the source of the second PMOS transistor is connected to the positive power supply terminal, so that the first PMOS transistor is connected to the positive power supply terminal via the second PMOS transistor; The control end of each digital control tube is connected to a different external chip port, and the two non-control ends of the at least one digital control tube are connected in parallel to the source and drain of the second PMOS tube. Under the premise of a fixed power supply, the current provided by each digital control tube is different.
5. The modulation circuit according to claim 1, wherein: The power control module includes: a low voltage to high voltage submodule and a selection submodule; The input end of the low-voltage to high-voltage submodule is the total input end, the output end of the low-voltage to high-voltage submodule is connected to the input end of the selection submodule, and the output end of the selection submodule is connected to the control end of the power tube. The selection submodule is used to determine the level value of the control end of the power tube according to the output signal of the low-voltage to high-voltage submodule.
6. The modulation circuit according to claim 5, characterized in that: The pull-down control module includes: a second inverter; The input terminal of the second inverter serves as the total input terminal, and the output terminal of the second inverter is connected to the second input terminal of the first AND gate.
7. The modulation circuit according to claim 1, wherein: The power control module includes: a selection submodule; The input end of the selection submodule serves as the main input end, and the output end of the selection submodule is connected to the control end of the power tube.
8. The modulation circuit according to claim 7, wherein: The pull-down control module includes: a second inverter and a high-voltage to low-voltage submodule; The second inverter and the high-voltage-to-low-voltage submodule are connected in series, and the total input end is connected to the second input end of the first AND gate via the second inverter and the high-voltage-to-low-voltage submodule.
9. The modulation circuit according to any one of claims 5 or 7, characterized in that: The selection submodule includes: a non-overlapping clock unit, a third Pmos tube and a second Nmos tube; The input end of the non-overlapping clock unit serves as the input end of the selection submodule, the first output end of the non-overlapping clock unit is connected to the gate of the third Pmos tube, the source of the third Pmos tube is connected to the positive electrode of the power supply, the drain of the third Pmos tube is respectively connected to the control end of the power tube, the input end of the high-voltage to low-voltage module and the drain of the second Nmos tube, the second output end of the non-overlapping clock unit is connected to the gate of the second Nmos tube, and the source of the second Nmos tube is connected to the negative electrode of the power supply.
10. The modulation circuit according to claim 9, characterized in that: The non-overlapping clock unit includes: a first branch and a second branch; The first branch includes a first OR gate and a branch inverters, wherein the first input end of the first OR gate serves as the input end of the non-overlapping clock unit, the first OR gate and the a branch inverters are sequentially connected in series, and the output end of the last branch inverter of the first branch serves as the first output end of the non-overlapping clock unit; The second branch includes a first AND gate and b branch inverters, wherein the first input end of the first AND gate serves as the input end of the non-overlapping clock unit, the first AND gate and the b branch inverters are sequentially connected in series, and the output end of the last branch inverter of the second branch serves as the second output end of the non-overlapping clock unit; The output end of the cth branch inverter in the first branch close to the first OR gate is connected to the second input end of the first AND gate, and the output end of the dth branch inverter in the second branch close to the first AND gate is connected to the second input end of the first OR gate, where a, b, c and d are all positive even numbers, and a≥c, b≥d.