Semiconductor packaging structure

Abstract

The utility model provides a semiconductor packaging structure. The semiconductor packaging structure comprises a substrate; the heat dissipation structure is arranged on the substrate; the electronic element is located on the substrate, a first distance is formed between the first side edge of the electronic element and the heat dissipation structure, a second distance is formed between the second side edge of the electronic element and the heat dissipation structure, and the first distance is smaller than the second distance; the bonding structures are used for connecting the substrate and the bottom of the heat dissipation structure, and on the same area of the top surface of the substrate below the bottom, the number of the bonding structures located at the first distance is smaller than the number of the bonding structures located at the second distance. The utility model aims to provide a semiconductor packaging structure so as to at least improve the yield of the semiconductor packaging structure.

Description

Technical Field

[0001] The utility model relates to a semiconductor packaging structure. Background Art

[0002] Figure 1 The figure shows a FlipChip Ball Grid Array with Heat Spread (HFCBGA) with heat spread characteristics in the prior art. Figure 2 FIG. 1 shows a top view of the HFCBGA after removing the heat dissipation structure 1. Figure 3 The stress distribution diagram of HFCBGA from a top view is shown. Figure 4 The bottom of the heat dissipation structure 1 is completely fixed to the substrate 3 by the adhesive layer 2, which has a high bonding strength. As a result, the substrate 3 cannot be continuously deformed under the conditions of the thermal cycle test, and the solder mask (SR) 4 on the bottom of the substrate 3 will be cracked. Figure 1 、 Figure 3 and Figure 4 The high stress area 6] causes the HFCBGA failure problem. Figure 2 and Figure 3 The distance between the first part 201 of the adhesive layer 2 and the chip 7 is smaller than the distance between the second part 202 and the chip 7. Therefore, the stress at the first part 201 is greater, resulting in a higher strain of the substrate 3 under the same unit length, which exceeds the stress that the substrate 3 can withstand, making it more likely that the solder mask 4 at the bottom will break. Figure 5 A partial cross-sectional electron microscope image of substrate 3 at region 6 is shown. Substrate 3 includes, for example, six layers of circuitry (e.g., copper wires). Cracks 5 originating from solder mask 4 extend upward, from solder mask 4 to circuit layers L6 and L5. The failure rate of conventional HFCBGAs is approximately 6%, meaning, for example, 15 out of every 240 units (15 / 240 ea) fail.

[0003] The prior art can avoid the above problem by improving the distribution of the circuit layers in the substrate 3 or the position of the chip 7 , but this will affect the utilization rate and electrical performance of the HFCBGA. Utility Model Content

[0004] In view of the problems existing in the related art, the purpose of the present invention is to provide a semiconductor packaging structure to at least improve the yield rate of the semiconductor packaging structure.

[0005] To achieve the above-mentioned objectives, the present invention provides a semiconductor packaging structure, comprising: a substrate; a heat dissipation structure disposed on the substrate; an electronic component located on the substrate, a first distance being formed between a first side of the electronic component and the heat dissipation structure, the first distance being smaller than a second distance, and a second distance being formed between a second side of the electronic component and the heat dissipation structure; and an adhesive structure for connecting the substrate and the bottom of the heat dissipation structure, wherein, on the same area of ​​the top surface of the substrate below the bottom, the amount of the adhesive structure located at the first distance is less than the amount of the adhesive structure located at the second distance.

[0006] In some embodiments, the bonding structure is discontinuous.

[0007] In some embodiments, the bonded structure has two fractures.

[0008] In some embodiments, the bonding structure has a serpentine structure.

[0009] In some embodiments, the bonding structure has a trapezoidal structure.

[0010] In some embodiments, the bonding structure includes: a plurality of first segments parallel to the extension direction of the bottom and staggered; and a plurality of second segments located between the staggered first segments and connected end to end with the first segments.

[0011] In some embodiments, the second segment is perpendicular to the first segment.

[0012] In some embodiments, the first section of the bonding structure at the second distance is longer than the first section of the bonding structure at the second distance.

[0013] In some embodiments, the length of the first segment of the bonding structure at the first distance is equal to the length of the second segment.

[0014] In some embodiments, the length of the first section of the bonding structure at the first distance is greater than the length of the second section.

[0015] In some embodiments, the second section of the bonding structure located at the second distance forms a right angle with the first section, and the second section of the bonding structure located at the first distance forms an obtuse angle with the first section.

[0016] In some embodiments, the length of the first section of the bonding structure at the first distance is different from the length of the first section of the bonding structure at the second distance.

[0017] In some embodiments, the lengths of the first sections of the bonding structure located at the first distance are different.

[0018] In some embodiments, the semiconductor package structure further includes: a connection layer located between the electronic component and the heat dissipation structure.

[0019] In some embodiments, the connection layer is a thermal interface material.

[0020] A semiconductor packaging structure includes: a substrate; a heat dissipation structure disposed on the substrate; an electronic component located between the substrate and the heat dissipation structure; and an adhesive structure surrounding the electronic component and connecting the substrate and a bottom portion of the heat dissipation structure. On the same area of ​​the top surface of the substrate below the bottom portion, the adhesive structure located below the heat dissipation structure at a first distance from the electronic component has a first amount, and the adhesive structure located below the heat dissipation structure at a second distance from the electronic component has a second amount. The first distance is smaller than the second distance, and the first amount is smaller than the second amount.

[0021] In some embodiments, the electronic component is directly bonded to the substrate.

[0022] In some embodiments, the semiconductor package structure further includes: an underfill layer located between the electronic component and the substrate.

[0023] In some embodiments, the semiconductor package structure further includes solder balls located on the bottom surface of the substrate.

[0024] In some embodiments, the top surface of the substrate includes a first side and a second side connected to each other, the first side is longer than the second side, and the bonding structure has a fracture at a middle position of the first side.

[0025] The beneficial technical effects of the present utility model are:

[0026] In an embodiment of the present application, on the same area of ​​the top surface of the substrate below the bottom of the heat dissipation structure, the first amount of the adhesive structure located at a first distance from the first side edge of the electronic component is less than the second amount of the adhesive structure located at a second distance from the second side edge of the electronic component (the second distance > the first distance). The adhesion force of the adhesive structure in an area closer to the electronic component (and therefore subject to greater stress due to the influence of the electronic component) is less than the adhesion force in an area farther from the electronic component, so as to achieve adaptive bonding strength: the bonding strength is low at locations close to the electronic component and high at locations farther from the electronic component, thereby reducing the possibility of substrate cracking. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without inventive work. It is worth noting that, according to standard industry practices, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the clarity of discussion, the sizes of the various components can be arbitrarily increased or decreased.

[0028] Figure 1 A prior art HFCBGA is shown.

[0029] Figure 2 FIG. 4 shows a top view of the HFCBGA without the heat dissipation structure.

[0030] Figure 3 The stress distribution diagram of HFCBGA from a top view is shown.

[0031] Figure 4 An electron microscope image of HFCBGA is shown from a bottom-up perspective.

[0032] Figure 5 A cross-sectional electron microscope image of a portion of the substrate is shown.

[0033] Figure 6 Providing a substrate is shown.

[0034] Figure 7 Bonding of electronic components to a substrate is shown.

[0035] Figure 8 The formation of an underfill layer is shown.

[0036] Figure 9 The formation of the connecting layer and the bonding structure are shown.

[0037] Figure 10 Shown Figure 9 Top view of the steps shown.

[0038] Figure 11 An enlarged view of the bonding structure of the second embodiment is shown.

[0039] Figure 12 An enlarged view of the bonding structure of the third embodiment is shown.

[0040] Figure 13 An enlarged view of the bonding structure of the fourth embodiment is shown.

[0041] Figure 14 An enlarged view of the bonding structure of the fifth embodiment is shown.

[0042] Figure 15 A heat dissipation structure is shown formed on a substrate.

[0043] Figure 16 A semiconductor package structure is shown.

[0044] Figure 17 The figure shows the stress distribution of the semiconductor package structure from a top view angle. DETAILED DESCRIPTION

[0045] In order to better understand the spirit of the embodiments of the present application, some preferred embodiments of the present application are further described below.

[0046] The embodiments of the present application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are represented by similar reference numerals. The embodiments described herein with respect to the accompanying drawings are illustrative and diagrammatic and are intended to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

[0047] As used herein, the terms "substantially," "substantially," and "approximately" are used to describe and illustrate small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred precisely as well as instances where the event or circumstance occurred very approximately.

[0048] In this specification, unless otherwise specified or limited, relative terms such as "central", "longitudinal", "lateral", "front", "rear", "right", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below", "above", "below", "top", "bottom" and their derivatives (such as "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the directions described in the discussion or depicted in the drawings. These relative terms are only used for convenience of description and do not require that the present application be constructed or operated in a specific orientation.

[0049] For ease of description, “first,” “second,” “third,” etc. may be used herein to distinguish different components in a figure or a series of figures. “First,” “second,” “third,” etc. are not intended to describe the corresponding components.

[0050] Figures 6 to 16 The diagram shows a process of forming a semiconductor package structure 100 according to an embodiment of the present application.

[0051] Figure 6 It is shown that a substrate 10 is provided.

[0052] Figure 7 The electronic component 30 is shown bonded to the substrate 10 , for example, by flip chip bonding (FCB).

[0053] Figure 8 An underfill layer 60 is shown formed between the electronic component 30 and the substrate 10 .

[0054] Figure 9It is shown that a connection layer 50 is formed on the electronic component 30 and the bonding structure 40 is formed on the substrate 10, and the connection layer 50 is a thermal interface material (TIM).

[0055] Figure 10 Shown Figure 9 In the top view of the step shown, the bonding structure 40 is discontinuous. The top surface of the substrate 10 includes a first side 11 and a second side 12 connected to each other. The first side (long side) 11 is longer than the second side (short side) 12. The bonding structure 40 has two breaks 44 at the middle positions of the two long sides.

[0056] Figure 10 Also shown are enlarged views of the bonding structure 40 at a region 46 at a first distance D1 from the first side 31 of the electronic component 30 and at a region 48 at a second distance D2 from the second side 32 of the electronic component 30. It can be seen that the bonding structure 40 is curved, has a serpentine structure, and has a trapezoidal (W-shaped) structure in region 46.

[0057] Furthermore, the bonding structure 40 includes a plurality of first segments 41 that are parallel to the first side 11 (i.e., the extension direction of the bottom of the heat dissipation structure 20) and staggered, and a plurality of second segments 42 that are located between the staggered first segments 41 and connected end-to-end to the first segments 41. The second segments 42 in region 48 are perpendicular to the first segments 41, meaning that the angle β between the second segments 42 and the first segments 41 is a right angle. The angle α between the second segments 42 and the first segments 41 in region 46 is an obtuse angle, meaning that it is greater than the angle β. Therefore, the wavelength of the bonding structure 40 in region 46 is greater than the wavelength of the bonding structure 40 in region 48. For the same area of ​​the top surface of the substrate 10, the first amount of the bonding structure 40 in region 46 is less than the second amount of the bonding structure 40 in region 48.

[0058] Figure 11 An enlarged view of the adhesive structure 40 at region 46 of the second embodiment is shown, where the angle between the first segment 41 and the second segment 42 is also a right angle. That is, on the same area of ​​the top surface of substrate 10, the amount of first segment 41 in region 46 and region 48 is the same, and therefore the adhesive strength of the adhesive structure 40 in the direction of extension of the first segment 41 is the same in region 46 and region 48. At the same time, the wavelength of the adhesive structure 40 in region 46 is increased, that is, the first segment 41 of the adhesive structure 40 at the first distance D1 is longer than the first segment 41 of the adhesive structure 40 at the second distance D2. That is, by increasing the distance between the second segments 42 in region 46, the amount of the second segments 42 is reduced (i.e., the total amount of the adhesive structure 40 is reduced). As a result, the adhesive strength of the adhesive structure 40 in the direction of extension of the second segment 41 in region 46 and region 48 is different, with the adhesive strength in region 46 being less than that in region 48. In region 46 of the second embodiment, the length of the first segment 41 can be equal to the length of the second segment 42.

[0059] Figure 12 An enlarged view of the bonding structure 40 at area 46 of the third embodiment is shown, wherein the angle between the first section 41 and the second section 42 is also a right angle. Compared with the second embodiment, the third embodiment further enlarges the length of the first section 41, and the length of the first section 41 is greater than the length of the second section 42, and the total amount of the bonding structure 40 at area 46 is further reduced.

[0060] Figure 13 An enlarged view of the bonding structure 40 at the region 46 of the fourth embodiment is shown, wherein the angle between the first segment 41 and the second segment 42 is an obtuse angle. Compared with the first embodiment, the fourth embodiment increases the wavelength of the bonding structure 40 at the region 46, that is, increases the length of the first segment 41, thereby increasing the distance between the second segments 42. Therefore, based on the fact that the angle α in the first and fourth embodiments is an obtuse angle, the fourth embodiment further reduces the total amount of the bonding structure 40.

[0061] Figure 14 An enlarged view of the bonding structure 40 at the area 46 of the fifth embodiment is shown, wherein the angle between the first section 41 and the second section 42 is an obtuse angle, compared to the first and fourth embodiments. Figure 14 The first section 41 on the upper side (closer to the electronic component 30 ) is shorter than the first section 41 on the lower side (farther from the electronic component 30 ). Therefore, in the fifth embodiment, the closer the adhesive structure 40 is to the electronic component 30 in the region 46 , the weaker the adhesive force.

[0062] Figure 15 It is shown that the heat dissipation structure 20 is formed on the substrate 10 , and the bonding structure 40 bonds the bottom of the heat dissipation structure 20 and the substrate 10 .

[0063] Figure 16 It is shown that solder balls 70 are formed on the bottom surface of the substrate 10 , completing the manufacture of the semiconductor package structure 100 .

[0064] The embodiment of the present application changes the dispensing method of the adhesive structure 40, that is, changes the coating shape of the adhesive structure 40. The adhesive structure 40 is curved. Compared with the prior art, the adhesive structure 40 does not fully coat the space between the bottom of the heat dissipation structure 40 and the substrate 10, so as to reduce the connection force between the heat dissipation structure 40 and the substrate 10, thereby reducing the possibility of cracking of the semiconductor packaging structure during continuous deformation during continuous temperature cycle testing (reliability testing), thereby improving the yield of the semiconductor packaging structure 100.

[0065] In addition, in the embodiment of the present application, on the same area of ​​the top surface of the substrate 10 below the bottom of the heat dissipation structure 20, the first amount of the adhesive structure 40 located at a first distance D1 from the first side 31 of the electronic component 30 is less than the second amount of the adhesive structure 40 located at a second distance D2 (D2>D1) from the second side 32 of the electronic component 30, and the adhesion of the adhesive structure in the area 46 closer to the electronic component 30 (and therefore subjected to greater stress due to the influence of the electronic component 30) is less than the adhesion in the area 48 farther from the electronic component 30, so as to achieve adaptive bonding strength: the bonding strength is low near the electronic component (chip) 30, and the bonding strength is high far from the electronic component 30, thereby further reducing the possibility of cracking the solder mask layer of the substrate 10 in the area close to the electronic component 30.

[0066] Figure 17 The stress distribution diagram of the semiconductor package structure 100 from a top view is shown, and the stress distribution diagram of the semiconductor package structure 100 from a top view is shown. Figure 3 and this application Figure 17 , set a same specific stress value, Figure 3 The area exceeding a specific stress value accounts for 100% of all areas, Figure 17 The area exceeding the specific stress value accounts for 58% of the entire area, and the stress of the semiconductor package structure 100 of the present application is reduced by 42%.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: substrate; a heat dissipation structure, disposed on the substrate; an electronic component located on the substrate, wherein a first distance exists between a first side of the electronic component and the heat dissipation structure, and a second distance exists between a second side of the electronic component and the heat dissipation structure, wherein the first distance is smaller than the second distance; The bonding structure is used to connect the substrate and the bottom of the heat dissipation structure. On the same area of ​​the top surface of the substrate below the bottom, the amount of the bonding structure located at the first distance is less than the amount of the bonding structure located at the second distance.

2. The semiconductor package structure according to claim 1, wherein: The bonded structure is discontinuous.

3. The semiconductor package structure according to claim 2, wherein: The bonding structure has two fractures.

4. The semiconductor package structure according to claim 1, wherein: The bonding structure comprises: a plurality of first segments parallel to and staggered from the bottom; A plurality of second segments are located between the staggered first segments and are connected end to end with the first segments.

5. The semiconductor package structure according to claim 4, wherein: The second section is perpendicular to the first section.

6. The semiconductor package structure according to claim 5, wherein: The first section of the bonding structure at the first distance is longer than the first section of the bonding structure at the second distance.

7. The semiconductor package structure according to claim 6, wherein: The length of the first section of the bonding structure at the first distance is equal to the length of the second section.

8. The semiconductor package structure according to claim 6, wherein: The length of the first section of the bonding structure at the first distance is greater than the length of the second section.

9. The semiconductor package structure according to claim 4, wherein: The first section of the bonding structure at the first distance has a different length from the first section of the bonding structure at the second distance.

10. The semiconductor package structure according to claim 4, wherein: The first sections of the bonding structures at the first distance have different lengths.

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