STM32F407-based dual-channel redundant Ethernet TRDP communication gateway

Abstract

The utility model relates to the technical field of communication gateways, in particular to a TRDP communication gateway based on an STM32F407 dual-channel redundant Ethernet. The device comprises a CPU processor circuit, a two-channel redundant Ethernet TRDP interface circuit, an SPI and UART interface circuit, a storage circuit and a reserved interface circuit. The CPU processor circuit is respectively connected with the dual-channel redundant TRDP interface circuit, the SPI and UART interface circuit, the storage chip circuit and the reserved interface circuit; the CPU processor circuit receives data of the two-channel Ethernet TRDP bus and performs data interaction through an SPI (Serial Peripheral Interface) and a UART (Universal Asynchronous Receiver / Transmitter) interface; and the CPU processor circuit transmits the SPI and UART interface data to the two-way Ethernet TRDP bus. The protocol conversion device is suitable for railway vehicle network communication, has the TRDP, SPI and UART interface communication functions at the same time, can conveniently achieve protocol conversion between a railway train bus TRDP network and a common SPI and UART interface communication network, and is widely applied to the industrial control field of train buses of subways, light rails, railway locomotives and the like.

Description

Technical Field

[0001] The utility model relates to the technical field of communication gateways, in particular to a dual-channel redundant Ethernet TRDP communication gateway based on STM32F407. Background Art

[0002] At present, in my country's subways, high-speed railways, urban rail transit vehicles and other different rail vehicles, the whole vehicle network (TCMS) and each subsystem network bus mainly adopt MVB, HDLC, CANOPEN and other communication networks; the Ethernet TRDP communication network mainly uses Ethernet to transmit communication information between different devices in the vehicle. Its advantages are large data volume and high communication efficiency during the transmission process. Therefore, it is an industry development trend to develop a communication gateway with large data volume, good real-time performance and reliability based on the existing mainstream MVB communication.

[0003] The TRDP (Train Real-time Data Protocol) protocol described in this utility model is used for rail transit real-time Ethernet networks. For railway Ethernet, improving real-time performance and ensuring reliability are also indispensable conditions. Utility Model Content

[0004] The utility model is mainly developed to solve the data volume and real-time problems in MVB network communication, and proposes a dual-channel redundant Ethernet TRDP communication gateway based on STM32F407, which can realize the conversion of dual-channel redundant Ethernet TRDP and SPI and UART gateway bus communication protocols. It is mainly used for communication between different devices in rail vehicles, and realizes data transparent transmission between dual-channel redundant Ethernet TRDP network and SPI and UART network.

[0005] The technical solution of the utility model, a dual-channel redundant Ethernet TRDP communication gateway based on STM32F407, including CPU processor circuit, dual-channel redundant Ethernet TRDP interface circuit, SPI and UART interface circuit and storage circuit and reserved interface circuit; The reserved interface circuit includes CAN interface and parallel bus interface; TRDP interface circuit is 2-way Ethernet interface circuit independently connected to the outside; SPI interface and UART interface circuit are interfaces for intranet communication between devices;

[0006] The CPU processor circuit is respectively connected to the dual-channel redundant TRDP interface circuit, the SPI and UART interface circuits, the memory chip circuit and the reserved interface circuit;

[0007] The CPU processor circuit receives the dual-channel Ethernet TRDP bus data, and then exchanges data through the SPI and UART interfaces; the CPU processor circuit transmits the SPI and UART interface data to the dual-channel Ethernet TRDP bus.

[0008] The CPU circuitry includes a minimal control system based on the STM32F407 processor. The STM32F407 processor boasts a 168MHz clock speed, supports both the FPU and DSP, 144 I / O pins, most of which are 5V-tolerant, 1024KB of flash memory, 192KB of SRAM, a 1.8-3.6V power supply and voltage, a clock, a 4-26MHz external high-speed crystal oscillator, three ADs, two DAs, and 16 DMAs. It also features 17 timers: ten general-purpose timers, two basic timers, three advanced timers, one system timer, two watchdog timers, and six serial ports.

[0009] The minimum control system with STM32F407 as the control core, and the minimum system peripheral circuits include: storage circuit, clock reset circuit, power supply circuit, and simulation debugging circuit.

[0010] In an optional embodiment, the power supply circuit uses a power supply chip SY8088IAAC to adjust the supply voltage to a required voltage.

[0011] In an optional embodiment, the clock reset circuit uses an 8 MHz crystal oscillator as a clock source.

[0012] In an optional embodiment, the SPI and UART interface circuits are brought out through the SPI interface and UART provided by the SMT32F407 chip.

[0013] In an optional embodiment, the storage circuit uses an MT29F1G08ABAEAWP storage chip and an EEROM chip 24C512.

[0014] In an optional embodiment, the dual-channel redundant TRDP interface circuit is composed of two independent Ethernet protocol stack chips and an isolation transformer, and the chips are W5500 and H1102NL.

[0015] In an optional embodiment, the simulation debugging circuit uses the SWD interface and UART1 of the CPU chip as the debugging simulation circuit of the entire system.

[0016] The main function of the processor SMT32F407 is to perform data transparent transmission, that is, to send the data received by the SPI interface and UART interface to the outside through the dual-channel Ethernet TRDP interface, and at the same time extract the received dual-channel Ethernet TRDP data and send it to the SPI interface and UART interface, thereby realizing the data transparent transmission function.

[0017] Compared with the prior art, the present invention has the following beneficial technical effects:

[0018] On the one hand, the utility model can respond to Ethernet TRDP data in real time, receive dual-channel redundant TRDP data, obtain valid data and transmit it to the SPI interface and UART interface; on the other hand, the communication gateway can save communication log events and communication data in real time, which effectively helps fault analysis;

[0019] This new device offers high stability and reliability, and is suitable for use in various subsystems within the rail vehicle industry. It is widely used in industrial control applications requiring high real-time performance and automated marshaling. It solves the interface conversion issue between rail vehicle network communication buses and is therefore suitable for widespread use within the rail vehicle communications industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic structural diagram of an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of a control block diagram provided by an embodiment of the present utility model. DETAILED DESCRIPTION

[0022] In order to further explain and illustrate the design scheme and design advantages of this utility model, the following Figure 1 and Figure 2 The specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0023] as follows Figure 1 As shown, a dual-channel redundant Ethernet TRDP communication gateway based on STM32F407 mainly includes a CPU processor circuit, a dual-channel redundant Ethernet TRDP interface circuit, an SPI and UART interface circuit, a storage circuit and a reserved interface circuit; the CPU processor circuit mainly includes a minimum control system with STM32F407 as a control core; the CPU processor circuit is respectively connected to the dual-channel redundant TRDP interface circuit, the SPI and UART interface circuit, the storage chip circuit and the reserved interface circuit.

[0024] as follows Figure 2As shown, the CPU processor circuit primarily consists of the SMT32F407 as the control core, along with the following minimum system peripheral circuits: memory circuit, clock reset circuit, power supply circuit, and simulation and debugging circuit. The power interface circuit primarily uses the SY8088IAAC power supply chip to convert the supply voltage to the required voltage; the clock circuit primarily uses an 8MHz crystal oscillator as the clock source. The SPI and UART interface circuits primarily utilize the SMT32F407 chip's built-in SPI and UART interfaces; the memory chip interface circuit primarily utilizes the MT29F1G08ABAEAWP memory chip and the 24C512 EEROM chip; the TRDP interface circuit primarily utilizes two independent Ethernet protocol stack chips, the W5500; and the simulation and debugging circuitry utilizes the CPU chip's built-in SWD interface and UART1 for the entire system's debugging and simulation circuitry. The processor circuit with SMT32F407 as the control core is mainly used to receive data from the dual-channel Ethernet TRDP bus, and then exchange data through the SPI and UART interfaces; at the same time, the CPU processor can also transmit SPI and UART interface data to the dual-channel Ethernet TRDP bus.

[0025] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited thereto. Various changes can be made within the knowledge scope of those skilled in the art without departing from the purpose of the present invention.

Claims

1. A dual-channel redundant Ethernet TRDP communication gateway based on STM32F407, characterized in that, It includes a CPU processor circuit, a dual-channel redundant Ethernet TRDP interface circuit, an SPI and UART interface circuit, a storage circuit, and a reserved interface circuit; The CPU processor circuit is respectively connected to the dual-channel redundant TRDP interface circuit, the SPI and UART interface circuits, the memory chip circuit and the reserved interface circuit; The CPU processor circuit receives the dual-channel Ethernet TRDP bus data, and then exchanges data through the SPI and UART interfaces; the CPU processor circuit transmits the SPI and UART interface data to the dual-channel Ethernet TRDP bus.

2. a kind of based on STM32F407 dual-channel redundant Ethernet TRDP communication gateway according to claim 1, it is characterised in that, The CPU processor circuit includes a minimum control system with STM32F407 as the control core.

3. a kind of based on STM32F407 dual-channel redundant Ethernet TRDP communication gateway according to claim 2, it is characterised in that, The minimum control system with STM32F407 as the control core, and the minimum system peripheral circuits include: storage circuit, clock reset circuit, power supply circuit, and simulation debugging circuit.

4. a kind of based on STM32F407 dual-channel redundant Ethernet TRDP communication gateway according to claim 3, it is characterised in that, The power supply circuit uses the power supply chip SY8088IAAC to adjust the supply voltage to the required voltage.

5. a kind of based on STM32F407 dual-channel redundant Ethernet TRDP communication gateway according to claim 3, it is characterised in that, The clock reset circuit uses an 8MHz crystal oscillator as the clock source.

6. a kind of based on STM32F407 dual-channel redundant Ethernet TRDP communication gateway according to claim 3, it is characterised in that, The storage circuit uses MT29F1G08ABAEAWP storage chip and EEROM chip 24C512.

7. a kind of based on STM32F407 dual-channel redundant Ethernet TRDP communication gateway according to claim 3, it is characterised in that, The simulation debugging circuit uses the SWD interface and UART1 of the CPU chip as the debugging simulation circuit of the entire system.

8. a kind of based on STM32F407 dual-channel redundant Ethernet TRDP communication gateway according to claim 1, it is characterised in that, The SPI and UART interface circuits are brought out through the SPI interface and UART of the SMT32F407 chip.

9. a kind of based on STM32F407 dual-channel redundant Ethernet TRDP communication gateway according to claim 1, it is characterised in that, The dual-channel redundant TRDP interface circuit uses two independent Ethernet protocol stack chips W5500.

10. a kind of based on STM32F407 dual-channel redundant Ethernet TRDP communication gateway according to claim 1, it is characterised in that, The reserved interface circuits include CAN interface and parallel bus interface.

Images