Novel SCR (Selective Catalytic Reduction) structure with high maintaining voltage
By introducing a new current trigger path in the SCR device, the carriers are transported along the trench wall, which solves the problem of low trigger voltage of ESD devices, achieves the combination of high maintenance voltage and low trigger voltage, and improves device performance.
Patent Information
- Application Number
- CN202422633823.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-09-19
- Estimated Expiration
- 2034-10-30
AI Technical Summary
The trigger voltage of ESD devices is relatively low and cannot meet the requirements of existing electronic devices.
By introducing a new current trigger path in the SCR device structure, carriers are transported along the trench wall, and the carrier transport path is transformed from the device surface to the inside of the device, thereby reducing the trigger voltage and alleviating the positive feedback effect between the internal parasitic bipolar transistors.
On the basis of not increasing the device area, a high sustain voltage and a low trigger voltage are achieved, thereby improving the performance of the device per unit area.
Smart Images
Figure CN223364479U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor integrated circuits, in particular to a novel high-maintaining voltage SCR structure. Background Art
[0002] ESD, or electrostatic discharge, is an ancient natural phenomenon. It exists in every corner of our daily lives. However, this commonplace electrical phenomenon can pose a deadly threat to sophisticated integrated circuits. A surge / transient voltage refers to a sudden, random, and excessively high voltage or current that occurs in a circuit. It is characterized by a short duration and extremely high instantaneous energy. Surges are highly destructive to electronic components and integrated circuits. At the very least, they can cause malfunctions in logic circuits. At worst, they can lead to secondary breakdown in transistors, latch-up in complementary metal oxide semiconductors (CMOS), and other severe thermal effects that can cause device or integrated circuit failure. Surges typically have two random sources. The first is power grid instability, such as sudden switching, the sudden activation of capacitive or inductive loads, hot-swapping of related equipment, and unstable power supply operation. The second is sudden external interference, such as lightning and electrostatic discharge.
[0003] With advancements in integrated circuit manufacturing processes, minimum line widths have dropped to submicron or even nanometer levels. While this has improved chip performance, it has also significantly reduced ESD resistance, leading to more severe electrostatic damage. ESD typically causes non-fatal damage to integrated circuits, reducing their lifespan and reliability, and ultimately degrading system functionality. This significantly hinders the implementation of large-scale, high-reliability integration.
[0004] However, the trigger voltage of some ESD devices is too low to meet the needs of existing electronic devices. In order to realize an ESD device with excellent trigger voltage and holding voltage characteristics, the present invention is based on the following examples: Figure 1 Based on the traditional SCR device structure shown in FIG, a new high holding voltage SCR structure is proposed.
[0005] It should be noted that the information disclosed in the background technology section of this utility model is only intended to deepen the understanding of the general background technology of the utility model, and should not be regarded as an admission or in any form of implication that the information constitutes prior art already known to those skilled in the art. Utility Model Content
[0006] The purpose of the utility model is to provide a novel high-maintaining voltage SCR structure to solve the problem of low triggering voltage of ESD devices.
[0007] In order to solve the above technical problems, the present invention provides a novel high holding voltage SCR structure, comprising:
[0008] a first conductive type substrate;
[0009] A first conductive type well region is provided in the first conductive type substrate, and a second conductive type well region is provided on one side edge of the first conductive type well region;
[0010] A trench spanning a junction between the first conductive type well region and the second conductive type well region;
[0011] a first conductive type sidewall Zener implantation region, disposed on a side of the trench where the trench connects to the first conductive type well region and extending to the bottom of the trench;
[0012] The second conductive type sidewall region is arranged on a side of the trench where it connects with the second conductive type well region, and extends to the bottom of the trench to connect with the first conductive type sidewall Zener injection region.
[0013] Preferably, the bottom of the trench is lower than lower edges of the first conductivity type well region and the second conductivity type well region.
[0014] Preferably, lower edges of the first conductivity type well region and the second conductivity type well region are on the same horizontal line.
[0015] Preferably, a bottom lower edge of the first conductive type sidewall Zener injection region is lower than a bottom lower edge of the second conductive type sidewall region.
[0016] Preferably, a first ion implantation region is provided in the second conductive type well region, and one side of the first ion implantation region is connected to a second ion implantation region.
[0017] Preferably, the first ion implantation region and the second ion implantation region have different conductivity types.
[0018] Preferably, the first ion implantation region and the second ion implantation region are interconnected by a wire and are used as an anode of the SCR structure.
[0019] Preferably, a third ion implantation region is provided in the first conductive type well region, and a fourth ion implantation region is connected to one side of the third ion implantation region.
[0020] Preferably, the third ion implantation region and the fourth ion implantation region have different conductivity types.
[0021] Preferably, the third ion implantation region and the fourth ion implantation region are interconnected by a wire and used as a cathode of the SCR structure.
[0022] In the novel high-sustaining-voltage SCR structure provided by the present invention, a new current triggering path is introduced, so that carriers are transported along the groove wall, and the carrier transport path is changed from the device to the inside of the device, thereby reducing the triggering voltage of the SCR device and effectively alleviating the positive feedback effect between the internal parasitic bipolar transistors. A high sustaining voltage and a low triggering voltage are simultaneously achieved without increasing the device area, thereby improving these two important indicators of the device and enhancing the performance of the device per unit area. A high sustaining voltage and a low triggering voltage are simultaneously achieved without increasing the device area, thereby improving these two important indicators of the device and enhancing the performance of the device per unit area. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0024] Figure 1 It is a schematic diagram of the structure of a traditional SCR device;
[0025] Figure 2 This is a schematic diagram of a novel high-maintaining voltage SCR structure proposed in one embodiment of the present utility model;
[0026] Figure 3 This is a schematic diagram of the current triggering path of a novel high holding voltage SCR structure proposed in one embodiment of the present utility model;
[0027] Figure 4 This is a schematic structural diagram of another embodiment of the present invention for forming a well region;
[0028] Figure 5 This is a schematic structural diagram of a groove formed in another embodiment of the present invention;
[0029] Figure 6 It is a schematic structural diagram of forming a sidewall area in another embodiment of the present invention.
[0030] In the attached figure:
[0031] 101. First conductive type substrate; 102. Second conductive type well region; 103. First conductive type well region; 104. First ion implantation region; 105. Second ion implantation region; 106. Third ion implantation region; 107. Fourth ion implantation region; 108. Second conductive type sidewall region; 109. First conductive type sidewall Zener implantation region. DETAILED DESCRIPTION
[0032] To further clarify the objectives, advantages, and features of the present invention, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are highly simplified and not drawn to scale, and are intended solely to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often portions of the actual structures. In particular, different drawings may require different emphases and may use different scales.
[0033] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end closest to the operator, and the term "distal end" generally refers to the end closest to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only endpoints. The terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be internal communication between two elements or an interaction relationship between two elements. In addition, as used in the present invention, an element is generally provided on another element, which generally only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements can be direct or indirect through an intermediate element, and it cannot be understood to indicate or imply a spatial positional relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below, or to the side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in this utility model can be understood according to specific circumstances.
[0034] The inventors have found that the trigger voltage of ESD devices is relatively low and cannot meet the requirements of existing electronic devices.
[0035] Based on this, the core idea of the present invention is to introduce a new current triggering path so that carriers are transported along the groove wall, and the carrier transport path is transformed from the device to the inside of the device, thereby reducing the trigger voltage of the SCR device and alleviating the positive feedback effect between the internal parasitic bipolar transistors.
[0036] [Example 1]
[0037] For details, please refer to Figure 2-Figure 3 , which is a schematic diagram of an embodiment of the present utility model. Figure 2 As shown, a new high holding voltage SCR structure includes:
[0038] First conductive type substrate 101;
[0039] A first conductive type well region 103 is provided in the first conductive type substrate 101 , and a second conductive type well region 102 is provided on one side edge of the first conductive type well region 103 ;
[0040] a trench (not labeled) spanning the boundary between the first conductivity type well region 103 and the second conductivity type well region 102 ;
[0041] a first conductivity type sidewall Zener implantation region 109, which is disposed on a side of the trench where the trench connects to the first conductivity type well region 103 and extends to the bottom of the trench;
[0042] The second conductive type sidewall region 108 is disposed on a side of the trench where it connects with the second conductive type well region 102 , and extends to the bottom of the trench to connect with the first conductive type sidewall Zener implantation region 109 .
[0043] For example, the first conductivity type is P-type and the second conductivity type is N-type. Therefore, the first conductivity type semiconductor substrate may be doped with a P-type dopant, such as boron. However, in other embodiments of the present invention, the carriers may be holes. In this case, the first conductivity type is N-type, and the corresponding second conductivity type is P-type. This description assumes that the first conductivity type is P-type and the second conductivity type is N-type.
[0044] By introducing an ion implantation region at the inner wall of the trench, carriers are transported along the trench wall, and the carrier transport path is changed from the surface to the interior of the device, thereby reducing the trigger voltage of the SCR device and effectively alleviating the positive feedback effect between the internal parasitic bipolar transistors. A high holding voltage and a low trigger voltage are achieved simultaneously without increasing the device area, thereby improving two important indicators of the device and enhancing the performance of the device per unit area. A high holding voltage and a low trigger voltage are achieved simultaneously without increasing the device area, thereby improving two important indicators of the device and enhancing the performance of the device per unit area.
[0045] Illustratively, the second conductivity type well region 102 is located within the first conductivity type substrate 101, with its upper edge tangent to the upper edge of the first conductivity type substrate 101, its left edge tangent to the left edge of the first conductivity type substrate 101, and its lower edge higher than the lower edge of the first conductivity type substrate 101. The second conductivity type sidewall region 108 is located to the right of the second conductivity type well region 102. The first conductivity type well region 103 is located within the first conductivity type substrate 101, with its edge tangent to the upper edge of the first conductivity type substrate 101, its right edge tangent to the right edge of the first conductivity type substrate 101, and its lower edge higher than the lower edge of the first conductivity type substrate 101. The first conductivity type sidewall Zener implantation region 109 is located to the left of the first conductivity type well region 103.
[0046] The bottom of the trench is lower than the lower edges of the first conductive type well region 103 and the second conductive type well region 102. The lower edges of the first conductive type well region 103 and the second conductive type well region 102 are on the same horizontal line.
[0047] like Figure 3 As shown, P-type high-concentration Zener implantation is used on the sidewall of the trench to form a first conductive type sidewall Zener implantation region 109, which can also be called a sidewall ZP region. When the ESD voltage comes, the second conductive type sidewall region 108 of the trench sidewall, that is, the N-type sidewall region, forms a PN junction with the first conductive type sidewall Zener implantation region 109, which has a lower breakdown voltage and thus causes a lower trigger voltage of the SCR device.
[0048] Furthermore, compared with traditional SCR devices, forming the sidewall and bottom ion implantation regions at the trench can effectively suppress the positive feedback effect of the parasitic NPN and PNP bipolar transistors inside the device after the SCR is excited, thereby greatly weakening the snapback effect and maintaining the voltage at a higher value.
[0049] In one embodiment, when ion implantation regions are provided in the first conductive type well region 103 and the second conductive type well region 102 to form an SCR structure, a first ion implantation region 104 is provided in the second conductive type well region 102, and a second ion implantation region 105 is connected to one side of the first ion implantation region 104. The first ion implantation region 104 and the second ion implantation region 105 have different conductivity types. The first ion implantation region 104 and the second ion implantation region 105 are interconnected by a wire and are used to serve as the anode of the SCR structure. A third ion implantation region 106 is provided in the first conductive type well region 103, and a fourth ion implantation region 107 is connected to one side of the third ion implantation region 106. The third ion implantation region 106 and the fourth ion implantation region 107 have different conductivity types. The third ion implantation region 106 and the fourth ion implantation region 107 are interconnected by a wire and are used to serve as the cathode of the SCR structure.
[0050] Exemplarily, the first ion implantation region 104 and the third ion implantation region 106 are of P type, and the second ion implantation region 105 and the fourth ion implantation region 107 are of N type.
[0051] In the aforementioned SCR structure, when an ESD voltage is applied, holes from third ion implantation region 106 are injected into second-conductivity-type sidewall region 108, where they recombine with electrons therein. Electrons from fourth ion implantation region 107 are injected into first-conductivity-type sidewall Zener implantation region 109, where they recombine with holes therein. This degrades the positive feedback mechanism composed of the parasitic NPN and PNP transistors, significantly reducing the bipolar amplification effect. Compared to traditional SCR device structures, the new high-sustaining-voltage device structure shifts the carrier transport path from the device surface to the interior, effectively increasing current density and sustaining voltage.
[0052] Exemplarily, the first ion implantation region 104 and the second ion implantation region 105 are located inside the second conductivity type well region 102, with their upper edges tangent to the upper edge of the second conductivity type well region 102 and their lower edges higher than the lower edge of the second conductivity type well region 102; wherein, the first ion implantation region 104 is located on the left side of the second ion implantation region 105, and its right edge is tangent to the left edge of the second ion implantation region 105. The third ion implantation region 106 and the fourth ion implantation region 107 are located inside the first conductivity type well region 103, with their upper edges tangent to the upper edge of the first conductivity type well region 103 and their lower edges higher than the lower edge of the first conductivity type well region 103; wherein, the fourth ion implantation region 107 is located on the right side of the third ion implantation region 106, and its left edge is tangent to the right edge of the third ion implantation region 106.
[0053] In one embodiment, a bottom lower edge of the first conductive type sidewall Zener injection region 109 is lower than a bottom lower edge of the second conductive type sidewall region 108 .
[0054] As can be understood, the second conductivity type sidewall region 108 spans the boundary between the second conductivity type well region 102 and the first conductivity type substrate 101, is located within the second conductivity type well region 102 and the first conductivity type substrate 101, has an upper edge tangent to the upper edge of the second conductivity type well region 102, and a lower edge lower than the lower edges of the second conductivity type well region 102 and the first conductivity type substrate 101, and higher than the lower edge of the first conductivity type sidewall Zener implant region 109; its left edge is tangent to the second conductivity type well region 102 and the first conductivity type substrate 101, respectively. The first conductivity type sidewall Zener implant region 109 is located to the right of the second conductivity type sidewall region 108, and its left edge is tangent to the right edge of the second conductivity type sidewall region 108.
[0055] The first conductive type sidewall Zener injection region 109 spans the junction of the first conductive type well region 103 and the first conductive type substrate 101, and is located inside the first conductive type well region 103 and the first conductive type substrate 101. Its upper edge is tangent to the upper edge of the first conductive type well region 103, and its lower edge is lower than the lower edges of the second conductive type well region 102 and the first conductive type well region 103 and lower than the lower edge of the second conductive type sidewall region 108; its right edge is tangent to the first conductive type well region 103 and the first conductive type substrate 101 respectively, and the second conductive type sidewall region 108 is located on the left side of the first conductive type sidewall Zener injection region 109 and its right edge is tangent to the right edge of the first conductive type sidewall Zener injection region 109.
[0056] Among them, ion implantation can also be continued on the basis of the first conductive type substrate 101 and the first conductive type well region 103 and the second conductive type well region 102 to form PNP structure, NPN structure, diode structure, MOS structure and other structures, or the number of stacked series or stacked packages can be changed according to different application scenarios.
[0057] [Example 2]
[0058] Based on the same technical concept, the present disclosure also provides a method for manufacturing a novel high-maintaining voltage SCR structure. Figure 2-Figure 6 As shown, the following steps are included:
[0059] S1, providing a first conductive type substrate 101.
[0060] S2, such as Figure 4 As shown, adjacent first conductivity type well region 103 and second conductivity type well region 102 are formed in the first conductivity type substrate 101 by ion implantation.
[0061] For example, the first conductivity type is P-type and the second conductivity type is N-type. Therefore, the first conductivity type semiconductor substrate may be doped with a P-type dopant, such as boron. However, in other embodiments of the present invention, the carriers may be holes. In this case, the first conductivity type is N-type, and the corresponding second conductivity type is P-type. This description assumes that the first conductivity type is P-type and the second conductivity type is N-type.
[0062] The first conductive type well region 103 and the second conductive type well region 102 are formed by ion implantation of N-type ions and P-type ions and then thermal injection.
[0063] S3, such as Figure 5 As shown, after forming the first conductivity type well region 103 and the second conductivity type well region 102, and before forming the trench: ion implantation is performed on the first conductivity type well region 103 and the second conductivity type well region 102 to form adjacent first ion implantation regions 104 and second ion implantation regions 105 in the first conductivity type well region 103, wherein the first ion implantation regions 104 and the second ion implantation regions 105 have different conductivity types; and adjacent third ion implantation regions 106 and fourth ion implantation regions 107 are formed in the second conductivity type well region 102, wherein the third ion implantation regions 106 and the fourth ion implantation regions 107 have different conductivity types. After forming the ion implantation regions, each ion implantation region is thermally activated.
[0064] In one embodiment, the first ion implantation region 104 and the second ion implantation region 105 are interconnected by a wire and serve as the anode of the SCR structure. The third ion implantation region 106 and the fourth ion implantation region 107 are interconnected by a wire and serve as the cathode of the SCR structure.
[0065] Exemplarily, the first ion implantation region 104 and the third ion implantation region 106 are of P type, and the second ion implantation region 105 and the fourth ion implantation region 107 are of N type.
[0066] S4, such as Figure 6 As shown, the junction area between the first conductive type well region 103 and the second conductive type well region 102 is etched to form a trench.
[0067] S5, such as Figure 2 As shown, second conductive type ions are injected into the sidewalls and bottom of the trench near the second conductive type well region 102 to form a second conductive type sidewall region 108; first conductive type ions are Zener injected into the sidewalls and bottom of the trench near the first conductive type well region 103, and thermal activation is performed to form a first conductive type sidewall Zener injection region 109.
[0068] As can be understood, the second conductivity type sidewall region 108 spans the boundary between the second conductivity type well region 102 and the first conductivity type substrate 101, is located within the second conductivity type well region 102 and the first conductivity type substrate 101, has an upper edge tangent to the upper edge of the second conductivity type well region 102, and a lower edge lower than the lower edges of the second conductivity type well region 102 and the first conductivity type substrate 101, and higher than the lower edge of the first conductivity type sidewall Zener implant region 109; its left edge is tangent to the second conductivity type well region 102 and the first conductivity type substrate 101, respectively. The first conductivity type sidewall Zener implant region 109 is located to the right of the second conductivity type sidewall region 108, and its left edge is tangent to the right edge of the second conductivity type sidewall region 108.
[0069] The first conductive type sidewall Zener injection region 109 spans the junction of the first conductive type well region 103 and the first conductive type substrate 101, and is located inside the first conductive type well region 103 and the first conductive type substrate 101. Its upper edge is tangent to the upper edge of the first conductive type well region 103, and its lower edge is lower than the lower edges of the second conductive type well region 102 and the first conductive type well region 103 and lower than the lower edge of the second conductive type sidewall region 108; its right edge is tangent to the first conductive type well region 103 and the first conductive type substrate 101 respectively, and the second conductive type sidewall region 108 is located on the left side of the first conductive type sidewall Zener injection region 109 and its right edge is tangent to the right edge of the first conductive type sidewall Zener injection region 109.
[0070] Compared with the traditional SCR structure, this structure introduces a trench at the interface of the well region and performs ion implantation on the sidewalls and bottom of the trench, so that carriers are transported along the trench walls, effectively suppressing the positive feedback effect of the parasitic NPN and PNP bipolar transistors inside the device after the SCR is excited, greatly weakening the snapback effect, maintaining the voltage at a higher value, reducing the trigger voltage of the SCR device, and improving the trigger voltage and holding voltage characteristics of the device.
[0071] The device structure and the accompanying drawings proposed in the present invention are merely a demonstration and illustration of the novel high holding voltage SCR device structure. In addition to the structure shown in the accompanying drawings, anyone familiar with the art may modify or change the above structure without departing from the spirit and scope of the present invention. For example, the SCR structure described above may be changed to a PNP structure, an NPN structure, a diode structure, a MOS structure, or the like, or the number of stacked series or stacked packages may be changed according to different application scenarios. Such structures are obviously within the scope of protection of the present invention.
[0072] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.
Claims
1. A new type of high holding voltage SCR structure, characterized in that: include: a first conductive type substrate; A first conductive type well region is provided in the first conductive type substrate, and a second conductive type well region is provided on one side edge of the first conductive type well region; A trench spanning a junction between the first conductive type well region and the second conductive type well region; a first conductive type sidewall Zener implantation region, disposed on a side of the trench where the trench connects to the first conductive type well region and extending to the bottom of the trench; The second conductive type sidewall region is arranged on a side of the trench where it connects with the second conductive type well region, and extends to the bottom of the trench to connect with the first conductive type sidewall Zener injection region.
2. The novel high holding voltage SCR structure according to claim 1, characterized in that: The bottom of the trench is lower than lower edges of the first conductive type well region and the second conductive type well region.
3. The novel high sustaining voltage SCR structure according to claim 1, characterized in that: Lower edges of the first conductivity type well region and the second conductivity type well region are on the same horizontal line.
4. The novel high sustaining voltage SCR structure according to claim 1, characterized in that: A bottom lower edge of the first conductive type sidewall Zener injection region is lower than a bottom lower edge of the second conductive type sidewall region.
5. The novel high sustaining voltage SCR structure according to claim 1, characterized in that: A first ion implantation region is provided in the second conductive type well region, and one side of the first ion implantation region is connected to the second ion implantation region.
6. The novel high sustaining voltage SCR structure according to claim 5, characterized in that: The first ion implantation region and the second ion implantation region have different conductivity types.
7. The novel high sustaining voltage SCR structure according to claim 5, characterized in that: The first ion implantation region and the second ion implantation region are interconnected by a wire and are used as an anode of the SCR structure.
8. The novel high sustaining voltage SCR structure according to claim 1, characterized in that: A third ion implantation region is provided in the first conductive type well region, and a fourth ion implantation region is connected to one side of the third ion implantation region.
9. The novel high sustaining voltage SCR structure according to claim 8, characterized in that: The third ion implantation region and the fourth ion implantation region have different conductivity types.
10. The novel high sustaining voltage SCR structure according to claim 8, characterized in that: The third ion implantation region and the fourth ion implantation region are interconnected via a wire and are used as a cathode of the SCR structure.