Interaction circuit of chip and external equipment, mainboard and electronic equipment

Abstract

The embodiment of the utility model provides an interaction circuit of a chip and an external device, a mainboard and an electronic device, and relates to the technical field of chips, under the condition that a reset signal obtained by a reset signal receiving end is a first level, the chip works normally at the moment, a third end and a fourth end corresponding to the third end are controlled to be conducted through a switch module, and the chip works normally. Enabling the chip to be communicated and interacted with external equipment; under the condition that the reset signal is the second level, the chip is reset or powered on, the third end and the fourth end corresponding to the third end are controlled to be disconnected through the switch module, so that the chip is disconnected from the external equipment, and interference signals generated by the general input and output port of the chip are prevented from being transmitted to the external equipment under the condition that the chip is powered on or reset; and the external equipment state is abnormal.

Description

Technical Field

[0001] The utility model relates to the technical field of chips, in particular to an interactive circuit between a chip and external equipment, a mainboard and electronic equipment. Background Art

[0002] General Purpose Input / Output (GPIO) ports perform input and output functions in different electronic devices. GPIOs are widely used in embedded systems, microcontrollers, computer hardware, IoT devices, and other fields to enable communication between chips and external devices.

[0003] In the prior art, the chip is directly electrically connected to the external device through wires.

[0004] In the process of implementing this application, the inventors discovered that there are at least the following problems in the prior art: when the chip is powered on or reset, the general input and output ports of the chip generate interference signals, and the interference signals are transmitted to the general input and output ports of external devices through wires, causing abnormal status of the external devices.

[0005] It should be noted that when the chip is powered on or reset, the level of the reset signal received by the reset terminal of the chip is opposite to the level of the reset signal when the chip is working normally. Utility Model Content

[0006] The utility model provides an interactive circuit between a chip and an external device, a mainboard, and an electronic device, so as to at least solve the problem in the prior art that when the chip is powered on or reset, the universal input and output ports of the chip generate interference signals, and the interference signals are transmitted to the universal input and output ports of the external device through wires, resulting in abnormal status of the external device.

[0007] In a first aspect, an embodiment of the present invention provides an interaction circuit between a chip and an external device, which is applied to a chip, wherein the chip has at least one corresponding external device, the chip includes at least one first terminal, and each external device corresponding to the chip includes at least one second terminal, wherein the first terminal and the second terminal have a one-to-one correspondence; the interaction circuit between the chip and the external device includes a switch module, wherein the switch module includes at least one control terminal, at least one third terminal, and at least one fourth terminal, wherein the third terminal and the fourth terminal have a one-to-one correspondence; each first terminal has a corresponding third terminal;

[0008] Each of the control terminals is used to be electrically connected to a reset signal receiving terminal of the chip;

[0009] The third end is electrically connected to the first end corresponding to the third end; the fourth end corresponding to the third end is electrically connected to the second end corresponding to the first end electrically connected to the third end;

[0010] The switch module is used to control the third end and the fourth end corresponding to the third end to be connected when the reset signal obtained by the reset signal receiving end is a first level; and to control the third end and the fourth end corresponding to the third end to be disconnected when the reset signal is a second level.

[0011] Optionally, the switch module includes at least one switch unit, each of the switch units includes at least one control end, at least one third end and at least one fourth end, and the third end of the switch unit corresponds one-to-one to the fourth end of the switch unit; the switch unit is used to control the third end of the switch unit and the fourth end corresponding to the third end of the switch unit to be conductive when the reset signal is the first level; and to control the third end of the switch unit and the fourth end corresponding to the third end of the switch unit to be disconnected when the reset signal is the second level.

[0012] Optionally, when the switch unit is a switch device, the switch unit includes one control terminal, one third terminal and one fourth terminal; when the switch unit is a phase shifter chip, the switch unit includes one control terminal, multiple third terminals and multiple fourth terminals.

[0013] Optionally, the types of the switch units in the switch module are all the same, partially the same, or all different, and the types of the switch units include switch devices and phase regulator chips.

[0014] Optionally, the switching device includes a MOS tube and / or a triode.

[0015] Optionally, the interaction circuit between the chip and the external device also includes at least one resistor, each of the resistors includes a fifth end and a sixth end; each of the second ends has a corresponding fifth end; the fifth end is electrically connected to the second end corresponding to the fifth end; and the sixth end is used to be electrically connected to an external power supply or to ground.

[0016] Optionally, the chip further includes a reset terminal, and the reset signal receiving terminal is electrically connected to the reset terminal.

[0017] Optionally, the type of the first end is GPIO, and / or the type of the second end is GPIO.

[0018] In a second aspect, an embodiment of the present invention further provides a mainboard, comprising an interactive circuit between the chip and an external device as described in the first aspect.

[0019] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising an interactive circuit between the chip and an external device as described in the first aspect, or a mainboard as described in the second aspect.

[0020] In an embodiment of the present utility model, since the third end of the switch module is electrically connected to the first end of the chip corresponding to the third end, the fourth end of the switch module corresponding to the third end is electrically connected to the second end of the external device corresponding to the first end, and the control end of the switch module is used to be electrically connected to the reset signal receiving end of the chip, then when the reset signal obtained by the reset signal receiving end is a first level, the chip works normally at this time, and the third end is controlled by the switch module to be connected to the fourth end corresponding to the third end, so that the chip is connected and interacts with the external device; when the reset signal is a second level, the chip is reset or powered on at this time, and the third end is controlled by the switch module to be disconnected from the fourth end corresponding to the third end, so that the chip is disconnected from the external device, so as to avoid the interference signal generated by the general input and output port of the chip being transmitted to the external device when the chip is powered on or reset, resulting in an abnormal state of the external device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0022] Figure 1 This is a schematic diagram of the structure of an interactive circuit between a chip and an external device provided by an embodiment of the present utility model;

[0023] Figure 2 This is a schematic diagram of a specific structure of the interactive circuit between the chip and the external device provided by the embodiment of the utility model;

[0024] Figure 3 This is another specific structural diagram of the interactive circuit between the chip and the external device provided by the embodiment of the utility model;

[0025] Figure 4 This is another specific structural diagram of the interactive circuit between the chip and the external device provided by the embodiment of the utility model;

[0026] Figure 5 This is another specific structural diagram of the interactive circuit between the chip and the external device provided by the embodiment of the utility model;

[0027] Figure 6 This is another specific structural diagram of the interaction circuit between the chip and the external device provided by the embodiment of the utility model;

[0028] Figure 7 This is yet another specific structural diagram of the interactive circuit between the chip and the external device provided by the embodiment of the present utility model.

[0029] Reference numerals:

[0030] 10 - switch module; 11 - switch unit; 101 - third terminal; 102 - fourth terminal; 103 - control terminal; 20 - chip; 201 - first terminal; 202 - reset terminal; 203 - reset signal receiving terminal; 30 - external device; 301 - second terminal; 40 - resistor; 401 - fifth terminal; 402 - sixth terminal. DETAILED DESCRIPTION

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0032] Reference Figure 1 The embodiment of the present invention provides an interactive circuit between a chip and an external device, which is applied to a chip 20. The chip 20 has at least one corresponding external device 30. The chip 20 includes at least one first terminal 201. Each external device 30 corresponding to the chip 20 includes at least one second terminal 301. The first terminal 201 corresponds to the second terminal 301 in a one-to-one manner. The interactive circuit between the chip and the external device includes a switch module 10. The switch module 10 includes at least one control terminal 103, at least one third terminal 101, and at least one fourth terminal 102. The third terminal 101 corresponds to the fourth terminal 102 in a one-to-one manner. Each first terminal 201 has a corresponding third terminal 103. 1; each of the control terminals 103 is used to be electrically connected to the reset signal receiving terminal 203 of the chip 20; the third terminal 101 is electrically connected to the first terminal 201 corresponding to the third terminal 101; the fourth terminal 102 corresponding to the third terminal 101 is electrically connected to the second terminal 301 corresponding to the first terminal 201 electrically connected to the third terminal 101; the switch module 10 is used to control the third terminal 101 to be conductive with the fourth terminal 102 corresponding to the third terminal 101 when the reset signal obtained by the reset signal receiving terminal 203 is a first level; and to control the third terminal 101 to be disconnected with the fourth terminal 102 corresponding to the third terminal 101 when the reset signal is a second level.

[0033] It should be noted that the chip 20 can be a central processing unit (CPU), a microcontroller unit (MCU), a single chip microcomputer, or other types of chips, and the external device 30 can be a switch device, a sensor, a driver, a relay, etc.

[0034] Specifically, in some embodiments, when the chip 20 is powered on or reset, the reset signal received by the chip 20 through the reset signal receiving terminal 203 is a low level, and when the chip 20 is working normally, the reset signal is a high level; in other embodiments, when the chip 20 is powered on or reset, the reset signal received by the chip 20 through the reset signal receiving terminal 203 is a high level, and when the chip 20 is working normally, the reset signal is a low level.

[0035] For example, refer to Figure 2 The chip 20 has a corresponding external device 30, the chip 20 includes a first end 201, the external device 30 includes a second end 301, and the first end 201 corresponds to the second end 301 one-to-one; the interaction circuit between the chip and the external device includes a switch module 10, the switch module 10 includes a control end 103, a third end 101 and a fourth end 102, and the third end 101 corresponds to the fourth end 102 one-to-one; the first end 201 has a corresponding third end 101; the control end 103 of the switch module 10 is used to be electrically connected to the reset signal receiving end 203 of the chip 20, the third end 101 of the switch module 10 is electrically connected to the first end 201 of the chip 20; the fourth end 102 of the switch module 10 is electrically connected to the second end 301 of the external device 30.

[0036] For example, refer to Figure 4 The chip 20 has a corresponding external device 30, the chip 20 includes two first terminals 201, the external device 30 includes two second terminals 301, and the first terminals 201 correspond to the second terminals 301 one-to-one; the interaction circuit between the chip and the external device includes a switch module 10, the switch module 10 includes two control terminals 103, two third terminals 101 and two fourth terminals 102, and the third terminals 101 correspond to the fourth terminals 102 one-to-one; the first terminal 201 has a corresponding third terminal 101; each control terminal 103 is used to be electrically connected to the reset signal receiving terminal 203 of the chip 20; the third terminal 101 is electrically connected to the first terminal 201 corresponding to the third terminal 101; the fourth terminal 102 corresponding to the third terminal 101 is electrically connected to the second terminal 301 corresponding to the first terminal 201 electrically connected to the third terminal 101.

[0037] For example, refer to Figure 7The chip 20 has two corresponding external devices 30, the chip 20 includes two first terminals 201, and the external device 30 includes two second terminals 301, and the first terminals 201 correspond to the second terminals 301 one-to-one; the interaction circuit between the chip and the external device includes a switch module 10, the switch module 10 includes two control terminals 103, two third terminals 101 and two fourth terminals 102, and the third terminals 101 correspond to the fourth terminals 102 one-to-one; the first terminal 201 has a corresponding third terminal 101; each control terminal 103 is used to be electrically connected to the reset signal receiving terminal 203 of the chip 20; the third terminal 101 is electrically connected to the first terminal 201 corresponding to the third terminal 101; the fourth terminal 102 corresponding to the third terminal 101 is electrically connected to the second terminal 301 corresponding to the first terminal 201 electrically connected to the third terminal 101.

[0038] In the embodiment of the present invention, since the third end 101 of the switch module 10 is electrically connected to the first end 201 of the chip 20 corresponding to the third end 101, the fourth end 102 of the switch module 10 corresponding to the third end 101 is electrically connected to the second end 301 of the external device 30 corresponding to the first end 201, and the control end 103 of the switch module 10 is used to be electrically connected to the reset signal receiving end 203 of the chip 20, then when the reset signal received by the reset signal receiving end 203 is the first level, the chip 20 works normally, and the control end 103 of the switch module 10 is electrically connected to the reset signal receiving end 203 of the chip 20. The third end 101 and the fourth end 102 corresponding to the third end 101 are connected, so that the chip 20 is connected and interacts with the external device 30; when the reset signal is at the second level, the chip 20 is reset or powered on, and the third end 101 and the fourth end 102 corresponding to the third end 101 are disconnected through the switch module 10, so that the chip 20 is disconnected from the external device 30, so as to avoid the interference signal generated by the universal input and output port of the chip 20 being transmitted to the external device 30 when the chip 20 is powered on or reset, causing the external device 30 to be in an abnormal state.

[0039] Optionally, in some embodiments, the switch module 10 includes at least one switch unit 11, each switch unit 11 includes at least one control terminal 103, at least one third terminal 101 and at least one fourth terminal 102, and the third terminal 101 of the switch unit 11 corresponds one-to-one to the fourth terminal 102 of the switch unit 11; the switch unit 11 is used to control the third terminal 101 of the switch unit 11 and the fourth terminal 102 corresponding to the third terminal 101 of the switch unit 11 to be turned on when the reset signal is the first level; and to control the third terminal 101 of the switch unit 11 and the fourth terminal 102 corresponding to the third terminal 101 of the switch unit 11 to be turned off when the reset signal is the second level.

[0040] It should be noted that the control end 103 of the switch unit 11 is a control end 103 of the switch module 10, the third end 101 of the switch unit 11 is a third end 101 of the switch module 10, and the fourth end 102 of the switch unit 11 is a fourth end 102 of the switch module 10.

[0041] For example, refer to Figure 2 The chip 20 has a corresponding external device 30, the chip 20 includes a first end 201, the external device 30 includes a second end 301, and the first end 201 corresponds to the second end 301 one-to-one; the interaction circuit between the chip and the external device includes a switch module 10, the switch module 10 includes a switch unit 11, the switch unit 11 includes a control end 103, a third end 101 and a fourth end 102, the third end 101 of the switch unit 11 corresponds to the fourth end 102 of the switch unit 11 one-to-one; the first end 201 has a corresponding third end 101; the control end 103 of the switch unit 11 is used to be electrically connected to the reset signal receiving end 203 of the chip 20, the third end 101 of the switch unit 11 is electrically connected to the first end 201 of the chip 20; the fourth end 102 of the switch unit 11 is electrically connected to the second end 301 of the external device 30.

[0042] For example, refer to Figure 3 The chip 20 has a corresponding external device 30, the chip 20 includes eight first terminals 201, and the external device 30 includes eight second terminals 301, and the first terminals 201 correspond to the second terminals 301 one-to-one; the interaction circuit between the chip and the external device includes a switch module 10, the switch module 10 includes a switch unit 11, the switch unit 11 includes a control terminal 103, eight third terminals 101 and eight fourth terminals 102, and the third terminal 101 of the switch unit 11 corresponds to the fourth terminal 102 of the switch unit 11 one-to-one; the first terminal 201 has a corresponding third terminal 101; the control terminal 103 is used to be electrically connected to the reset signal receiving terminal 203 of the chip 20; the third terminal 101 is electrically connected to the first terminal 201 corresponding to the third terminal 101; the fourth terminal 102 corresponding to the third terminal 101 is electrically connected to the second terminal 301 corresponding to the first terminal 201 electrically connected to the third terminal 101.

[0043] For example, refer to Figure 4The chip 20 has a corresponding external device 30, the chip 20 includes two first terminals 201, and the external device 30 includes two second terminals 301, and the first terminal 201 corresponds to the second terminal 301 one-to-one; the interaction circuit between the chip and the external device includes a switch module 10, the switch module 10 includes two switch units 11, each switch unit 11 includes a control terminal 103, a third terminal 101 and a fourth terminal 102, and the third terminal 101 of the switch unit 11 corresponds to the fourth terminal 102 of the switch unit 11 one-to-one; the first terminal 201 has a corresponding third terminal 101; each control terminal 103 is used to be electrically connected to the reset signal receiving terminal 203 of the chip 20; the third terminal 101 is electrically connected to the first terminal 201 corresponding to the third terminal 101; the fourth terminal 102 corresponding to the third terminal 101 is electrically connected to the second terminal 301 corresponding to the first terminal 201 electrically connected to the third terminal 101.

[0044] In an embodiment of the present utility model, when the reset signal obtained by the reset signal receiving end 203 is at the first level, the chip 20 operates normally at this time, and the third end 101 of the switch unit 11 is controlled by the switch unit 11 to be turned on with the fourth end 102 corresponding to the third end 101 of the switch unit 11, so that the chip 20 is connected and interacts with the external device 30; when the reset signal is at the second level, the chip 20 is reset or powered on at this time, and the third end 101 of the switch unit 11 is controlled by the switch unit 11 to be disconnected with the fourth end 102 corresponding to the third end 101 of the switch unit 11, so that the chip 20 is disconnected from the external device 30, so as to avoid the interference signal generated by the general input and output port of the chip 20 being transmitted to the external device 30 when the chip 20 is powered on or reset, causing the external device 30 to be in an abnormal state.

[0045] Optionally, in some embodiments, when the switch unit 11 is a switching device, the switch unit 11 includes one control terminal 103, one third terminal 101 and one fourth terminal 102; when the switch unit 11 is a phase shifter chip, the switch unit 11 includes one control terminal 103, multiple third terminals 101 and multiple fourth terminals 102.

[0046] For example, refer to Figure 2 The switch unit 11 is a switch device, and the switch unit 11 includes a control terminal 103 , a third terminal 101 and a fourth terminal 102 .

[0047] For example, refer to Figure 3 The switch unit 11 is a phase shifter chip, and includes a control terminal 103 , eight third terminals 101 and eight fourth terminals 102 .

[0048] In an embodiment of the present invention, when the switch unit 11 is a switching device, the switch unit 11 can control the conduction and disconnection of a third end 101 and the fourth end 102 corresponding to the third end 101; when the switch unit 11 is a phase shifter chip, the switch unit 11 can control the conduction and disconnection of multiple third ends 101 and the fourth end 102 corresponding to the third end 101.

[0049] Optionally, in some embodiments, the switching device includes a MOS tube and / or a transistor.

[0050] It should be noted that MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transistor) include PMOS tubes (positive channel Metal Oxide Semiconductor) and NMOS tubes (Negative channel-Metal-Oxide-Semiconductor).

[0051] Transistors include NPN transistors and PNP transistors. Among them, the NPN transistor is composed of three semiconductors, including two N (Negative Electricity) type semiconductors (electron semiconductors) and one P (Positive Electricity) type semiconductor (hole semiconductor), with the P-type semiconductor in the middle and two N-type semiconductors on both sides; the PNP transistor is composed of three semiconductors, including one N-type semiconductor and two P-type semiconductors, with the N-type semiconductor in the middle and two P-type semiconductors on both sides.

[0052] Specifically, in some embodiments, when the chip 20 is powered on or reset, the reset signal received by the chip 20 through the reset signal receiving end 203 is at a low level; when the chip 20 is working normally, the reset signal is at a high level, and the switching device is an NMOS tube or an NPN transistor; when the switching device is an NMOS tube, the third end 101 of the switching unit 11 is the drain of the NMOS tube, the fourth end 102 of the switching unit 11 is the source of the NMOS tube, and the control end 103 of the switching unit 11 is the gate of the NMOS tube; when the switching device is an NPN transistor, the third end 101 of the switching unit 11 is the collector of the NPN transistor, the fourth end 102 of the switching unit 11 is the emitter of the NPN transistor, and the control end 103 of the switch unit 11 is the base of the NPN transistor.

[0053] In other embodiments, when the chip 20 is powered on or reset, the reset signal received by the chip 20 through the reset signal receiving end 203 is a high level; when the chip 20 is working normally, the reset signal is a low level, and the switching device is a PMOS tube or a PNP type transistor; when the switching device is a PMOS tube, the third end 101 of the switch unit 11 is the source of the PMOS tube, the fourth end 102 of the switch unit 11 is the drain of the PMOS tube, and the control end 103 of the switch unit 11 is the gate of the PMOS tube; when the switching device is a PNP type transistor, the third end 101 of the switch unit 11 is the emitter of the PNP type transistor, the fourth end 102 of the switch unit 11 is the collector of the PNP type transistor, and the control end 103 of the switch unit 11 is the base of the PNP type transistor.

[0054] For example, refer to Figure 2 The chip 20 has a corresponding external device 30, the chip 20 includes a first end 201, the external device 30 includes a second end 301, and the first end 201 corresponds to the second end 301 one-to-one; the interaction circuit between the chip and the external device includes a switch module 10, the switch module 10 includes a switch unit 11, the switch unit 11 is an NMOS tube, the switch unit 11 includes a control end 103, a third end 101 and a fourth end 102, the third end 101 of the switch unit 11 corresponds to the fourth end 102 of the switch unit 11 one-to-one; the first end 201 has a corresponding third end 101; the control end 103 of the switch unit 11 is used to be electrically connected to the reset signal receiving end 203 of the chip 20, the third end 101 of the switch unit 11 is electrically connected to the first end 201 of the chip 20; the fourth end 102 of the switch unit 11 is electrically connected to the second end 301 of the external device 30.

[0055] In the embodiment of the present invention, when the switch unit 11 is a MOS transistor or a triode, the switch unit 11 can control the on / off of a third terminal 101 and a fourth terminal 102 corresponding to the third terminal 101 .

[0056] Optionally, in some embodiments, the types of the switch units 11 in the switch module 10 are all the same, partially the same, or all different, and the types of the switch units 11 include switch devices and phase regulator chips.

[0057] For example, refer to Figure 4The chip 20 has a corresponding external device 30. The chip 20 includes two first terminals 201, and the external device 30 includes two second terminals 301. The first terminals 201 correspond to the second terminals 301 one-to-one. The interactive circuit between the chip and the external device includes a switch module 10. The switch module 10 includes two switch units 11. The two switch units 11 are all of the same type. Both switch units 11 are NMOS tubes. Each switch unit 11 includes a control terminal 103, a third terminal 101 and a fourth terminal 102. The third terminal 101 of the switch unit 11 corresponds to the fourth terminal 102 of the switch unit 11 one-to-one. The first terminal 201 has a corresponding third terminal 101. Each control terminal 103 is used to be electrically connected to the reset signal receiving terminal 203 of the chip 20. The third terminal 101 is electrically connected to the first terminal 201 corresponding to the third terminal 101. The fourth terminal 102 corresponding to the third terminal 101 is electrically connected to the second terminal 301 corresponding to the first terminal 201 electrically connected to the third terminal 101.

[0058] For example, refer to Figure 5 The chip 20 has a corresponding external device 30. The chip 20 includes nine first terminals 201. The external device 30 includes nine second terminals 301. The first terminals 201 correspond to the second terminals 301 one by one. The interactive circuit between the chip and the external device includes a switch module 10. The switch module 10 includes two switch units 11. The types of the two switch units 11 are all different. One switch unit 11 is a phase shifter chip, and the other switch unit 11 is an NMOS tube. The switch unit 11 of the phase shifter chip includes a control terminal 103, eight third terminals 101 and eight fourth terminals 103. 2. The switch unit 11 of the NMOS transistor includes a control terminal 103, a third terminal 101, and a fourth terminal 102; the third terminal 101 of the switch unit 11 corresponds one-to-one with the fourth terminal 102 of the switch unit 11; the first terminal 201 has a corresponding third terminal 101; each control terminal 103 is used to be electrically connected to the reset signal receiving terminal 203 of the chip 20; the third terminal 101 is electrically connected to the first terminal 201 corresponding to the third terminal 101; the fourth terminal 102 corresponding to the third terminal 101 is electrically connected to the second terminal 301 corresponding to the first terminal 201 electrically connected to the third terminal 101.

[0059] For example, refer to Figure 6The chip 20 has a corresponding external device 30. The chip 20 includes ten first terminals 201, and the external device 30 includes ten second terminals 301. The first terminals 201 correspond to the second terminals 301 one by one. The interactive circuit between the chip and the external device includes a switch module 10. The switch module 10 includes three switch units 11. The three switch units 11 are of the same type. One switch unit 11 is a phase shifter chip, and the other two switch units 11 are NMOS tubes. The switch unit 11 of the phase shifter chip includes a control terminal 103, eight third terminals 101, and eight fourth terminals 103. 2. The switch unit 11 of the NMOS transistor includes a control terminal 103, a third terminal 101, and a fourth terminal 102; the third terminal 101 of the switch unit 11 corresponds one-to-one with the fourth terminal 102 of the switch unit 11; the first terminal 201 has a corresponding third terminal 101; each control terminal 103 is used to be electrically connected to the reset signal receiving terminal 203 of the chip 20; the third terminal 101 is electrically connected to the first terminal 201 corresponding to the third terminal 101; the fourth terminal 102 corresponding to the third terminal 101 is electrically connected to the second terminal 301 corresponding to the first terminal 201 electrically connected to the third terminal 101.

[0060] In an embodiment of the present invention, the type of the switch unit 11 can be selected according to the number of external devices 30 electrically connected to the chip 20 and the number of ports of the external devices 30. The types of the switch units 11 in the switch module 10 can be all the same, partially the same, or all different to adapt to different scenarios of interaction between the chip 20 and the external devices 30.

[0061] Optionally, in some embodiments, the interaction circuit between the chip and the external device further includes at least one resistor 40, each of the resistors 40 includes a fifth end 401 and a sixth end 402; each of the second ends 301 has a corresponding fifth end 401; the fifth end 401 is electrically connected to the second end 301 corresponding to the fifth end 401; and the sixth end 402 is used to be electrically connected to an external power supply or to ground.

[0062] For example, refer to Figure 2 The external device 30 includes a second end 301, and the interactive circuit between the chip and the external device includes a resistor 40. The fifth end 401 of the resistor 40 is electrically connected to the second end 301 of the external device 30, and the sixth end 402 of the resistor 40 is used to be electrically connected to an external power supply or grounded.

[0063] For example, refer to Figure 3The external device 30 includes eight second terminals 301, and the interactive circuit between the chip and the external device also includes eight resistors 40, each resistor 40 includes a fifth terminal 401 and a sixth terminal 402; each second terminal 301 has a corresponding fifth terminal 401; the fifth terminal 401 is electrically connected to the second terminal 301 corresponding to the fifth terminal 401; the sixth terminal 402 is used to be electrically connected to an external power supply or to be grounded.

[0064] In an embodiment of the present utility model, the fifth end 401 of the resistor 40 is electrically connected to the second end 301 of the external device 30 corresponding to the fifth end 401, and the sixth end 402 of the resistor 40 is electrically connected to the external power supply, so that the resistor 40 is a pull-up resistor 40 of the second end 301 of the external device 30; the fifth end 401 of the resistor 40 is electrically connected to the second end 301 of the external device 30 corresponding to the fifth end 401, and the sixth end 402 of the resistor 40 is grounded, so that the resistor 40 is a pull-down resistor 40 of the second end 301 of the external device 30.

[0065] Optionally, in some embodiments, the chip 20 further includes a reset terminal 202 , and the reset signal receiving terminal 203 is electrically connected to the reset terminal 202 .

[0066] In an embodiment of the present invention, the reset terminal 202 of the chip 20 is electrically connected to the reset signal receiving terminal 203, so that the chip 20 can receive the reset signal. When the reset signal is at the first level, the chip 20 works normally. When the reset signal is at the second level, the chip 20 is reset or powered on.

[0067] Optionally, in some embodiments, the type of the first end 201 is GPIO, and / or the type of the second end 301 is GPIO.

[0068] In an embodiment of the present utility model, the first end 201 of the chip 20 and the second end 301 of the external device 30 are both GPIOs. When the reset signal obtained by the reset signal receiving end 203 is a first level, the chip 20 works normally at this time. The third end 101 is controlled by the switch module 10 to be connected with the fourth end 102 corresponding to the third end 101, so that the chip 20 is connected with the external device 30, and communication between the chip 20 and the external device 30 can be realized.

[0069] An embodiment of the present invention further provides a mainboard, comprising an interactive circuit between the chip and an external device as described in the first aspect.

[0070] The specific implementation method of the interactive circuit between the chip in the mainboard and the external device is similar to the specific implementation method of the interactive circuit between the chip and the external device mentioned above, and will not be repeated here.

[0071] An embodiment of the present invention further provides an electronic device, comprising an interactive circuit between the chip and an external device as described in the first aspect, or a mainboard as described in the second aspect.

[0072] The specific implementation of the interactive circuit between the chip in the electronic device and the external device is similar to the specific implementation of the interactive circuit between the chip and the external device described above, and will not be repeated here.

[0073] In some embodiments, the process of powering on the chip 20 is as follows: when the chip 20 is powered on, the reset signal receiving end 203 always maintains a low level, so that the switch unit 11 is in the off state, the second end 301 of the external device 30 is always in the off-circuit high-impedance state, and the level of the second end 301 of the external device 30 is maintained by the pull-up resistor 40 or the pull-down resistor 40; at the same time, since the second end 301 of the external device 30 is always in the off-circuit state, it can be avoided that the second end 301 of the external device 30 leaks to the chip 20 when the external device 30 is powered on earlier than the chip 20; after the chip 20 is powered on, the reset signal receiving end 203 is pulled high, the chip 20 is reset, the first end 201 of the chip 20 can be controlled normally, and at the same time the switch unit 11 opens the path, and the state of the second end 301 of the external device 30 follows the state of the first end 201 of the chip 20 corresponding to the second end 301 of the previous stage.

[0074] In related technologies, the chip is directly electrically connected to the external device through wires. When the chip is powered on or reset, the universal input and output port of the external device generates an interference signal, which is transmitted to the universal input and output port of the chip through the wires, causing abnormal power-on or reset of the chip.

[0075] In an embodiment of the present invention, when the reset signal is at the second level, the chip 20 is reset or powered on, and the third end 101 is controlled by the switch module 10 to be disconnected from the fourth end 102 corresponding to the third end 101, so that the chip 20 is disconnected from the external device 30, so as to avoid the general input and output port of the external device 30 generating an interference signal (such as leakage) when the chip 20 is powered on or reset, and the interference signal is transmitted to the general input and output port of the chip 20 through the wire, causing abnormal power-on or reset of the chip 20.

[0076] In summary, in the embodiment of the present invention, since the third end 101 of the switch module 10 is electrically connected to the first end 201 of the chip 20 corresponding to the third end 101, the fourth end 102 of the switch module 10 corresponding to the third end 101 is electrically connected to the second end 301 of the external device 30 corresponding to the first end 201, and the control end 103 of the switch module 10 is used to be electrically connected to the reset signal receiving end 203 of the chip 20, then when the reset signal received by the reset signal receiving end 203 is the first level, the chip 20 works normally, and the switch module 10 controls the third end 101 and the fourth end 102 corresponding to the third end 101 to be turned on, so that the chip 20 is connected and interacts with the external device 30; when the reset signal is at the second level, the chip 20 is reset or powered on, and the third end 101 and the fourth end 102 corresponding to the third end 101 are controlled to be disconnected through the switch module 10, so that the chip 20 is disconnected from the external device 30, so as to avoid the interference signal generated by the universal input and output port of the chip 20 being transmitted to the external device 30 when the chip 20 is powered on or reset, causing the external device 30 to be in an abnormal state.

[0077] Finally, it should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprise" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or terminal device that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements that are inherent to such process, method, article, or terminal device.

[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0079] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An interactive circuit between a chip and an external device, characterized in that: Applied to a chip (20), the chip (20) has at least one corresponding external device (30), the chip (20) includes at least one first terminal (201), each external device (30) corresponding to the chip (20) includes at least one second terminal (301), and the first terminal (201) and the second terminal (301) are in one-to-one correspondence; an interactive circuit between the chip and the external device includes a switch module (10), the switch module (10) includes at least one control terminal (103), at least one third terminal (101) and at least one fourth terminal (102), and the third terminal (101) and the fourth terminal (102) are in one-to-one correspondence; each first terminal (201) has a corresponding third terminal (101); Each of the control terminals (103) is used to be electrically connected to a reset signal receiving terminal (203) of the chip (20); The third end (101) is electrically connected to the first end (201) corresponding to the third end (101); the fourth end (102) corresponding to the third end (101) is electrically connected to the second end (301) corresponding to the first end (201) electrically connected to the third end (101); The switch module (10) is used to control the third end (101) and the fourth end (102) corresponding to the third end (101) to be connected when the reset signal obtained by the reset signal receiving end (203) is at a first level; and to control the third end (101) and the fourth end (102) corresponding to the third end (101) to be disconnected when the reset signal is at a second level.

2. The chip-to-external-device interaction circuit according to claim 1, characterized in that: The switch module (10) comprises at least one switch unit (11), each switch unit (11) comprises at least one control terminal (103), at least one third terminal (101) and at least one fourth terminal (102), and the third terminal (101) of the switch unit (11) corresponds to the fourth terminal (102) of the switch unit (11) in one-to-one correspondence; The switch unit (11) is used to control the third end (101) of the switch unit (11) and the fourth end (102) corresponding to the third end (101) of the switch unit (11) to be turned on when the reset signal is at the first level; and to control the third end (101) of the switch unit (11) and the fourth end (102) corresponding to the third end (101) of the switch unit (11) to be turned off when the reset signal is at the second level.

3. The chip-to-external-device interaction circuit according to claim 2, characterized in that: In the case where the switch unit (11) is a switch device, the switch unit (11) includes a control terminal (103), a third terminal (101), and a fourth terminal (102); In the case where the switch unit (11) is a phase detector chip, the switch unit (11) includes one control terminal (103), a plurality of third terminals (101), and a plurality of fourth terminals (102).

4. The chip-to-external-device interaction circuit according to claim 2, wherein: The types of the switch units (11) in the switch module (10) are all the same, partially the same, or all different, and the types of the switch units (11) include switch devices and phase regulator chips.

5. The chip-to-external-device interaction circuit according to claim 3 or 4, characterized in that: The switching device includes a MOS tube and / or a triode.

6. The chip-to-external-device interaction circuit according to any one of claims 1 to 4, characterized in that: The interaction circuit between the chip and the external device further comprises at least one resistor (40), each resistor (40) comprising a fifth terminal (401) and a sixth terminal (402); each second terminal (301) has a corresponding fifth terminal (401); The fifth end (401) is electrically connected to the second end (301) corresponding to the fifth end (401); The sixth end (402) is used for being electrically connected to an external power source or being grounded.

7. The chip-to-external-device interaction circuit according to any one of claims 1 to 4, characterized in that: The chip (20) further includes a reset terminal (202), and the reset signal receiving terminal (203) is electrically connected to the reset terminal (202).

8. The chip-to-external-device interaction circuit according to any one of claims 1 to 4, characterized in that: The type of the first end (201) is GPIO, and / or the type of the second end (301) is GPIO.

9. A motherboard, characterized in that: A circuit comprising an interaction circuit between the chip according to any one of claims 1 to 8 and an external device.

10. An electronic device, characterized in that: The invention comprises an interactive circuit between a chip and an external device as claimed in any one of claims 1 to 8, or a mainboard as claimed in claim 9.

Images