Quasi-super junction planar gate silicon carbide VDMOS

Abstract

The utility model provides a quasi-super junction planar gate silicon carbide VDMOS. The lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate, and the lower part of the drift layer is provided with a plurality of N-type body regions; a plurality of P-type diffusion regions are arranged at the upper part of the drift layer, the lower side surface of each N-type body region is connected to the upper side surface of the silicon carbide substrate, a lug boss is arranged on the drift layer, and a current equalizing layer is arranged in the lug boss; the lower side surface of the P-type well region is connected to the upper side surface of the drift layer and the upper side surface of the P-type diffusion region; the inner side surface of the P-type well region is connected to the outer side surface of the lug boss; an N-type source region is arranged in the P-type well region; the gate dielectric layer is respectively connected with the P-type well region, the drift layer and the current sharing layer; the gate metal layer is connected to the gate dielectric layer; the source metal layer is respectively connected with the P-type well region and the N-type source region; the drain metal layer is connected to the lower side surface of the silicon carbide substrate, a quasi-super junction structure and a current sharing layer are constructed in the device, and the voltage endurance capability, the gate reliability and the conduction capability of the device can be effectively improved.

Description

Technical Field

[0001] The utility model relates to a quasi-super junction planar gate silicon carbide VDMOS. Background Art

[0002] Silicon carbide VDMOS is a typical example of silicon carbide power devices, widely used in electric vehicles, aerospace, power conversion, and other fields. While different fields place varying emphasis on device performance requirements for silicon carbide power VDMOS, the overall requirements include higher voltage withstand capability, lower on-resistance, faster switching speeds, and higher reliability (including gate reliability, drain voltage surge reliability, and short-circuit reliability). Furthermore, silicon carbide VDMOS constructs an insulating dielectric region directly beneath the planar gate. The P-type well region and the N-type drift region directly beneath the gate metal layer naturally form a space charge region. However, as the distance from the P-type well region increases, the depth of the space charge region decreases, making it increasingly difficult to withstand high drain voltages. Utility Model Content

[0003] The technical problem to be solved by the present invention is to provide a quasi-superjunction planar gate silicon carbide VDMOS, which constructs a quasi-superjunction structure and a current-sharing layer inside the device, which can effectively improve the device's voltage resistance, gate reliability and conduction capability.

[0004] The utility model provides a quasi-superjunction planar gate silicon carbide VDMOS, comprising:

[0005] Silicon carbide substrate,

[0006] a drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, a plurality of N-type body regions are provided at the lower portion of the drift layer; a plurality of P-type diffusion regions are provided at the upper portion of the drift layer, the lower side of each N-type body region is connected to the upper side of the silicon carbide substrate, a raised portion is provided on the drift layer, and a current equalizing layer is provided within the raised portion;

[0007] A P-type well region, wherein the lower side of the P-type well region is connected to the upper side of the drift layer and the upper side of the P-type diffusion region, and the inner side of the P-type well region is connected to the outer side of the protrusion; an N-type source region is provided in the P-type well region;

[0008] a gate dielectric layer, the gate dielectric layer being connected to the P-type well region, the drift layer and the current-balancing layer respectively;

[0009] a gate metal layer connected to the gate dielectric layer;

[0010] a source metal layer, the source metal layer being connected to the P-type well region and the N-type source region respectively;

[0011] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0012] The advantages of the present invention are:

[0013] 1. The present invention constructs a quasi-superjunction device structure, specifically including a P-type diffusion region and an N-type body region that are laterally cross-distributed, transforming the vertically distributed electric field into a combined horizontal and vertical electric field distribution, thereby improving the device's withstand voltage capability;

[0014] Second, a current-sharing layer is constructed directly below the planar gate, which increases the doping concentration in the JFET region of the device and effectively reduces the JFET resistance and overall on-resistance of the device.

[0015] 3. The gate of the device adopts a convex structure, and the thickness of the gate dielectric is increased above the N-type current balancing layer, which can effectively improve the gate reliability of the N-type current balancing layer area and improve the ability to resist drain voltage shock. At the same time, the gate dielectric thickness remains unchanged from the N-type source region to the JFET region (including the N-type current balancing layer directly below the gate and the N-type drift layers on its left and right sides), which does not affect the gate control capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0017] Figure 1 This is a schematic diagram of a quasi-superjunction planar gate silicon carbide VDMOS according to the present invention.

[0018] Figure 2 This is a cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS in this utility model. Figure 1 .

[0019] Figure 3 This is a cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS in this utility model. Figure 2 .

[0020] Figure 4 This is a cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS in this utility model. Figure 3 .

[0021] Figure 5 This is a cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS in this utility model. Figure 4 .

[0022] Figure 6 This is a cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS in this utility model. Figure 5 .

[0023] Figure 7 This is a cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS in this utility model. Figure 6 .

[0024] Figure 8 This is a cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS in this utility model. Figure 7 .

[0025] Figure 9 This is a cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS in this utility model. Figure 8 .

[0026] Figure 10 This is a cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS in this utility model. Figure 9 .

[0027] Figure 11 This is a cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS in this utility model. Figure 10 . DETAILED DESCRIPTION

[0028] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0030] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0031] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0032] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] like Figure 1 As shown, the embodiment of the present application provides a quasi-superjunction planar gate silicon carbide VDMOS, including:

[0034] Silicon carbide substrate 1,

[0035] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, and a plurality of N-type body regions 21 are provided at the lower portion of the drift layer 2; a plurality of P-type diffusion regions 22 are provided at the upper portion of the drift layer 2, and the lower side of each of the N-type body regions 21 is connected to the upper side of the silicon carbide substrate 1; a raised portion 23 is provided on the drift layer 2, and a current equalizing layer 231 is provided within the raised portion 23;

[0036] A P-type well region 3, wherein the lower side of the P-type well region 3 is connected to the upper side of the drift layer 2 and the upper side of the P-type diffusion region 22, and the inner side of the P-type well region 3 is connected to the outer side of the protrusion 23; an N-type source region 31 is provided in the P-type well region 4;

[0037] a gate dielectric layer 4, wherein the gate dielectric layer 4 is respectively connected to the P-type well region 3, the drift layer 2 and the current-balancing layer 231;

[0038] a gate metal layer 5 connected to the gate dielectric layer 4;

[0039] a source metal layer 6 , the source metal layer 6 being connected to the P-type well region 3 and the N-type source region 31 ;

[0040] and a drain metal layer 7 , wherein the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1 .

[0041] In this embodiment, preferably, the gate dielectric layer 4 is provided with a protrusion 41, the width of the protrusion 41 is equal to the width of the current equalizing layer 231, and the gate metal layer 5 is an inverted concave shape; the thickness of the N-type body region 21 is 50% of the thickness of the drift layer; the thickness of the P-type diffusion region 22 is 30% of the thickness of the drift layer 2; the N-type body region 21 and the P-type diffusion region 22 are arranged at intervals in the vertical direction, that is, the diffusion region 22 is not directly above the N-type body region 21; the doping concentration of the N-type body region 21 is greater than the doping concentration of the drift layer 2, and the doping concentration of the P-type diffusion region 22 is greater than the doping concentration of the N-type body region 21.

[0042] like Figures 1 to 11 As shown, the method for preparing the silicon carbide VDMOS comprises the following steps:

[0043] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 7; epitaxially growing the side of the silicon carbide substrate 1 to form a drift layer 2;

[0044] Step 2: forming a barrier layer 8 above the drift layer 2, etching the barrier layer 8 to form through holes, and performing ion implantation into the drift layer 2 to form a plurality of N-type body regions 21;

[0045] Step 3: remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form through holes, and perform ion implantation into the drift layer 2 to form a plurality of diffusion regions 22;

[0046] Step 4: remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and perform ion implantation into the drift layer 2 to form a P-type well region 3;

[0047] Step 5: remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and perform ion implantation into the P-type well region 3 to form an N-type source region 31;

[0048] Step 6: remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and perform ion implantation into the drift layer 2 to form a current balancing layer 231, wherein the current balancing layer 231 is located in the raised portion 23 of the drift layer 2;

[0049] Step 7: Remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and deposit a first insulating dielectric layer 42; remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and deposit a second insulating dielectric layer 43; the gate dielectric layer 4 includes the first insulating dielectric layer 42 and the second insulating dielectric layer 43; the width of the second insulating dielectric layer 43 is equal to the width of the current-balancing layer 231; the second insulating layer 43 is the protrusion 41 of the gate dielectric layer 4;

[0050] Step 8: removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and depositing metal to form a gate metal layer 5, wherein the gate metal layer 5 is an inverted concave shape;

[0051] Step 9: remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, deposit metal to form a source metal layer 6, remove the barrier layer 8, and complete the preparation.

[0052] In another embodiment of the present invention, the silicon carbide substrate 1, the drift layer 2 and the current-balancing layer 231 are all N-type; the diffusion region 22 is P-type; the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e17cm -3 The doping concentration of the N-type current balancing layer 231 is 0.8-1.2e18cm -3 , the doping concentration of the N-type body region 21 is 5-8e17cm -3 , the doping concentration of the P-type diffusion region 22 is 0.8-2e18 cm -3 The doping concentration of the P-type well region 3 is 5-8e17 cm -3 The gate dielectric layer 4 is silicon dioxide, and the doping concentration of the N-type source region 31 is 2-8e18cm -3 ;

[0053] The doping concentration of the N-type silicon carbide substrate 1 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 7, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device; the function of the N-type current equalizing layer 231 is to increase the doping concentration of the JFET region of the device, reduce the resistance of the JFET region of the device, and thereby reduce the on-resistance of the device; the N-type body region 21 is to transfer the potential of the drain upward, and then form a horizontally and vertically combined withstand voltage structure with the P-type diffusion region 22, thereby improving the withstand voltage of the device; the P-type well region 3 is to form the vertical withstand voltage structure of the device and the gate control structure of the device; the N-type source region 31 is to form a low-resistance ohmic contact with the source metal layer 6.

[0054] The thickness of the N-type silicon carbide substrate 1 of the device is 1μm, and the thickness of the N-type drift layer 2 is 10-30μm. It is adjusted within the above range according to the different requirements for the device's withstand voltage characteristics. The thickness of the N-type body region 21 is 50% of the thickness of the N-type drift layer 2. This is to achieve upward transfer of potential; the thickness of the P-type diffusion region 22 is 30% of the thickness of the N-type drift layer 2. This is to form a horizontal and vertical combined electric field distribution with the N-type body region 21, thereby achieving a structure that can withstand voltage in both the horizontal and vertical directions, thereby improving the device's withstand voltage capability; N-type The thickness of the current-balancing layer 231 is 300nm, the thickness of the N-type source region 31 is 100nm, the thickness of the P-type well region 3 below the N-type source region 31 is 200nm, and the thickness of the P-type well region 3 is 300nm. This is to ensure the device's voltage resistance and gate control capability. The gate dielectric thickness directly above the N-type current-balancing layer 231 is 100nm, and the gate dielectric thickness in other areas is 50nm. This is to improve the reliability of the gate above the N-type source region. The source metal layer 6 is 200nm thick, and the gate metal layer 5 is 150nm thick.

[0055] The gate dielectric layer 4 of the present invention is convex in shape and has the ability to withstand high voltage, which can effectively improve the gate's ability to withstand the impact of drain voltage and improve device reliability. The distance from the bottom of the P-type diffusion region 22 to the top of the N-type body region 21 is 20% of the thickness of the N-type drift layer. The small thickness of the P-type diffusion region 22 is because the doping concentrations of the N-type drift layer 2 and the N-type body region 21 are both lower than those of the P-type diffusion layer 22. The doping concentration relationship can ensure that the distribution of the space charge region during reverse withstand voltage does not affect the structure of the device's P-type well region 3. The P-type diffusion region 22 and the N-type body region 21 are cross-distributed. This cross-distribution method allows the space charge region to diffuse both upward and horizontally in the P-type diffusion region 22 and the N-type body region 21 during reverse withstand voltage, transforming the vertically distributed electric field into a combined horizontal and vertical electric field distribution, constructing a quasi-superjunction structure, thereby improving the device's withstand voltage capability.

[0056] An N-type current-balancing layer 231 is constructed directly below the planar gate, which increases the doping concentration of the device's JFET region, effectively reducing the device's JFET resistance and overall on-resistance. The device's gate dielectric layer 4 adopts a convex structure, and the thickness of the gate dielectric is increased above the N-type current-balancing layer 231, which can effectively improve the gate reliability of the N-type current-balancing layer 231 region and enhance the ability to resist drain voltage shocks. At the same time, the gate dielectric thickness remains unchanged from the N-type source region to the JFET region (including the N-type current-balancing layer directly below the gate and the N-type drift layers on its left and right sides), without affecting the device's gate control capability.

[0057] The device of this embodiment realizes a quasi-superjunction structure to improve the device's voltage resistance. The N-type current balancing layer 231 reduces the device's on-resistance. The convex gate dielectric improves the device's gate reliability.

[0058] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A quasi-superjunction planar gate silicon carbide VDMOS, characterized by: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and a plurality of N-type body regions are provided at the lower portion of the drift layer; A plurality of P-type diffusion regions are provided on the upper portion of the drift layer, the lower side of each N-type body region is connected to the upper side of the silicon carbide substrate, a convex portion is provided on the drift layer, and a current equalizing layer is provided in the convex portion; A P-type well region, wherein the lower side of the P-type well region is connected to the upper side of the drift layer and the upper side of the P-type diffusion region, and the inner side of the P-type well region is connected to the outer side of the protrusion; an N-type source region is provided in the P-type well region; a gate dielectric layer, the gate dielectric layer being connected to the P-type well region, the drift layer and the current-balancing layer respectively; a gate metal layer connected to the gate dielectric layer; a source metal layer, the source metal layer being connected to the P-type well region and the N-type source region respectively; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. The quasi-superjunction planar gate silicon carbide VDMOS according to claim 1, wherein: The gate dielectric layer is provided with a protrusion, the width of the protrusion is equal to the width of the current-balancing layer, and the gate metal layer is in an inverted concave shape.

3. The quasi-superjunction planar gate silicon carbide VDMOS according to claim 1, wherein: The thickness of the N-type body region is 50% of the thickness of the drift layer.

4. The quasi-superjunction planar gate silicon carbide VDMOS according to claim 1, wherein: The thickness of the P-type diffusion region is 30% of the thickness of the drift layer.

5. The quasi-superjunction planar gate silicon carbide VDMOS according to claim 1, wherein: The N-type body region and the P-type diffusion region are spaced apart in the vertical direction.

6. The quasi-superjunction planar gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the N-type body region is greater than the doping concentration of the drift layer, and the doping concentration of the P-type diffusion region is greater than the doping concentration of the N-type body region.

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