Display module

Abstract

The utility model provides a display module, and relates to the technical field of display, the display module comprises a time sequence control circuit, a plurality of driving circuits and a display panel; the input end of the driving circuit is electrically connected with the output end of the time sequence control circuit; the output end of the driving circuit is electrically connected with the input end of the display panel; the plurality of driving circuits are arranged in an array along a first direction, and the plurality of driving circuits are symmetrically distributed about the central axis of the display panel; the central axis extends along a second direction; the first circuit group comprises a first driving circuit and a second driving circuit; the second circuit group is arranged between the first driving circuit and the second driving circuit; the first group of signals are second signals sent to the display panel by the first circuit group, and the second group of signals are second signals sent to the display panel by the second circuit group; a first moment when the display panel receives the first group of signals is greater than a second moment when the display panel receives the second group of signals. Electromagnetic interference of the display module can be reduced, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display module. Background Art

[0002] In LCD modules, point-to-point (P-to-P) signals are commonly used to transmit data between modules. These signals are transmitted using an embedded clock and can also include embedded control instructions. For example, a timing controller (TCON) has independent signal lines connected to each source driver IC, using point-to-point signaling for data transmission.

[0003] Currently, during the display panel driving process, the timing controller (TCON) outputs signals to the source driver IC, which then outputs signals to the display panel. These signals are typically sent synchronously, resulting in high instantaneous energy and easily causing excessive electromagnetic interference (EMI).

[0004] Electromagnetic interference is positively correlated with signal energy. While improvements can be made by using a spread spectrum clock generator (SSCG) to disperse the clock signal's peak energy, adjusting the TCON signal's peak and valley values, and reducing the data stream's energy spectral density through the source driver IC's perturbation function, SSCG is subject to TCON and source driver IC specifications. Signal peak and valley values ​​must meet signal quality requirements, and the perturbation and recovery process carries the risk of data errors. Consequently, improvements are often ineffective and may even affect display quality. Utility Model Content

[0005] The present application provides a display module that can solve the problem that current EMI improvement measures have poor improvement effects and even affect the display effect.

[0006] The present application provides a display module, comprising: a timing control circuit, a plurality of driving circuits and a display panel connected in sequence;

[0007] The input terminal of the driving circuit is electrically connected to the output terminal of the timing control circuit, and the timing control circuit is configured to identify a first signal sent to the driving circuit and control the timing of the first signal;

[0008] The output terminal of the driving circuit is electrically connected to the input terminal of the display panel, and the driving circuit is configured to receive and process the first signal to form a second signal to be input to the display panel;

[0009] The plurality of driving circuits are arranged in an array along a first direction, and the plurality of driving circuits are symmetrically distributed about a central axis of the display panel, the central axis extends along a second direction, and the first direction and the second direction are orthogonal;

[0010] The plurality of driving circuits include a first circuit group and a second circuit group, the first circuit group includes a first driving circuit and a second driving circuit, and the second circuit group is arranged between the first driving circuit and the second driving circuit;

[0011] The second signal includes a first group of signals and a second group of signals, the first group of signals being the second signals sent by the first circuit group to the display panel, and the second group of signals being the second signals sent by the second circuit group to the display panel, wherein the moment when the display panel receives the first group of signals is a first moment, and the moment when the display panel receives the second group of signals is a second moment, and the first moment is greater than the second moment.

[0012] Optionally, there is a first time difference between the first moment and the second moment;

[0013] The first time difference is greater than or equal to 5 bits in width, and the first time difference is less than or equal to 15 bits in width.

[0014] Optionally, the first group of signals has a first slew rate, and the second group of signals has a second slew rate;

[0015] The first slew rate is smaller than the second slew rate.

[0016] Optionally, a rising edge duration of the first group of signals changing from a first level to a second level is a first duration, and a rising edge duration of the second group of signals changing from the first level to the second level is a second duration, wherein the second level is greater than the first level;

[0017] The first duration is greater than the second duration.

[0018] Optionally, the difference between the first duration and the second duration is greater than zero and less than 4 bits in width.

[0019] Optionally, there is a first duration between the rising edge and the falling edge of the first group of signals, and there is a second duration between the rising edge and the falling edge of the second group of signals, wherein,

[0020] The first duration is shorter than the second duration.

[0021] Optionally, the second circuit group includes a third driving circuit and a fourth driving circuit, and the plurality of driving circuit groups further includes a third circuit group;

[0022] A portion of the third circuit group is located between the first drive circuit and the third drive circuit, and another portion of the third circuit group is located between the second drive circuit and the fourth drive circuit;

[0023] The second signal also includes a third group of signals, which are the second signals sent by the third circuit group to the display panel. The moment when the display panel receives the third group of signals is a third moment, which is smaller than the second moment.

[0024] Optionally, the third circuit group includes a fifth driving circuit and a sixth driving circuit, and the plurality of driving circuit groups further include a fourth circuit group;

[0025] A portion of the fourth circuit group is located between the fifth drive circuit and the third drive circuit, and another portion of the third circuit group is located between the sixth drive circuit and the fourth drive circuit;

[0026] The second signal also includes a fourth group of signals, which are the second signals sent by the fourth circuit group to the display panel. The moment when the display panel receives the fourth group of signals is a fourth moment, which is smaller than the third moment.

[0027] Optionally, the fourth circuit group includes a seventh drive circuit and an eighth drive circuit, and the third circuit group further includes a ninth drive circuit and a tenth drive circuit, wherein the ninth drive circuit is located between the third drive circuit and the seventh drive circuit, and the tenth drive circuit is located between the fourth drive circuit and the eighth drive circuit, the ninth drive circuit and the fifth drive circuit are symmetrical with respect to the seventh drive circuit, and the sixth drive circuit and the tenth drive circuit are symmetrical with respect to the eighth drive circuit.

[0028] and / or,

[0029] The second circuit group further includes an eleventh drive circuit and a twelfth drive circuit, wherein the eleventh drive circuit is located between the first drive circuit and the seventh drive circuit, the twelfth drive circuit is located between the second drive circuit and the eighth drive circuit, the eleventh drive circuit and the third drive circuit are symmetrical with respect to the seventh drive circuit, and the twelfth drive circuit and the fourth drive circuit are symmetrical with respect to the eighth drive circuit.

[0030] Optionally, the first time difference is the time difference between the first moment and the second moment, the second time difference is the time difference between the second moment and the third moment, and the third time difference is the time difference between the third moment and the fourth moment;

[0031] The first time difference, the second time difference and the third time difference are equal; and / or,

[0032] The third group of signals has a third slew rate, the fourth group of signals has a fourth slew rate, the first slew rate is smaller than the second slew rate, the second slew rate is smaller than the third slew rate, and the third slew rate is smaller than the fourth slew rate.

[0033] Optionally, the display module further includes a plurality of differential signal lines;

[0034] One end of the differential signal line is electrically connected to an output end of the timing control circuit, and the other end of the differential signal line is electrically connected to an input end of the driving circuit;

[0035] The first signal is a differential signal sent by the timing control circuit to the driving circuit, and the timing at which the timing control circuit sends the differential signal to the plurality of driving circuits is different.

[0036] Optionally, in a direction away from the central axis, the time difference between the timing control circuit sending the differential signal to two adjacent driving circuits is P bit widths, where P is a positive integer.

[0037] Optionally, the time when the timing control circuit sends the differential signal to the first circuit group is the fifth time, and the time when the timing control circuit sends the differential signal to the second circuit group is the sixth time;

[0038] The time difference between the fifth moment and the sixth moment is X bit width, where X is a positive integer.

[0039] Optionally, the number of the driving circuits is N;

[0040] N is an odd number, and the driving circuit located on the central axis is the first driving circuit of the timing control circuit to send the differential signal.

[0041] Alternatively, N is an even number, and the two driving circuits located on both sides of the central axis and closest to the central axis are the first driving circuits of the timing control circuit to send the differential signal.

[0042] Optionally, the first driving circuit among the multiple driving circuits that sends the second signal to the display panel is a target driving circuit, and the target driving circuit belongs to the second circuit group;

[0043] The time when the display panel receives the second signal sent by the target driving circuit is a target time, and the time difference between the first time and the target time is greater than or equal to 15 bit widths and less than 325 bit widths;

[0044] The time difference between the second moment and the target moment is greater than or equal to 0 and less than a width of 15 bits.

[0045] Optionally, the driving circuit further comprises a plurality of signal lines; the display panel further comprises a plurality of data lines; the plurality of signal lines are electrically connected to the data lines of the display panel to serve as channels for transmitting source signals;

[0046] The signal lines in different driving circuits receive the source signal at different times, and / or the signal lines in different driving circuits send the source signal at different times.

[0047] Optionally, the plurality of signal lines are arranged along the first direction;

[0048] The first target signal line is one of the plurality of signal lines, and a timing at which the first target signal line sends the source signal is greater than a timing at which the other signal lines in the plurality of signal lines send the source signal;

[0049] In a direction away from the first target signal line, a time difference between adjacent signal lines in sending the source signal is S bit widths, where S is a positive integer.

[0050] Optionally, the plurality of signal lines are arranged in sequence along the first direction;

[0051] The first target signal line is the signal line with the largest sequence number among the multiple signal lines, or the first target signal line is the signal line with the smallest sequence number among the multiple signal lines, or the first target signal line is a signal line with a middle sequence number among the multiple signal lines.

[0052] Optionally, the first signal line among the plurality of signal lines that sends the source signal to the connecting line is the second target signal line;

[0053] A time difference between the first target signal line and the second target signal line in sending the source signal is greater than zero and less than a 16-bit width.

[0054] Optionally, the charging time of the display module is greater than or equal to 1.6 microseconds.

[0055] A display module provided by the present application has at least the following advantages: a sequentially connected timing control circuit, multiple driving circuits, and a display panel; an input end of the driving circuit is electrically connected to an output end of the timing control circuit; the timing control circuit is configured to identify a first signal sent to the driving circuit and control the timing of the first signal; the output end of the driving circuit is electrically connected to an input end of the display panel; the driving circuit is configured to receive and process the first signal to form a second signal to be input to the display panel; the multiple driving circuits are arranged in an array along a first direction, and the multiple driving circuits are symmetrically distributed about the central axis of the display panel; the central axis extends along a second direction; the first direction and the second direction are orthogonal; the multiple driving circuits include a first circuit group and a second circuit group; the first circuit group includes a first driving circuit and a second driving circuit; the second circuit group is arranged between the first driving circuit and the second driving circuit; the second signal includes a first group of signals and a second group of signals, the first group of signals being the second signal sent to the display panel by the first circuit group, and the second group of signals being the second signal sent to the display panel by the second circuit group; wherein the moment when the display panel receives the first group of signals is the first moment, and the moment when the display panel receives the second group of signals is the second moment, and the first moment is greater than the second moment. In this way, the display panel receives the first group of signals and the second group of signals at different times, so the energy is dispersed during the transmission of the second signal, reducing the instantaneous energy and thus reducing the EMI noise of the display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0057] Figure 1 This is a schematic diagram of the effect of suppressing EMI by using a spread spectrum clock generator in the related art;

[0058] Figure 2 It is an eye diagram and mask diagram in the related art;

[0059] Figure 3 This is a schematic diagram of the structure of a disturbance function circuit in the related art;

[0060] Figure 4 This is one of the structural diagrams of a display module provided in an embodiment of the present application;

[0061] Figure 5 This is the second structural diagram of a display module provided in an embodiment of the present application;

[0062] Figure 6This is a schematic diagram of a data format of a point-to-point signal in the related art;

[0063] Figure 7 This is a schematic diagram of a display panel screen segmentation in the related art;

[0064] Figure 8 This is a schematic diagram of signal waveforms during a display panel charging process provided by an embodiment of the present application;

[0065] Figure 9 This is a connection diagram of a timing control circuit and a driving circuit provided in an embodiment of the present application;

[0066] Figure 10 This is a schematic diagram of the hardware interface of a timing controller provided in an embodiment of the present application;

[0067] Figure 11 This is a schematic diagram of a grouping of a driving circuit provided in an embodiment of the present application;

[0068] Figure 12 This is the third structural diagram of a display module provided in an embodiment of the present application.

[0069] Figure 13 This is a schematic diagram of a clock rising edge of a differential signal in the related art;

[0070] Figure 14 This is a schematic diagram of the position of a rising edge of a signal provided in an embodiment of the present application;

[0071] Figure 15 This is a schematic diagram of synchronous transmission of a driving circuit group provided by an embodiment of the present application;

[0072] Figure 16 This is a schematic diagram of a driving circuit component provided by an embodiment of the present application;

[0073] Figure 17 This is one of the schematic diagrams of a signal rising edge and a signal slope provided in an embodiment of the present application;

[0074] Figure 18 This is a second schematic diagram of a signal rising edge and a signal slope provided in an embodiment of the present application;

[0075] Figure 19 Schematic diagram of the delay duration of the three channel delay modes provided in the embodiments of the present application;

[0076] Figure 20 This is a schematic diagram of time-sharing transmission combining multiple improvement measures provided by an embodiment of the present application;

[0077] Figure 21 This is a schematic diagram of EMI test results in related technology;

[0078] Figure 22 This is a schematic diagram of EMI test results after EMI improvement measures are taken in the related art;

[0079] Figure 23 This is a schematic diagram of EMI test results provided by an embodiment of the present application;

[0080] Figure 24 This is a flowchart of the steps of a display driving process provided by an embodiment of the present application;

[0081] Figure 25 This is a schematic diagram of time-sharing transmission of a timing control circuit provided by an embodiment of the present application;

[0082] Figure 26 This is a schematic diagram of clock skew between adjacent differential pairs provided in an embodiment of the present application;

[0083] Figure 27 1 is a schematic diagram of a delay time difference of a first clock signal provided in an embodiment of the present application;

[0084] Figure 28 This is a flow chart of a display driver provided in an embodiment of the present application. DETAILED DESCRIPTION

[0085] The following will be combined with the accompanying drawings in some embodiments to clearly and completely describe the technical solutions in some embodiments. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0086] Currently, for the EMI noise at the back end of TCON, a spread-spectrum clock generator (SSCG) can be set in TCON to disperse the peak energy of the clock signal into multiple frequency bands in the spread spectrum area. For example, Figure 1 The curves in the figure show the energy reduction effect corresponding to spread amplitudes of 0% to 4%, respectively. This reduces the peak energy of the clock signal, thereby suppressing EMI. However, due to the specifications of the TCON and Source Driver IC, the improvement can only be achieved within the allowable range. Sometimes, even the optimal spread spectrum effect cannot fully meet EMI test requirements.

[0087] In related technologies, the overall energy of the output signal can be reduced by adjusting the peak-to-valley value of the TCON output signal, thereby reducing EMI noise. However, adjusting the peak-to-valley value of the TCON signal is subject to the quality requirements of the signal quality, such as Figure 2 As shown in the figure, the eye diagram of the signal after peak-valley value adjustment cannot be compressed to the mask, and the signal quality must be stable. Therefore, this improvement method has limited effect on improving EMI.

[0088] In addition, random display data streams can be transmitted through the perturbation and descrambling functions to reduce the energy spectrum density of the data stream and thus reduce EMI noise. For example, a perturbation function circuit can be set in the Source Driver IC, such as Figure 3 As shown, it includes a 24-bit dither module, a 24-bit D-type flip-flop (DFF), and a logic circuit. This dither circuit outputs 24-bit RGB image data or dithered data under the control of the RST, PCLK, D_SCR_EN, and D_SCR_RST signals sent by the TCON. However, this method involves scrambling and descrambling, and there is a risk of data errors due to decoding errors, resulting in abnormal display panel images.

[0089] Figure 4 The structural diagram of a display module provided by an embodiment of the present application is exemplarily shown as follows: Figure 4 As shown, the display module includes: a timing control circuit, multiple driving circuits and a display panel connected in sequence;

[0090] The input terminal of the driving circuit is electrically connected to the output terminal of the timing control circuit, and the timing control circuit is configured to identify the first signal sent to the driving circuit and control the timing of the first signal;

[0091] The output terminal of the driving circuit is electrically connected to the input terminal of the display panel, and the driving circuit is configured to receive and process the first signal to form a second signal to be input to the display panel;

[0092] The plurality of driving circuits are arranged in an array along a first direction, and the plurality of driving circuits are symmetrically distributed about a central axis of the display panel, the central axis extends along a second direction, and the first direction and the second direction are orthogonal;

[0093] The plurality of driving circuits include a first circuit group and a second circuit group, the first circuit group includes a first driving circuit and a second driving circuit, and the second circuit group is arranged between the first driving circuit and the second driving circuit;

[0094] The second signal includes a first group of signals and a second group of signals, the first group of signals is the second signal sent to the display panel by the first circuit group, and the second group of signals is the second signal sent to the display panel by the second circuit group, wherein the moment when the display panel receives the first group of signals is the first moment, and the moment when the display panel receives the second group of signals is the second moment, and the first moment is greater than the second moment.

[0095] In some embodiments, an independent signal line may be provided between the timing control circuit and each driver circuit, i.e., the timing control circuit is electrically connected to each of the multiple driver circuits. Specifically, the timing control circuit may include multiple output terminals, each of which is electrically connected to an input terminal of a driver circuit via a signal line. Point-to-point signaling may be used to transmit data between the timing control circuit and the driver circuit, for example, image data, control instructions, etc. The display module may be a liquid crystal display module that uses point-to-point signaling for data transmission, and the data transmission process between the timing control circuit and the driver circuit complies with the point-to-point signal interface transmission protocol for liquid crystal displays.

[0096] For example, Figure 5 is a structural diagram of another display module provided in an embodiment of the present application, such as Figure 5 As shown, the timing control circuit is a timing controller (TCON), which is installed on the TCON board. The TCON board includes external interfaces 1 to 51, through which image data can be received. The TCON board is connected to 12 driver circuits via two printed circuit boards (XPCBs) for data transmission. The driver circuit is a source driver IC, which is installed on a chip on film (COF) package. Figure 5 The TCON is connected to each Source Driver IC via independent signal lines, enabling point-to-point data transmission. Each Source Driver IC is then connected to the display panel, sending source signals to the panel to drive the display to display the image.

[0097] It should be noted that if Figure 6 As shown, the data format of a complete point-to-point signal may include a regular training clock signal (Training CLK), a configuration signal (Configuration) for configuring parameters of a driving circuit, and a normal image signal such as RGB DATA.

[0098] In the embodiment of the present application, the first signal can be Figure 6In the data format of the point-to-point signal shown, the first signal may include a training clock signal, a configuration signal, and an image signal. The timing control circuit may receive the image data and generate first signals corresponding to each of the multiple driving circuits based on the image data. The timing control circuit then controls the timing of the multiple first signals and transmits the first signals to the driving circuits, allowing the driving circuits to obtain second signals based on the first signals.

[0099] For example, the first signal sent by the timing control circuit to the driver circuit may include a first signal and image data. The first signal includes an embedded clock signal and control instructions, and the remainder is the image data. The driver circuit may extract the image data from the first signal as a source signal and then, in response to the control instructions of the timing control circuit, send a second signal to the display panel to drive the display panel to display an image.

[0100] In order to solve the EMI problem caused by the TCON sending signals to multiple Source Driver ICs synchronously and the multiple Source Driver ICs sending signals to the display panel synchronously in the related art, the embodiments of the present application use a timing control circuit to send signals to multiple driver circuits in a time-sharing manner, and / or the timing control circuit controls the signal delay of at least one driver circuit so that the driver circuit sends signals to the display panel in a time-sharing manner, which can reduce the instantaneous energy of the signal transmission process and achieve the effect of reducing EMI noise.

[0101] In some embodiments, multiple drive circuits in a display module are arranged in an array along a first direction, which may be a direction parallel to an edge of the display panel. The central axis of the display panel extends along a second direction, and the first direction is orthogonal to the second direction, so the first direction is perpendicular to the central axis of the display panel. Furthermore, the multiple drive circuits are symmetrically distributed about the central axis. If there is an odd number of drive circuits, the centermost drive circuit is located on the central axis. If there is an even number of drive circuits, the number of drive circuits located on either side of the central axis is equal.

[0102] In some embodiments, the driving circuits can be grouped to obtain multiple driving circuit groups, and the multiple driving circuit groups include at least a first circuit group and a second circuit group. For example, when the driving circuit group only includes a first circuit group and a second circuit group, the first circuit group includes two driving circuits, namely a first driving circuit and a second driving circuit, and the second circuit group includes other driving circuits. The second circuit group is set between the first driving circuit and the second driving circuit, and the first driving circuit and the second driving circuit are driving circuits on both sides. For example, referring to Figure 5 The first circuit group may include two Source Driver ICs, XD1 and XD12, and the second circuit group may include the other 10 Source Driver ICs.

[0103] In some embodiments, the first circuit group and the second circuit group can be controlled to send the second signal to the display panel at the same time, thereby reducing the instantaneous energy of the signal transmission process to improve the EMI noise of the display module. Specifically, the second signal sent by the first circuit group to the display panel is referred to as the first group of signals, and the second signal sent by the second circuit group to the display panel is referred to as the second group of signals. Among them, the display panel serves as the receiving end of the signal, and the first moment of receiving the first group of signals is greater than the second moment of receiving the second group of signals, that is, the display panel receives the first group of signals later than the second group of signals. Therefore, the number of signals received at the same time can be reduced, thereby reducing the instantaneous energy.

[0104] Specifically, the first sending process refers to the process in which the timing control circuit sends multiple first signals to the driving circuit, and the second sending process refers to the process in which the driving circuit sends the second signal to the display panel. At least one of the first sending process and the second sending process adopts a time-sharing sending method, and the first circuit group and the second circuit group can be time-sharing, which can reduce instantaneous energy and thus reduce the EMI of the display module. In the first sending process, after the timing control circuit sends the first signal to the driving circuit in the second circuit group, it can delay for a period of time before sending the first signal to the first driving circuit and the second driving circuit in the first circuit group. Alternatively, in the second sending process, after the driving circuit in the second circuit group sends the second signal to the display panel, the first driving circuit and the second driving circuit in the first circuit group can send the second signal to the display panel.

[0105] In some embodiments, the data transmission mode includes a synchronous transmission mode and a time-sharing transmission mode to reduce the EMI of the display module. When the first transmission process corresponding to the timing control circuit adopts the time-sharing transmission mode, the second transmission process corresponding to the driving circuit can adopt the synchronous transmission mode or the time-sharing transmission mode. When the first transmission process adopts the synchronous transmission mode, at least one driving circuit in the second transmission process needs to adopt the time-sharing transmission mode. The number of driving circuits adopting the time-sharing transmission mode can be determined according to the EMI test requirements, and the embodiments of the present application do not limit this.

[0106] In some embodiments, the multiple first signals sent by the timing control circuit can be delayed separately so that the clocks of the multiple first signals are not synchronized, thereby enabling the timing control circuit to send the first signal to the multiple driving circuits in a time-sharing manner, staggering the energy peaks, reducing instantaneous energy, and thus reducing EMI noise.

[0107] In some embodiments, the time-sharing transmission method used in the second transmission process may include separately delaying the second signals sent by different driving circuits, and separately delaying the source signals sent by different channels in the driving circuit. This is merely an example and is not limited in the present embodiment.

[0108] In some embodiments, the second signals transmitted by different driving circuits are delayed separately. This can be achieved by delaying the data transmission time of the second signals of the driving circuits, so that the second signals of the multiple driving circuits are transmitted in a time-sharing manner, thereby reducing instantaneous energy. Alternatively, the second signals transmitted by different driving circuits can be delayed separately by adjusting the corresponding slew rate of the driving circuits. The slew rate is expressed as the slope of the output signal. This allows the second signals of the multiple driving circuits to have different signal slopes. This disperses the energy spectrum of the second transmission process in the frequency domain, thereby also reducing instantaneous energy.

[0109] In some embodiments, delaying the source signals transmitted by different channels in a driver circuit can be achieved by delaying the signal output times of multiple channels of the driver circuit. This allows the source signals of multiple channels to be output in a time-sharing manner, thereby reducing the instantaneous energy of a single driver circuit during the second transmission process. During the second transmission process, the number of driver circuits using a time-sharing transmission method can be determined in practice based on EMI testing requirements and is not limited in this embodiment of the present application.

[0110] A display module provided by an embodiment of the present application includes: a timing control circuit, multiple driving circuits, and a display panel connected in sequence; an input end of the driving circuit is electrically connected to an output end of the timing control circuit; the timing control circuit is configured to identify a first signal sent to the driving circuit and control the timing of the first signal; the output end of the driving circuit is electrically connected to an input end of the display panel; the driving circuit is configured to receive and process the first signal to form a second signal to be input to the display panel; the multiple driving circuits are arranged in an array along a first direction and symmetrically distributed about a central axis of the display panel; the central axis extends along a second direction; the first direction and the second direction are orthogonal; the multiple driving circuits include a first circuit group and a second circuit group; the first circuit group includes a first driving circuit and a second driving circuit; the second circuit group is arranged between the first driving circuit and the second driving circuit; the second signal includes a first group of signals and a second group of signals, the first group of signals being the second signal sent to the display panel by the first circuit group, and the second group of signals being the second signal sent to the display panel by the second circuit group; wherein the moment when the display panel receives the first group of signals is a first moment, and the moment when the display panel receives the second group of signals is a second moment, and the first moment is greater than the second moment. In this way, the display panel receives the first group of signals and the second group of signals at different times, so the energy is dispersed during the transmission of the second signal, reducing the instantaneous energy and thus reducing the EMI noise of the display module.

[0111] Figure 7This example illustrates an abnormal charging time for the display panel due to an excessively long delay in the second signal sent by the driver circuit. This can lead to image segmentation in display areas driven by different driver circuits, impacting the display quality of the display panel. Therefore, reducing EMI noise in the display module requires ensuring normal display of the display panel. To properly display a frame of image, the display panel must have sufficient charging time, which limits the maximum delay of the display module, referred to in this embodiment as the panel delay.

[0112] In the embodiment of the present application, for different display modules, due to differences in wiring methods and display panel structures, the panel delay time may be different and needs to be determined in combination with the actual parameters of the display module. The corresponding charging time of the display panel can be calculated according to the following formula (1):

[0113] T=t1-t2-t3-t4 (1)

[0114] The meaning of each parameter in formula (1) is as follows Figure 8 As shown in Figure 1, T represents the charging time, t1 is the charging time of a pixel row in the display panel, t2 is the prevention of wrong charging (GOE) time, t3 is the chamfer width, and t4 / t5 are the rise time and fall time of the source signal, respectively. t4 in formula (1) can be replaced by t5. The purpose of GOE is to prevent wrong charging, because the previous pixel row in the display panel cannot be turned off instantly and requires a fall process. The next pixel row also requires a process to turn on. If the opening speed of the next pixel row exceeds the closing speed of the previous pixel row, it is likely to cause malfunction and the signal of the next pixel row will be charged into the previous pixel row.

[0115] For Figure 5 The display module shown in the formula (1) has the following parameters as shown in Table 1. The following parameters are calculated based on the formula (1): Figure 5 The charging time of the display module shown is 1.85 microseconds (us).

[0116] Table 1 shows the actual parameters of the module

[0117] parameter Value (unit: us) t1 One line of time 7.4us t2 GOE 4.2us t3 Chamfer width 0us t4 Rise time 1.35us t5 Fall time 1.35us

[0118] Define the delayed charging time as Td, and the panel delay as ΔT, then Td = T - ΔT. Therefore, the source charging circuit with the longest delay has the shortest charging time. To ensure that the display area corresponding to the driver circuit displays normally, the actual charging time must be no less than the charging time Td.

[0119] Table 2 exemplifies the theoretical and actual charging times for three display modules. As shown in Table 2, these three display modules require an actual charging time of at least 1.6µs for normal display. For the second display module, the theoretical charging time T is 1.85µs, and the actual charging time Td is 1.6µs, resulting in a panel delay ΔT of 0.25µs.

[0120] In some embodiments, the register internal unit is usually UI, 1UI represents the width of one bit, UI is the reciprocal of the baud rate, i.e. Data Rate means baud rate, which is the data transmission rate. Figure 10 The timing controller (TCON) shown communicates with the Source Driver IC via the USIT interface, and the data transmission rate (USIT DataRate) can be calculated by referring to the following formula (2).

[0121]

[0122] Among them, H-total is the total horizontal duration of the signal, V-total is the total vertical duration of the signal, Frame is the refresh rate, Color Depth is the color depth, 3RGB is 3 RGB sub-pixels, 10 / 9 means that USIT uses 10B / 9B encoding, DriverNumber is the number of Source Driver ICs, and Input port is the number of interfaces (ports) input by the Source Driver IC. Figure 5 For example, the display module shown in Figure 1 has a data rate of 1.3G, meaning 1.3G of data bits are transmitted per second. Converting the panel delay to UI units yields the panel delay ΔUI as shown in the following formula (3). Based on a ΔT of 0.25us and a data rate of 1.3G, the resulting ΔUI is 325UI.

[0123]

[0124] In some embodiments, the TCON can communicate with the Source Driver IC via a clock embedded differential signaling (CEDS) interface or a high-definition display interface (CHPI). The data transmission rates corresponding to the CEDS interface and the CHPI interface can be calculated using formulas (4) and (5).

[0125]

[0126] In some embodiments, the second signals sent by different driver circuits are delayed separately. This can be achieved by grouping multiple driver circuits into multiple driver circuit groups. The second signals corresponding to the multiple driver circuit groups are then delayed separately, allowing the multiple driver circuit groups to send the second signals to the display panel in a time-sharing manner. The driver circuits in the driver circuit groups can transmit the second signals synchronously, i.e., they can send the second signals to the display panel synchronously.

[0127] In some embodiments, multiple driving circuit groups may follow the following grouping principles. First, if the number of driving circuit groups is an even number, the multiple driving circuit groups should be symmetrically distributed about the center of the display panel. If the number of driving circuit groups is an odd number, the other driving circuit groups in the multiple driving circuit groups are symmetrically distributed about the middle driving circuit group, and the middle driving circuit group is located at the center of the display panel. Second, adjacent driving circuits may belong to the same driving circuit group or to different driving circuit groups. When adjacent driving circuits belong to different driving circuit groups, the delay time difference between adjacent driving circuits should be as small as possible. Third, the total delay time corresponding to the second sending process is less than the panel delay time, and the total delay time corresponding to the second sending process plus the total delay time corresponding to the first sending process should be less than the panel delay time to ensure that the display panel can display a frame of image normally.

[0128] Among them, for the second grouping principle, although the greater the signal delay, the smaller the instantaneous energy of the signal, and the overall energy is dispersed, a large delay of the source signal will affect the charging time of the display panel. The delay time difference between adjacent driving circuits should be as small as possible to avoid the display panel boundary problem caused by the large delay time difference between adjacent driving circuits.

[0129] For example, for Figure 5 The 12 driving circuits in the display module shown can be divided into two groups of 6+6, or four groups of 3+3+3+3, etc. The driving circuit groups can be evenly grouped or unevenly grouped, which is not limited in the present embodiment. Figure 11 The grouping method shown divides XD1-XD12 into four groups, a, b, c, and d. The data transmission times corresponding to groups a, b, c, and d are t4, t3, t2, and t1, respectively. Group d is the driving circuit group with the longest delay, and its corresponding data transmission time t1 is the latest. Group a is the driving circuit group with the shortest delay, and its corresponding data transmission time t4 is the latest. The delay order of the four driving circuit groups a, b, c, and d is from smallest to largest. The delay time difference between two adjacent driving circuit groups in the delay order is Δt, where Δt represents the second offset. Δt can be calculated using the following formula (6).

[0130]

[0131] The results after grouping XD1 to XD12 are as follows Figure 12 shown. Figure 12 In the example, adjacent XD6 and XD7 both belong to group c, and adjacent XD7 and XD8 belong to group c and group d respectively, and group c and group d are adjacent in the delay sequence. Figure 5 The display module shown is routed through the XPCB. Due to the XPCB's own routing, there is also a certain delay. The longer the routing, the greater the delay. Compared with other COFs, XD1 and XD12 at the edge of the screen have the longest delay in receiving the TCON signal. If XD1 and XD12 are divided into a drive circuit group with lower delay, the delay caused by the routing problem and the delay of the source signal may cancel each other out, and the purpose of time-sharing transmission may not be achieved. Figure 12 As shown, XD1 and XD12 can be divided into group d with the largest delay, so that the Source Driver ICs corresponding to XD1 and XD12 send the second signal to the display panel in a time-sharing manner.

[0132] In some embodiments, such as Figure 13 As shown in , the sending time of the first rising edge of the signal corresponds to the sending time of the signal, so delaying the sending time of the first rising edge of the signal can delay the sending time of the signal. Figure 14 As shown, the rising edges of the four signals are staggered, indicating that the sending times of the four signals are different. Accordingly, the times when the signal receiving end receives the rising edges of the four signals are also different.

[0133] In some embodiments, multiple driver circuit groups may correspond to different delay durations. The delay duration may be set to N bits wide, where N is a positive integer. The value of N may vary for different driver circuit groups. For driver circuits within the same driver circuit group, the first configuration parameter embedded in the first signal sent by the timing control circuit may include the same delay duration, thereby storing the same delay duration in each driver circuit within the driver circuit group. For driver circuit groups with adjacent delay sequences, the first configuration parameter embedded in the first signal sent by the timing control circuit includes different delay durations, and the delay time difference between the rising edges of the second signal is the second offset.

[0134] In some embodiments, during the second transmission process, the driver circuit transmits the second signal to the display panel after a delay of N bit widths, such that the delay time difference between the second signal and the second signal corresponding to an adjacent driver circuit group is a second offset. On the signal waveform of the second transmission process, the delay time difference between rising edges of source signals corresponding to channels with the same sequence number in adjacent driver circuit groups is represented by the second offset.

[0135] Optionally, the first driving circuit among the multiple driving circuits that sends the second signal to the display panel is a target driving circuit, and the target driving circuit belongs to the second circuit group;

[0136] The time when the display panel receives the second signal sent by the target driving circuit is the target time, and the time difference between the first time and the target time is greater than or equal to 15 bit widths and less than 325 bit widths;

[0137] The time difference between the second moment and the target moment is greater than or equal to 0 and less than a 15-bit width.

[0138] In some embodiments, the first driver circuit in the second circuit group that sends the second signal to the display panel can be used as the target driver circuit. With the target driver circuit as a reference, the first time at which the display panel receives the second signal sent by the first and second driver circuits in the first circuit group is later than the target time corresponding to the target driver circuit, that is, the first time is greater than the target time. The second time includes the target time.

[0139] In some embodiments, a register for storing a delay duration, namely a first register, may be provided in the driver circuit. The first configuration parameter embedded in the first signal sent by the timing control circuit to the driver circuit may include the value of the first register, i.e., the first configuration parameter includes the N-bit width corresponding to the delay duration of the rising edge of the second signal. After receiving the first configuration parameter, the driver circuit may write the N-bit width into the first register, so that the first register stores the N-bit width.

[0140] Table 2 First register configuration table

[0141] a b c d CLK1TL0 1 0 1 0 CLK1TL1 0 1 1 0 CLK1TL2 1 0 1 1 CLK1TL3 0 1 1 0 CLK1TL4 0 0 0 1 CLK1TL5 0 0 0 0

[0142] As shown in Table 2, the first register may include CLK1TL0-5 registers, which can store 6-bit binary values, and the 6-bit binary value represents N bit width. Figure 12 For the grouping results of XD1 to XD12, the N-bit width corresponding to group a is binary 000101, the N-bit width corresponding to group b is binary 001010, the N-bit width corresponding to group c is binary 001111, and the N-bit width corresponding to group d is binary 010100. Converting the N-bit widths corresponding to groups a, b, c, and d to decimal is 5, 10, 15, and 20, respectively. Referring to formula (6), the second offset Δt = 5UI.

[0143] for Figure 12 The grouping result of XD1 to XD12 is as follows: Figure 15As shown, the waveforms after delaying the rising edges of the signals of the four driving circuit groups a, b, c and d are as follows: Figure 16 As shown. Before the rising edge of the signal is delayed, the first rising edge position of the output signals of the 12 drive circuits XD1 to XD12 is the same, indicating that the source signals of the 12 drive circuits are sent synchronously. After the rising edge of the signal is delayed, see Figure 16 The first rising edge positions of the output signals of the 12 drive circuits XD1 to XD12 are staggered, indicating that the source signals of the 12 drive circuits are sent in a time-sharing manner.

[0144] In some embodiments, the target driving circuit is the first to send the second signal to the display panel. For example, the target driving circuit may be Figure 12 The driving circuit in the driving circuit group a shown in FIG. Figure 11 As shown, the target time may be the target time t4 corresponding to the driving circuit group a. The first driving circuit and the second driving circuit in the first circuit group may be, for example, Figure 12 The driving circuits in the driving circuit group d shown in FIG. 1 are respectively located on both sides of the display panel. The second circuit group may include three driving circuit groups a, b and c. Figure 12 As shown, the second circuit group is located between the first driving circuit and the second driving circuit.

[0145] like Figure 11 As shown, the first moment corresponding to the first circuit group can be t1 corresponding to the driving circuit group d, and the second moment corresponding to the second circuit group can include t2, t3 and t4. For example, if △t=5UI, the time difference between the second moment and the target moment can include the time difference between t2 and t3 and t4, as well as the time difference between t4 and itself. The minimum time difference is zero and the maximum does not exceed 3 times of △t. Therefore, the time difference between the second moment and the target moment is greater than or equal to 0 and has a bit width of 15. In addition, the time difference between the first moment and the target moment can be the time difference between t1 and t4. The time difference is greater than 3 times of △t, that is, greater than 15UI. And in order to ensure that the display panel displays the picture normally, the time difference between the first moment and the target moment should be less than the panel delay time △T=0.25us, which is converted to a bit width of 325UI.

[0146] Optionally, there is a first time difference between the first moment and the second moment;

[0147] The first time difference is greater than or equal to 5 bits in width, and the first time difference is less than or equal to 15 bits in width.

[0148] In some embodiments, different driving circuits in the second circuit group may send the second signal to the display panel synchronously or in a time-sharing manner, and the present application does not limit this. If the second signal is sent synchronously, the second time corresponding to the driving circuits in the second circuit group is the same; otherwise, the second time corresponding to the driving circuit includes a certain time within a period of time. For example, Figure 11 As shown, the first circuit group includes the driving circuit group d, then the first moment is t1, the second circuit group includes the driving circuit groups a, b and c, then the second moment can be t1, t2 or t3, since the time difference between adjacent driving circuit groups is △t=5UI, the time difference between the first moment and the second moment is at least 1 △t and at most 3 △t, so the first time difference can be greater than or equal to 5 bit widths, and the first time difference can be less than or equal to 15 bit widths.

[0149] Optionally, the first group of signals has a first slew rate, and the second group of signals has a second slew rate;

[0150] The first slew rate is less than the second slew rate.

[0151] In some embodiments, the slew rate of different drive circuits can be adjusted, i.e., the signal slope of the second signal corresponding to different drive circuits is set to different slope values ​​to disperse the energy spectrum in the frequency domain, thereby reducing the instantaneous energy of the second transmission process and reducing the EMI noise caused by the second transmission process. The slew rate can be expressed as the slope of the output signal of the operational amplifier in the drive circuit.

[0152] In some embodiments, a greater signal slew rate shortens the time required for the signal to rise to a valid level, which is manifested on the signal waveform as a greater slope of the signal's rising edge and a shorter duration of the signal's rising edge. For example, a greater slope of a signal's rising edge shortens the time required for the signal to rise from a low level to a high level. Conversely, a smaller signal slew rate lengthens the time required for the signal to rise to a valid level, which is manifested on the signal waveform as a smaller slope of the signal's rising edge and a shorter duration of the signal's rising edge.

[0153] In some embodiments, the signal slew rate of the first group of signals corresponding to the first circuit group can be less than the signal slew rate of the second group of signals corresponding to the second group of signals, that is, the first slew rate is less than the second slew rate. In this way, even if the second signals of multiple driving circuits are transmitted synchronously, because the signal slew rates corresponding to the first circuit group and the second circuit group are different, the energy spectrum in the frequency domain during the second transmission process is dispersed, which can reduce the instantaneous energy of the second transmission process. At the display panel, because the first slew rate is less than the second slew rate, the second group of signals received by the display panel rises to the valid level first, while the first group of signals rises to the valid level later, that is, the first moment corresponding to the display panel receiving the first group of signals is greater than the second moment corresponding to the display panel receiving the second group of signals.

[0154] In some embodiments, the signal slope can be changed by changing the rising edge duration and / or falling edge duration of the signal. Figure 17 As shown, Figure 17 The square wave signal in (a) has an amplitude of 10 volts (V), a frequency of 400 kilohertz (kHZ), a duty cycle of 50%, and a rise time (tr) and fall time (tf) of 10 nanoseconds (ns). The amplitude of the square wave signal for the nth harmonic and the amplitude in the frequency domain are as follows: Figure 17 (b) and Figure 17 (c) As shown. Figure 18 As shown in Figure 2, if the rise time (tr) and fall time (tf) are set to 100ns, the following is obtained: Figure 18 The signal shown in (a) shows a change in the signal slope. Figure 18 (b) and Figure 18 (c), the energy spectrum in the frequency domain is dispersed.

[0155] Optionally, a rising edge duration of the first group of signals changing from a first level to a second level is a first duration, and a rising edge duration of the second group of signals changing from a first level to a second level is a second duration, wherein the second level is greater than the first level;

[0156] The first duration is greater than the second duration.

[0157] In some embodiments, the second signals of multiple drive circuit groups may correspond to different signal slopes, and if the second signal is high-level valid, the signal slope may be changed by changing the rising edge duration of the signal, and the rising edge duration of the second signal may be set to M bit widths, where M is a positive integer, and the value of M corresponding to different drive circuit groups is different. For drive circuits belonging to the same drive circuit group, the first configuration parameters embedded in the first signal sent by the timing control circuit may include the same rising edge duration, thereby storing the same rising edge duration in the drive circuit group. For drive circuit groups with adjacent delay sequences, the first configuration parameters embedded in the first signal sent by the timing control circuit include different rising edge durations, and the difference in rising edge duration between the target second signals is the second offset.

[0158] In some embodiments, the rising edge duration of a second signal transmitted by the driving circuit to the display panel is equal to the M-bit width stored in the driving circuit, such that the difference in rising edge duration between the second signal and the second signal corresponding to an adjacent driving circuit group is equal to a second offset. In the signal waveform of the second transmission process, the difference in rising edge duration between the second signals corresponding to channels with the same sequence number in adjacent driving circuit groups is represented by the second offset.

[0159] In some embodiments, because the second level is greater than the first level, the change of the second signal from the first level to the second level may be a change in the level of the second signal from a low level to a high level, generating a rising edge on the waveform of the second signal. The duration of the rising edge corresponding to the first group of signals is a first duration, and the duration of the rising edge corresponding to the second group of signals is a second duration. The first duration may be greater than the second duration, such that the signal slope of the first group of signals is less than the signal slope of the second group of signals.

[0160] Optionally, the difference between the first duration and the second duration is greater than zero and less than 4 bits in width.

[0161] In some embodiments, a register for storing the duration of a rising edge of a signal, namely a second register, may be provided in the driver circuit. The first configuration parameter embedded in the first signal sent by the timing control circuit to the driver circuit may include the value of the second register, i.e., the first configuration parameter includes the M bit width corresponding to the duration of the rising edge of the second signal. After receiving the first configuration parameter, the driver circuit may write the M bit width into the second register, so that the second register stores the M bit width.

[0162] Table 3 Second register configuration table

[0163]

[0164]

[0165] As shown in Table 3, the second register may include a slew<0,1,2> register, which can store a 3-bit binary value, where the 3-bit binary value represents a width of M bits. Different register values ​​correspond to different rising edge durations. The shorter the rising edge duration, the greater the signal slope. As shown in Table 3, the slew<0,1,2> register can set eight signal rising edge durations. For example, when slew<0,1,2> is set to 000, the rising edge duration increases by 1UI. When slew<0,1,2> is set to 001, the rising edge duration increases by 2UI, and so on. The second offset is 1UI.

[0166] For Figure 12 The grouping results of XD1 to XD12 are shown in Table 4. The rising edge duration of the signal corresponding to group a is the shortest, so the signal slope of group a is the largest, and the signal slopes of groups b, c, and d decrease in turn.

[0167] Table 4 Second register group configuration

[0168] a b c d SLEW<2> 0 1 0 1 SLEW<0> 0 0 0 0 SLEW<1> 0 0 1 1

[0169] In some embodiments, such as Figure 11 As shown, the first group of signals may include the second signal sent by driving circuit group d. In this case, the first duration corresponding to the first group of signals can be increased by a maximum of 2UI. The second group of signals may be the second signal sent by driving circuit group a, b, or c. In this case, the second duration corresponding to the second group of signals can be increased by a minimum of 1UI. Therefore, the difference between the first and second durations should be a minimum of 1UI and a maximum of 3UI, i.e., the difference should be greater than zero and less than 4UI.

[0170] Optionally, there is a first duration between the rising edge and the falling edge of the first group of signals, and there is a second duration between the rising edge and the falling edge of the second group of signals, wherein,

[0171] The first duration is less than the second duration.

[0172] In some embodiments, the first duration may represent the duration of the effective level of the first group of signals, that is, there is a first duration between the rising edge and the falling edge of the first group of signals. The second duration may represent the duration of the effective level of the second group of signals, that is, there is a second duration between the rising edge and the falling edge of the second group of signals. In this embodiment, the period of the second signal is determined, and the difference obtained by subtracting the first duration from the half-period duration of the second signal represents the total duration of the rising edge and the falling edge of the second signal. The smaller the first duration, the larger the total duration of the rising edge and the falling edge, and the smaller the slope of the signal. The larger the second duration, the smaller the total duration of the rising edge and the falling edge, and the greater the slope of the signal.

[0173] In some embodiments, the rising and falling edges of the second signal can be symmetrical. Because the first duration is shorter than the second duration, the duration of the rising edge corresponding to the first group of signals is longer than the duration of the rising edge corresponding to the second group of signals. Thus, by defining the magnitude relationship between the first and second durations, the signal slopes corresponding to the first and second groups of signals can be differentiated, resulting in a time difference between the moments when the display panel receives the first and second groups of signals. Consequently, the instantaneous energy of the signal can be reduced, thereby reducing EMI noise from the display module.

[0174] Optionally, the second circuit group includes a third driving circuit and a fourth driving circuit, and the plurality of driving circuit groups further includes a third circuit group;

[0175] A portion of the third circuit group is located between the first drive circuit and the third drive circuit, and another portion of the third circuit group is located between the second drive circuit and the fourth drive circuit;

[0176] The second signal also includes a third group of signals. The third group of signals is the second signal sent to the display panel by the third circuit group. The time when the display panel receives the third group of signals is the third time, which is less than the second time.

[0177] In some embodiments, the second circuit group may be a driving circuit group that is adjacent to the first circuit group in a delayed order, for example Figure 11 The first circuit group may be driver circuit group d, and the second circuit group may be driver circuit group c. The driver circuits in the second circuit group should be arranged adjacent to the first circuit group when arranged along the first direction. The delay time difference between two adjacent driver circuit groups in the delay sequence is Δt. By setting the value of Δt sufficiently small, the problem of screen splitting between the display areas of the display panels driven by the first and second circuit groups can be avoided.

[0178] In some embodiments, the driving circuit other than the first circuit group and the second circuit group can be divided into a third circuit group. The second signal sent to the display panel by the third circuit group can be called a third group signal. The third moment when the display panel receives the third group signal should be less than the second moment when it receives the second group signal, that is, the third moment is less than the second moment, and the second moment is less than the first moment.

[0179] For example, refer to Figure 12 , the first circuit group may include two Source Driver ICs, XD1 and XD12, the second circuit group may include four Source Driver ICs, XD2, XD11, XD6, and XD7, and the remaining Source Driver ICs may belong to the third circuit group. Figure 12 As shown, XD2 is adjacent to XD1, and XD11 is adjacent to XD12.

[0180] In some embodiments, the third circuit group and the second circuit group are also adjacent in the delay order. The driving circuit in the third circuit group can be divided into two parts, and the driving circuits of the two parts are separately arranged between the driving circuits in the second circuit group. This can also avoid the problem of screen segmentation between the display areas driven by the second circuit group and the third circuit group.

[0181] Specifically, the second circuit group includes a third driving circuit and a fourth driving circuit. The third driving circuit and the fourth driving circuit are located adjacent to each other in the plurality of driving circuits, and the third driving circuit and the fourth driving circuit are not directly adjacent to the driving circuits in the first circuit group. For example, the third driving circuit and the fourth driving circuit can be respectively as follows: Figure 12 The two Source Driver ICs shown are XD6 and XD7.

[0182] Specifically, a portion of the third circuit group is located between the first drive circuit and the third drive circuit, and a portion of the third circuit group is located between the drive circuit of the second circuit group adjacent to the first drive circuit and the third drive circuit. Another portion of the third circuit group is located between the second drive circuit and the fourth drive circuit, and another portion of the third circuit group is located between the drive circuit of the second circuit group adjacent to the second drive circuit and the fourth drive circuit. For example, Figure 12 As shown, a portion of the third circuit group may include a driver IC between the two Source Driver ICs XD2 and XD6, and another portion of the third circuit group may include a driver IC between the two Source Driver ICs XD7 and XD11. This is merely an example and is not limited in the present embodiment.

[0183] In some embodiments, the first, second, and third circuit groups can be controlled to simultaneously transmit the second signal to the display panel, thereby reducing the instantaneous energy during signal transmission and improving EMI noise in the display module. Specifically, the first moment is greater than the second moment, and the second moment is greater than the third moment. This reduces the number of signals received by the display panel at the same time, thereby reducing instantaneous energy.

[0184] Optionally, the third circuit group includes a fifth driving circuit and a sixth driving circuit, and the plurality of driving circuit groups further includes a fourth circuit group;

[0185] A portion of the fourth circuit group is located between the fifth drive circuit and the third drive circuit, and another portion of the third circuit group is located between the sixth drive circuit and the fourth drive circuit;

[0186] The second signal also includes a fourth group of signals. The fourth group of signals is the second signal sent to the display panel by the fourth circuit group. The moment when the display panel receives the fourth group of signals is a fourth moment, which is less than the third moment.

[0187] In some embodiments, the fourth circuit group may be a driving circuit group that is adjacent to the third circuit group in a delayed order, for example Figure 11 The third circuit group may be driver circuit group b, and the fourth circuit group may be driver circuit group a. The driver circuits in the fourth circuit group should be positioned adjacent to the third circuit group when arranged along the first direction. The delay time difference between two adjacent driver circuit groups in the delay sequence is Δt. By setting the value of Δt sufficiently small, the problem of screen splitting between the display areas of the display panels driven by the third and fourth circuit groups can be avoided.

[0188] In some embodiments, the driving circuits other than the first circuit group, the second circuit group, and the third circuit group can be divided into a fourth circuit group. The second signal sent to the display panel by the fourth circuit group can be called a fourth group signal. The fourth moment when the display panel receives the fourth group signal should be less than the third moment when the display panel receives the third group signal, that is, the fourth moment is less than the fourth moment, and the third moment is less than the second moment, and the second moment is less than the first moment.

[0189] For example, refer to Figure 12 The first circuit group may include two source driver ICs, XD1 and XD12; the second circuit group may include four source driver ICs, XD2, XD11, XD6, and XD7; the third circuit group may include four source driver ICs, XD3, XD5, XD8, and XD10. The remaining source driver ICs may belong to a fourth circuit group.

[0190] In some embodiments, the driving circuit in the fourth circuit group can be divided into two parts, and the driving circuits of the two parts can be separately arranged between the driving circuits in the third circuit group. This can also avoid the problem of screen segmentation between the display areas driven by the fourth circuit group and the third circuit group. Specifically, the third circuit group includes a fifth driving circuit and a sixth driving circuit. When arranged along the first direction, the fifth driving circuit is arranged at an adjacent position to the driving circuit in the second circuit group. Similarly, the sixth driving circuit is arranged at an adjacent position to the driving circuit in the second circuit group. For example, the fifth driving circuit and the sixth driving circuit can be respectively as follows: Figure 12 The two Source Driver ICs shown are XD3 and XD10.

[0191] Specifically, a portion of the fourth circuit group is located between the fifth drive circuit and the third drive circuit, and a portion of the fourth circuit group is located between the drive circuit of the third circuit group adjacent to the third drive circuit and the fifth drive circuit. Another portion of the fourth circuit group is located between the sixth drive circuit and the fourth drive circuit, and another portion of the fourth circuit group is located between the drive circuit of the third circuit group adjacent to the fourth drive circuit and the sixth drive circuit. For example, Figure 12 As shown, a portion of the fourth circuit group may include a Source Driver IC XD4, and another portion of the fourth circuit group may include a Source Driver IC XD9. This is merely an example and is not limited in the present embodiment.

[0192] In some embodiments, the first, second, third, and fourth circuit groups can be controlled to simultaneously transmit the second signal to the display panel, thereby reducing the instantaneous energy during signal transmission and improving EMI noise in the display module. Specifically, the first moment is greater than the second moment, the second moment is greater than the third moment, and the third moment is greater than the fourth moment. This reduces the number of signals received by the display panel at the same time and reduces instantaneous energy.

[0193] Optionally, the fourth circuit group includes a seventh drive circuit and an eighth drive circuit, and the third circuit group further includes a ninth drive circuit and a tenth drive circuit, wherein the ninth drive circuit is located between the third drive circuit and the seventh drive circuit, the tenth drive circuit is located between the fourth drive circuit and the eighth drive circuit, the ninth drive circuit and the fifth drive circuit are symmetrical with respect to the seventh drive circuit, and the sixth drive circuit and the tenth drive circuit are symmetrical with respect to the eighth drive circuit.

[0194] and / or,

[0195] The second circuit group also includes an eleventh drive circuit and a twelfth drive circuit, wherein the eleventh drive circuit is located between the first drive circuit and the seventh drive circuit, the twelfth drive circuit is located between the second drive circuit and the eighth drive circuit, the eleventh drive circuit and the third drive circuit are symmetrical with respect to the seventh drive circuit, and the twelfth drive circuit and the fourth drive circuit are symmetrical with respect to the eighth drive circuit.

[0196] In some embodiments, the seventh driver circuit in the fourth circuit group can be disposed adjacent to one or two driver circuits in the third circuit group. For example, the seventh driver circuit can be disposed between the fifth and ninth driver circuits in the third circuit group, with the fifth and ninth driver circuits being symmetrical with respect to the seventh driver circuit. The same applies to the eighth driver circuit. For example, the seventh driver circuit can be disposed between the sixth and tenth driver circuits in the third circuit group, with the sixth and tenth driver circuits being symmetrical with respect to the eighth driver circuit.

[0197] In some embodiments, the third driver circuit belongs to the second circuit group, the seventh driver circuit belongs to the fourth circuit group, and the ninth driver circuit belongs to the third circuit group. In terms of delay order, the third circuit group is located between the second circuit group and the fourth circuit group. Therefore, the ninth driver circuit is located between the third and seventh driver circuits. Similarly, the tenth driver circuit is located between the fourth and eighth driver circuits.

[0198] For example, refer to Figure 12 The first circuit group may include two Source Driver ICs, XD1 and XD12; the second circuit group may include four Source Driver ICs, XD2, XD11, XD6, and XD7; the third circuit group may include four Source Driver ICs, XD3, XD5, XD8, and XD10; and the fourth circuit group may include two Source Driver ICs, XD4 and XD9. The seventh driver circuit may be XD4, the eighth driver circuit may be XD9, the ninth driver circuit may be XD5, and the tenth driver circuit may be XD10. This is merely an example and is not a limitation of the present invention.

[0199] In some embodiments, the eleventh drive circuit is located between the first drive circuit and the seventh drive circuit, and the eleventh drive circuit is located between the first drive circuit and the fifth drive circuit, and the first drive circuit and the fifth drive circuit are symmetrical with respect to the eleventh drive circuit. The twelfth drive circuit is located between the second drive circuit and the eighth drive circuit, and the twelfth drive circuit is located between the second drive circuit and the sixth drive circuit, and the first drive circuit and the fifth drive circuit are symmetrical with respect to the twelfth drive circuit.

[0200] In some embodiments, the second circuit group includes a third driving circuit, a fourth driving circuit, an eleventh driving circuit, and a twelfth driving circuit, wherein driving circuits in the third circuit group and the fourth circuit group may be arranged between the third driving circuit and the eleventh driving circuit, and the same applies between the fourth driving circuit and the twelfth driving circuit.

[0201] Specifically, the fourth circuit group includes a seventh drive circuit and an eighth drive circuit. A drive circuit from the third circuit group can be disposed between the third drive circuit and the seventh drive circuit. A drive circuit from the third circuit group can also be disposed between the eleventh drive circuit and the seventh drive circuit. The same applies to the twelfth drive circuit. In order to avoid the problem of screen segmentation on the display panel, the eleventh drive circuit and the third drive circuit are symmetrical with respect to the seventh drive circuit, and the twelfth drive circuit and the fourth drive circuit are symmetrical with respect to the eighth drive circuit. For example, the eleventh drive circuit and the twelfth drive circuit can be respectively as follows: Figure 12The two Source Driver ICs shown are XD2 and XD11.

[0202] Optionally, the first time difference is the time difference between the first moment and the second moment, the second time difference is the time difference between the second moment and the third moment, and the third time difference is the time difference between the third moment and the fourth moment;

[0203] The first time difference, the second time difference and the third time difference are equal; and / or,

[0204] The third group of signals has a third slew rate, the fourth group of signals has a fourth slew rate, the first slew rate is smaller than the second slew rate, the second slew rate is smaller than the third slew rate, and the third slew rate is smaller than the fourth slew rate.

[0205] In some embodiments, the signal slew rate of the third group of signals corresponding to the third circuit group is a third slew rate, and the signal slew rate of the fourth group of signals corresponding to the fourth circuit group is a fourth slew rate. The first slew rate is less than the second slew rate, the second slew rate is less than the third slew rate, and the third slew rate is less than the fourth slew rate. Thus, even if the second signals of multiple driving circuits are transmitted synchronously, the different slew rates of the signals corresponding to the first, second, third, and fourth circuit groups disperse the frequency domain energy spectrum during the second transmission process, thereby reducing the instantaneous energy of the second transmission process. At the display panel, because the first slew rate is less than the second slew rate, the second slew rate is less than the third slew rate, and the third slew rate is less than the fourth slew rate, the fourth group of signals received by the display panel rises to a valid level first, while the first group of signals rises to a valid level last. The first moment is greater than the second moment, the second moment is greater than the third moment, and the third moment is greater than the fourth moment. This reduces the number of signals received by the display panel at the same time, thereby reducing instantaneous energy.

[0206] In some embodiments, the delay sequence follows the fourth circuit group, the third circuit group, the second circuit group, and the first circuit group, with the first circuit group having the longest delay and the fourth circuit group having the shortest delay. The first moment corresponding to the first circuit group is the longest, and the second, third, and fourth moments decrease in sequence. The moments at which the display panel receives the second signal, corresponding to adjacent driving circuit groups, can be subtracted in the delay sequence to obtain a first time difference, a second time difference, and a third time difference. The first time difference is the time difference between the first moment and the second moment, the second time difference is the time difference between the second moment and the third moment, and the third time difference is the time difference between the third moment and the fourth moment.

[0207] In some embodiments, the delay time differences between adjacent driving circuit groups in the delay sequence can be set to be equal, so that the time differences between the second signals sent by the adjacent driving circuit groups received by the display panel are also equal, that is, the first time difference, the second time difference, and the third time difference are equal. In this way, the delay time differences between adjacent driving circuit groups can be conveniently controlled to avoid the problem of screen segmentation between the display areas driven by the adjacent driving circuit groups. For example, Figure 11 As shown, the first time difference, the second time difference and the third time difference can be respectively Δt, and the delay time difference between adjacent driving circuit groups is Δt=5UI.

[0208] Optionally, the display module further includes a plurality of differential signal lines;

[0209] One end of the differential signal line is electrically connected to an output end of the timing control circuit, and the other end of the differential signal line is electrically connected to an input end of the driving circuit;

[0210] The first signal is a differential signal sent by the timing control circuit to the driving circuit, and the timing at which the timing control circuit sends the differential signal to the plurality of driving circuits is different.

[0211] In some embodiments, the driver circuit and the timing control circuit are connected via differential signal lines. The output of the timing control circuit may include multiple differential output terminals, and one end of the differential signal line is electrically connected to the differential output terminal of the timing control circuit. The input of the driver circuit may be a differential input terminal, and the other end of the differential signal line is electrically connected to the differential input terminal of the driver circuit.

[0212] In some embodiments, the timing control circuit sends the first signal to the driver circuit in the form of a differential signal, that is, the first signal is a differential signal sent by the timing control circuit to the driver circuit. The timing control circuit can send signals to multiple driver circuits in a time-sharing manner. Specifically, the timing control circuit sends the differential signals to the multiple driver circuits at different times, which can reduce the instantaneous energy of the first sending process and achieve the effect of reducing EMI noise of the display module. For example, the multiple first signals sent by the timing control circuit can be delayed separately, so that the clocks of the multiple first signals are not synchronized, thereby enabling the timing control circuit to send the first signal to the multiple driver circuits in a time-sharing manner.

[0213] In some embodiments, the timing control circuit can be a circuit composed of different functional modules or an integrated TCON. Similarly, the driving circuit can also be a circuit composed of different functional modules or an integrated Source Driver IC, which is not limited in the embodiments of the present application. Figure 6As shown, TCON is connected to multiple SourceDriver ICs through independent signal lines, and point-to-point signal transmission can be used between TCON and each Source Driver IC. Figure 9 In the process, TCON sends data to Source Driver IC through a signal line, which may be a differential signal line. Source Driver IC may return a lock signal (LOCK) to TCON.

[0214] Figure 10 : is a schematic diagram of a hardware interface of a timing controller (TCON) provided in an embodiment of the present application, such as Figure 10 As shown, the TCON may include a unified standard interface for TV (USIT). The USIT interface of the TCON may be a differential output terminal, and the USIT interface and the Source Driver IC may be electrically connected via a differential signal line. Figure 5 In the display module shown, the TCON can be connected to XD1 to XD12 respectively through 12 interfaces, namely USIT1P, USIT1N, ..., USIT6P, and USIT6N. The TCON communicates with the Source Driver IC on the COF package through the USIT, thereby realizing point-to-point signal transmission between the TCON and the Source Driver IC.

[0215] Optionally, in a direction away from the central axis, the time difference between the timing control circuit sending the differential signal to two adjacent driving circuits is P bit widths, where P is a positive integer.

[0216] In some embodiments, the timing control circuit can send differential signals to multiple drive circuits by means of clock offset. The timing control circuit can use the drive circuit located on the central axis, or the drive circuit located on both sides of the central axis and closest to the central axis, as the target drive circuit of the clock offset method. The time difference between the timing control circuit sending the differential signal to two adjacent drive circuits can be the delay time difference between the first signals corresponding to the adjacent drive circuits, which is referred to as the clock offset in this embodiment. The clock offset is P bits wide, where P is a positive integer. The value range of P is 6UI to 15UI.

[0217] Optionally, the time when the timing control circuit sends the differential signal to the first circuit group is the fifth time, and the time when the timing control circuit sends the differential signal to the second circuit group is the sixth time;

[0218] The time difference between the fifth moment and the sixth moment is X bit widths, where X is a positive integer.

[0219] In some embodiments, when a timing control circuit sends differential signals to multiple driver circuits, different clock offsets can be set for the differential signals corresponding to different driver circuit groups, so that there is a time difference between the differential signals sent to different driver circuit groups. Specifically, the multiple driver circuits include a first circuit group and a second circuit group. Only the first clock signal embedded in the differential signal corresponding to the first circuit group can be delayed, or both the first circuit group and the second circuit group can be clock offset. However, after the delay, there is a time difference between the differential signals corresponding to the first circuit group and the second circuit group. The time difference is X bits wide, where X is a positive integer. The value range of X is 5UI to 15UI.

[0220] In some embodiments, the plurality of driving circuit groups may further include a third circuit group and a fourth circuit group. The timing control circuit may set different clock offsets for the first circuit group, the second circuit group, the third circuit group, and the fourth circuit group, so that there is a time difference between the differential signals sent by the timing control circuit to each driving circuit group. In the case where the time required for different driving circuits to process the first signal to form the second signal is approximately equal, since there is a time difference between the differential signals, i.e., the first signals, sent by the timing control circuit to the first circuit group, the second circuit group, the third circuit group, and the fourth circuit group, there is also a time difference between the moments when the display panel receives the first group of signals, the second group of signals, the third group of signals, and the fourth group of signals. Among them, the time difference caused by the clock offset between the driving circuit groups in adjacent delay orders can be equal or different, and the embodiments of the present application do not limit this.

[0221] In some embodiments, the time when the second signal is received at the display panel includes the first time, the second time, the third time, and the fourth time corresponding to the first group of signals, the second group of signals, the third group of signals, and the fourth group of signals, respectively. The first time difference is the time difference between the first time and the second time, the second time difference is the time difference between the second time and the third time, and the third time difference is the time difference between the third time and the fourth time.

[0222] Specifically, the first time difference, the second time difference, and the third time difference are equal, which can be achieved by making the time difference between the differential signals sent by the timing control circuit to the adjacent delay sequence driving circuit groups equal, and the time difference is generated because the timing control circuit sets different clock offsets for different driving circuit groups. For example, Figure 11As shown, the first circuit group is drive circuit group d, and the timing control circuit can set the clock offset corresponding to drive circuit group d to 3 times Δt, or 15 UI. The second circuit group is drive circuit group c, and the timing control circuit can set the clock offset corresponding to drive circuit group c to 2 times Δt, or 10 UI. The third circuit group, drive circuit group b, has a clock offset of Δt = 5 UI, and the fourth circuit group, drive circuit group a, has a clock offset of 0. In this way, the time difference between the differential signals sent by the timing control circuit to drive circuit groups a, b, c, and d is 5 UI.

[0223] Optionally, the number of driving circuits is N;

[0224] N is an odd number. The driving circuit located on the central axis is the first driving circuit of the timing control circuit to send a differential signal.

[0225] Alternatively, N is an even number, and the two driving circuits located on both sides of the central axis and closest to the central axis are the first driving circuits to send differential signals in the timing control circuit.

[0226] In some embodiments, the target driving circuit may be the first driving circuit in the timing control circuit to send a differential signal. The number of target driving circuits may be one or two, and may be determined based on the total number of driving circuits in the display module, ensuring that the number of driving circuits on both sides of the central axis of the display panel is equal. This allows for a symmetrical distribution of the driving circuits on both sides of the central axis.

[0227] Specifically, the number of driving circuits is N, which can be an odd number or an even number. If N is an odd number, the driving circuit located on the central axis is the target driving circuit. If N is an even number, the two driving circuits located on both sides of the central axis and closest to the central axis are the target driving circuits. For example, Figure 5 Among the 12 driving circuits of the display module shown, namely the SourceDriver IC, XD6 and XD7 located in the middle can be used as target driving circuits.

[0228] Optionally, the driving circuit further comprises a plurality of signal lines; the display panel further comprises a plurality of data lines; the plurality of signal lines are electrically connected to the data lines of the display panel to serve as channels for transmitting source signals;

[0229] The timings at which the signal lines in different driving circuits receive the source signals are different, and / or the timings at which different signal lines in the driving circuits send the source signals to the connecting lines are different.

[0230] In some embodiments, the signal line in the driving circuit can be a signal line connected to the output end of the driving circuit, used to output the source signal, and can serve as a signal transmission channel within the driving circuit. The data line of the display panel can be a data line that transmits the source signal on the display panel. The data line can be electrically connected to the pixel circuit in the pixel array of the display panel, and is used to transmit the source signal to the pixel circuit. The connecting line in the display module is used to connect the signal line of the driving circuit and the data line of the display panel, for example Figure 5 In the display module shown, the wiring connecting the Source Driver IC and the display panel on the Chip on Film (COF) package can be the connecting wires in this embodiment.

[0231] In some embodiments, the interconnected signal lines, connection lines, and data lines in the display module constitute channels for transmitting source signals. The driver circuit includes multiple channels, each of which may be a channel within the driver circuit for transmitting source signals, with each channel corresponding to a different sequence number. The second signal transmitted by the driver circuit to the display panel includes the source signal transmitted by the driver circuit to the display panel via each channel.

[0232] In some embodiments, the timing control circuit configures parameters such as the delay duration and signal slope of the driver circuits in the driver circuit group, enabling multiple driver circuits to use a time-sharing transmission method during the second transmission process. The second signals transmitted by different driver circuits are delayed separately, specifically, the source signals corresponding to the same channels in the driver circuits of different driver circuit groups are delayed separately. The second signals transmitted by different driver circuits are delayed separately, resulting in the delay time difference between the source signals corresponding to the same channels in adjacent driver circuit groups being a second offset, i.e., the delay time difference between the target second signals being a second offset.

[0233] In some embodiments, during the first transmission process, the timing control circuit can employ a time-sharing transmission method, such that different driver circuits receive the first signal at different times. Multiple driver circuits in a display module can employ the same internal structure. This allows the driver circuits to process the first signal for approximately the same amount of time, and the different driver circuits to generate the second signal for approximately the same amount of time. Because different driver circuits receive the first signal at different times, the different driver circuits transmit the source signal to the signal line at different times, i.e., the signal line receives the source signal at different times.

[0234] Optionally, the plurality of signal lines are arranged along the first direction;

[0235] The first target signal line is one of the plurality of signal lines, and a timing at which the first target signal line sends a source signal is greater than a timing at which other signal lines in the plurality of signal lines send a source signal;

[0236] In a direction away from the first target signal line, the time difference between adjacent signal lines in sending source signals is S bit widths, where S is a positive integer.

[0237] In some embodiments, the source signals sent from different signal lines in the driver circuit to the connecting line are delayed separately. Different delay durations can be set for channels with different sequence numbers in the driver circuit, so that the source signals output by different signal lines are sent in a time-sharing manner. This can reduce the instantaneous energy of the driver circuit during the second transmission process, thereby reducing the EMI noise caused by the second transmission process.

[0238] Specifically, the multiple signal lines in the driving circuit are also arranged along the first direction in which the driving circuit is arranged. The signal line with the longest delay time in the driving circuit can be determined as the first target signal line. Taking the first target signal line as the reference, the time when the first target signal line sends the source signal is greater than the time when other signal lines send the source signal. In the direction away from the first target signal line, the time difference between adjacent signal lines in sending the source signal can be the second offset in this embodiment, thereby setting different delay times for the multiple signal lines in the driving circuit. Specifically, the second offset is S bit widths, where S is a positive integer. Wherein, when the delay time of the first target signal line is known, the delay time of the first target signal line is divided by the number of signal lines to obtain the second offset. Wherein, the product of the value of S and the number of signal lines, that is, the delay time of the first target signal line, should be greater than or equal to 4UI and less than or equal to 16UI.

[0239] In some embodiments, the first configuration parameters embedded in the first signal sent by the timing control circuit to the driver circuit may include a first target signal line and a delay duration of the first target signal line among the multiple signal lines. After receiving the first configuration parameters, the driver circuit can determine the delay durations of the multiple signal lines from shortest to longest based on the delay durations of the first target signal line and the first target signal line during the second transmission process, and sequentially transmit source signals to the display panel via the corresponding signal lines after the delay duration is reached at the transmission moment. In this way, the source signals corresponding to the multiple signal lines are transmitted by the driver circuit in a time-sharing manner during the second transmission process, which can reduce the instantaneous energy of the driver circuit during the second transmission process.

[0240] Optionally, the plurality of signal lines are arranged in a first direction;

[0241] The first target signal line is the signal line with the largest sequence number among the multiple signal lines, or the first target signal line is the signal line with the smallest sequence number among the multiple signal lines, or the first target signal line is the signal line with a middle sequence number among the multiple signal lines.

[0242] In some embodiments, multiple signal lines in a driver circuit can be arranged along a first direction, with each signal line corresponding to a sequence number. A third register for storing a channel delay mode and a fourth register for storing a channel delay duration can be provided in the driver circuit. The first configuration parameter embedded in the first signal sent by the timing control circuit to the driver circuit can include a third register value and a fourth register value, that is, the first configuration parameter includes the channel delay mode corresponding to the location of the first target signal line and a width of F bits corresponding to the delay duration of the first target signal line. After receiving the first configuration parameter, the driver circuit can write the third register value into the third register and write the fourth register value into the fourth register.

[0243] In some embodiments, the channel delay mode includes at least three delay modes: a first delay mode, a second delay mode, and a third delay mode. Figure 19 As shown, the first delay mode indicates that the first target signal line is the signal line with the middle sequence number, corresponding to the V-shift channel delay mode, that is, the delay time corresponding to the signal line with the middle sequence number is the longest. The second delay mode indicates that the first target signal line is the signal line with the smallest sequence number, corresponding to the L-shift channel delay mode, that is, the delay time corresponding to the signal line with the smallest sequence number is the longest. The third delay mode indicates that the first target signal line is the signal line with the largest sequence number, corresponding to the R-shift channel delay mode, that is, the delay time corresponding to the signal line with the largest sequence number is the longest.

[0244] Table 5 Third register configuration table

[0245] DMS_SHIFT<1> DMS_SHIFT<0> MODE 0 0 V-shift 0 1 L-shift 1 0 R-shift 1 1 Default

[0246] As shown in Table 5, the third register may include a DMS_SHIFT<1:0> register, which can store a 2-bit binary value representing a width of F bits. Different register values ​​correspond to different channel delay modes. The 2-bit binary value includes four results: V-shift, L-shift, and R-shift channel delay modes, as well as a default mode in which no channel delay is set. As shown in Table 5, when the DMS_SHIFT register value is set to 00, the V-shift channel delay mode is used; when the DMS_SHIFT register value is set to 01, the L-shift channel delay mode is used; when the DMS_SHIFT register value is set to 11, the R-shift channel delay mode is used; and when DMS_SHIFT is set to 11, no channel delay is set.

[0247] Optionally, the first signal line among the plurality of signal lines that sends a source signal to the connection line is the second target signal line;

[0248] A time difference between the first target signal line and the second target signal line in sending the source signal is greater than zero and less than a 16-bit width.

[0249] In some embodiments, the first signal line among multiple signal lines that sends a source signal to the connecting line can be set as the second target signal line. By controlling the time difference between the first target signal line and the second target signal line in sending the source signal, the problem of screen segmentation in the display area driven by multiple signal lines of the driving circuit can be avoided.

[0250] Table 6 Fourth register configuration table

[0251] DMS_F1<1> DMS_F1<0> Delay duration 0 0 4UI 0 1 8UI 1 0 12UI 1 1 16UI

[0252] In some embodiments, the time difference between the first target signal line and the second target signal line in sending the source signal can be greater than and less than 16 bit widths. As shown in Table 6, the fourth register can include a DMS_F1<1:0> register, which can store a 2-bit binary value, where the 2-bit binary value represents F bit widths. Different register values ​​correspond to different channel delay lengths. As shown in Table 6, when the DMS_F register value is set to 00, the delay length is 4UI, when the DMS_F register value is set to 01, the delay length is 8UI, when the DMS_F register value is set to 10, the delay length is 12UI, and when the DMS_F register value is set to 11, the delay length is 16UI.

[0253] In some embodiments, both the first and second transmission processes may utilize a time-sharing transmission method, or the second transmission process may combine multiple delay methods, such as separately delaying the second signals transmitted by different driver circuits, combined with separately delaying the source signals transmitted by different channels in the driver circuit. As long as the total delay duration of the first and second transmission processes is less than the panel delay duration, the rationality of the panel delay duration must also be confirmed in combination with the actual display conditions of the display panel to ensure that the display panel displays the image normally.

[0254] In some embodiments, the first sending process and the second sending process can both adopt a time-sharing sending method. In the first sending process, the multiple first signals sent by the timing control circuit are delayed respectively, and in the second sending process, the source signals sent by different signal lines in the driving circuit are delayed respectively. For example, based on the delay of the multiple first signals sent by the timing control circuit, Figure 20 As shown in the figure, the channel delay mode of XD1 to 6 is set to L-Shift, and the channel delay mode of XD7 to 12 is set to R-Shift. The configuration of the DMS_SHIFT<1:0> and DMS_F1<1:0> registers is shown in Table 7.

[0255] Table 7 DMS_SHIFT<1:0> and DMS_F1<1:0> register configuration

[0256] XD1~6 XD7~12 Remark DMS_SHIFT0 0 1 L-SHIFT DMS_SHIFT1 1 0 R-SHIFT DMS_F1<0> 0 1 8UI DMS_F1<1> 0 1 8UI

[0257] Among them, the multiple signal lines in the driving circuit corresponding to each XD are divided into 4 areas, and the delay time between two adjacent areas is 8UI. Therefore, for the signal lines XD1-6 or the signal lines XD7-12, the total delay time is 8UI×4×5=160UI.

[0258] For Figure 5 The EMI test results of the display module shown in the figure are as follows: Figure 21 As shown in the figure, the EMI noise exceeds the EMI test requirement (40dB). After taking the improvement measures of adjusting the peak and valley values ​​of the TCON signal in the relevant technology, the Figure 22 As shown in Figure 1, the EMI noise around 600MHz is still higher than 40dB. Figure 23 As shown, the EMI noise is less than 40dB, which can meet the EMI test requirements. Figures 21-23 The noise within 100 MHz is the power supply noise and has nothing to do with the display module. Therefore, the EMI improvement measures provided in this embodiment can be used in conjunction with other EMI improvement measures in related technologies to achieve the effect of reducing the EMI noise of the display panel.

[0259] like Figure 24 As shown, for the display module shown in the above embodiment, its display driving process includes the following steps:

[0260] Step S1, a first sending process, in which the timing control circuit sends a first signal to a plurality of driving circuits according to data of a frame of image; wherein, during the first sending process, the delay time difference between the first signals corresponding to adjacent driving circuits is a preset first offset, and / or the first signal corresponding to at least one driving circuit has a first configuration parameter embedded therein; the first configuration parameter includes a preset second offset;

[0261] Step S2, a second sending process, wherein the driving circuit sends a source signal to the display panel according to the first signal; wherein, during the second sending process, a delay time difference between the source signals of at least one driving circuit is a second offset; the source signal includes source signals corresponding to a plurality of channels in the driving circuit; and at least one of the first offset and the second offset is non-zero, such that a first time when the display panel receives the first set of signals is greater than a second time when the display panel receives the second set of signals;

[0262] The second signal includes a first group of signals and a second group of signals. The first group of signals is the second signal sent to the display panel by the first circuit group among the multiple driving circuits. The second group of signals is the second signal sent to the display panel by the second circuit group among the multiple driving circuits.

[0263] In some embodiments, delaying multiple first signals separately can be achieved by clock offset. In this embodiment, the delay time difference between the first signals corresponding to adjacent driving circuits is referred to as clock offset. Among them, the first signal embeds the first clock signal, and the delay time between the first signals refers to the delay time difference between the first clock signals. Before the first sending process, the clock offset is pre-configured in the timing control circuit to be a preset first offset, and the first offset is not zero. During the first sending process, the timing control circuit can determine the sending time corresponding to each first signal according to the preset first offset, and send the first signal to the corresponding driving circuit after the sending time is reached.

[0264] In this way, for a frame of image, the timing control circuit obtains the first signal corresponding to each driving circuit based on the data of the frame of image, and then sends multiple first signals to the driving circuit in a time-sharing manner, so that the first sending process reduces the instantaneous energy and can achieve the effect of reducing EMI noise.

[0265] Optionally, step S1 includes the following sub-steps:

[0266] Sub-step A1: the timing control circuit sends a corresponding first signal to the target driving circuit;

[0267] In sub-step A2, the timing control circuit uses the target driving circuit as a reference and sequentially sends corresponding first signals to adjacent driving circuits according to a first offset, wherein the first offset represents a clock offset of the first signals received by the adjacent driving circuits.

[0268] In some embodiments, the target driving circuit is a reference for the timing control circuit to perform clock shift. During the first sending process, the timing control circuit can send the corresponding first signal to the target driving circuit, and then use the data sending time corresponding to the target driving circuit as a reference to determine the data sending time corresponding to the adjacent driving circuit according to the first offset. After reaching the data sending time, the corresponding first signal is sent to the driving circuit. In this way, the corresponding first signals are sent to the adjacent driving circuits in sequence, so that the first signal is sent to multiple driving circuits in a time-sharing manner during the first sending process.

[0269] For example, Figure 25 As shown, Figure 5Among the 12 driver circuits of the display module shown, the Source Driver ICs XD6 and XD7 located on the middle COF package serve as the target driver circuits. The delay time of the first signal corresponding to the target driver circuit is zero. The driver circuits adjacent to the target driver circuit include the Source Driver ICs XD5 and XD8. The delay time difference between the first signals corresponding to the Source Driver ICs XD8 and XD7 is 6UI, that is, the first offset is 6UI. Figure 25 As shown, the total delay time of the timing control circuit in the first sending process is 30UI, which is the delay time corresponding to XD1 and XD12. Figure 25 For a display module in which the number of Source Driver ICs is even and the delay times of different Source Driver ICs are symmetrically arranged, when the first offset is known, the total delay time corresponding to TCON can be calculated by referring to the following formula (7).

[0270]

[0271] Tskew sum represents the total delay duration, and Tskew represents the first offset.

[0272] for Figure 10 The timing controller shown, Figure 26 The clock skew (Tskew) between adjacent differential pairs output by adjacent USIT interfaces USIT0 and USIT1 is shown. Figure 27 The first signal sent by the timing control circuit to the adjacent driving circuit is shown. The two first signals are respectively embedded with the first clock signal. The first clock signal can be Figure 6 The training clock signal is shown as Figure 27 As shown, there is an obvious misalignment between the first clock signals corresponding to adjacent driving circuits, and the delay time difference between the two first clock signals is a first offset.

[0273] Compared with the measures of improving EMI by using a spread spectrum clock generator in related technologies, the clock offset method is not limited by device specifications and has greater versatility.

[0274] Optionally, step S1 includes the following sub-steps:

[0275] In sub-step A3, the timing control circuit sends a first signal with a first configuration parameter embedded in it to at least one driving circuit, and sends a first signal with a second configuration parameter embedded in it to other driving circuits, wherein the signal waveform of the first signal with the first configuration parameter embedded in it is different from the signal waveform of the first signal with the second configuration parameter embedded in it, and the first signal with the second configuration parameter embedded in it is used to control the other driving circuits to simultaneously send the second signal to the display panel.

[0276] Optionally, before step S2, the display driving process further includes:

[0277] Step S3: the driving circuit stores a second offset in response to the first signal embedded with the first configuration parameter; wherein the first configuration parameter includes the second offset;

[0278] Step S2 includes the following sub-steps:

[0279] In sub-step B1, the driving circuit delays sending a second signal to the display panel, wherein the delay time difference between the rising edges of the target second signals in adjacent driving circuits is a second offset, and the target second signal includes source signals corresponding to channels with the same serial number in multiple driving circuits.

[0280] In some embodiments, after the second signals sent by different driving circuits are delayed respectively, there is a delay time difference between the source signals corresponding to the channels with the same serial number in different driving circuits. The delay time difference is the second offset preset in the first configuration parameter. At this time, the second offset is not zero, indicating that the second sending process corresponding to multiple driving circuits adopts a time-sharing sending method.

[0281] Step S2 includes the following sub-steps:

[0282] In sub-step B2, the driving circuit sends a second signal to the driving circuit according to a preset rising edge duration; wherein the rising edge duration difference between the target second signals in adjacent driving circuits is a second offset; and the target second signal includes source signals corresponding to channels with the same serial number in multiple driving circuits.

[0283] Step S2 includes the following sub-steps:

[0284] In sub-step B3, the driving circuit sends source signals to the display panel through multiple channels in order of delay time from shortest to longest; wherein the delay time difference between the source signals corresponding to channels with adjacent serial numbers is a third offset; and the sum of the third offsets corresponding to the multiple channels is equal to the second offset.

[0285] In an embodiment of the present application, the driver circuit can, under the control of a control instruction embedded in the first signal, obtain image data, i.e., a second signal, from the first signal, and transmit the second signal to the display panel according to the data transmission method indicated by the control instruction, thereby driving the display panel to display an image via the second signal. The control instruction embedded in the first signal can be a first configuration parameter or a second configuration parameter, where the first configuration parameter is used to control the driver circuit to transmit the second signal to the display panel in a time-sharing manner during the second transmission process, and the second configuration parameter is used to control the driver circuit to transmit the second signal to the display panel synchronously during the second transmission process.

[0286] Specifically, for a driving circuit among multiple driving circuits that uses a time-sharing transmission method, the timing control circuit may embed a first configuration parameter in the first signal, and control the driving circuit to transmit the source signal to the display panel in a time-sharing manner using the first configuration parameter. For a driving circuit among multiple driving circuits that uses a synchronous transmission method, the timing control circuit may embed a second configuration parameter in the first signal, and control the driving circuit to transmit the source signal to the display panel synchronously using the second configuration parameter.

[0287] In some embodiments, due to the different functions of the first configuration parameter and the second configuration parameter, there are differences in the instruction content of the first configuration parameter and the second configuration parameter, which are manifested in differences in the signal waveform. Even if the first configuration parameters are different, if the delay modes corresponding to the first configuration parameters are different, there are differences in the instruction content, which are manifested in differences in the signal waveform. For example, the first configuration parameter and the second configuration parameter include different configuration parameters, and the configuration parameters are used to configure the registers in the driving circuit, such as Figure 6 The configuration signal waveforms shown, the signal waveform of the first configuration parameter and the signal waveform of the second configuration parameter, differ in parameters such as signal amplitude, frequency or phase.

[0288] In the embodiments of the present application, the instantaneous energy of the second transmission process is reduced, thereby reducing the EMI noise caused by the second transmission process. Compared with the EMI improvement method of scrambling and descrambling in related technologies, the method of controlling at least one driving circuit to transmit the source signal in a time-sharing manner by a timing control circuit does not require the provision of additional scrambling and descrambling circuits. The complexity of the data transmission process is reduced, the risk of display panel image abnormalities can be avoided, and security is high.

[0289] Optionally, step S1 includes the following sub-steps:

[0290] Sub-step A4, when the sum of the first delay time and the second delay time is less than the preset panel delay time, execute the step of sending the first signal to multiple driving circuits respectively according to the data of a frame of image by the timing control circuit, wherein the first delay time is the total delay time corresponding to the timing control circuit, the second delay time is the total delay time corresponding to the multiple driving circuits, and the panel delay time represents the delay time threshold for driving the display panel to normally display a frame of image.

[0291] In an embodiment of the present application, the panel delay duration represents the delay duration threshold for driving the display panel to normally display a frame of image, such as △T=0.25us calculated according to Table 2 in the aforementioned embodiment, or △UI=325UI after unit conversion. The first delay duration is the total delay duration corresponding to the timing control circuit, that is, the total delay duration of multiple first signals in the first transmission process. The second delay duration is the total delay duration corresponding to multiple driving circuits, that is, the total delay duration of multiple second signals in the second transmission process. The sum of the first delay duration and the second delay duration should be less than the preset panel delay duration, so that the display panel can have sufficient charging time, thereby ensuring that the display panel normally displays a frame of image, and avoiding abnormal screen phenomena on the display panel.

[0292] Figure 28 This is a flow chart of a display driving process provided by an embodiment of the present application, such as Figure 28 As shown, for any display module, the display module parameters are substituted into formula (1) to calculate the charging time, and then the panel delay duration is calculated based on the charging time. Multiple drive circuits are grouped to obtain multiple drive circuit groups. A time-sharing transmission method is used for at least one of the first and second transmission processes to drive the display panel to display a frame of image. In practical applications, the data transmission method of the first and second transmission processes can be adjusted by checking the image quality of the display panel to ensure that the display panel can normally display a frame of image.

[0293] Compared with the current improvement measures, the embodiment of the present application provides a display module and display driving process. The first sending process and the second sending process are not limited by the specifications of the timing control circuit and the driving circuit, but are only related to the data sending method adopted by the timing control circuit and the driving circuit. The signal peak and valley values ​​are not changed, so the signal quality is not affected, and no disturbance and recovery process is required. Therefore, the EMI effect of the display module can be improved without affecting the display effect of the display module.

[0294] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0295] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0296] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0297] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements that are inherent to such process, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, article, or terminal device that includes the element.

[0298] The above is a detailed introduction to a display module provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display module, characterized in that: The display module includes: a timing control circuit, a plurality of driving circuits and a display panel connected in sequence; The input terminal of the driving circuit is electrically connected to the output terminal of the timing control circuit, and the timing control circuit is configured to identify a first signal sent to the driving circuit and control the timing of the first signal; The output terminal of the driving circuit is electrically connected to the input terminal of the display panel, and the driving circuit is configured to receive and process the first signal to form a second signal to be input to the display panel; The plurality of driving circuits are arranged in an array along a first direction, and the plurality of driving circuits are symmetrically distributed about a central axis of the display panel, the central axis extends along a second direction, and the first direction and the second direction are orthogonal; The plurality of driving circuits include a first circuit group and a second circuit group, the first circuit group includes a first driving circuit and a second driving circuit, and the second circuit group is arranged between the first driving circuit and the second driving circuit; The second signal includes a first group of signals and a second group of signals, the first group of signals being the second signals sent by the first circuit group to the display panel, and the second group of signals being the second signals sent by the second circuit group to the display panel, wherein the moment when the display panel receives the first group of signals is a first moment, and the moment when the display panel receives the second group of signals is a second moment, and the first moment is greater than the second moment.

2. The display module according to claim 1, wherein: There is a first time difference between the first moment and the second moment; The first time difference is greater than or equal to 5 bits in width, and the first time difference is less than or equal to 15 bits in width.

3. The display module according to claim 1, wherein: The first set of signals has a first slew rate, and the second set of signals has a second slew rate; The first slew rate is smaller than the second slew rate.

4. The display module according to claim 1, wherein: The duration of the rising edge of the first group of signals changing from a first level to a second level is a first duration, and the duration of the rising edge of the second group of signals changing from the first level to the second level is a second duration, wherein the second level is greater than the first level; The first duration is greater than the second duration.

5. The display module according to claim 4, wherein: The difference between the first duration and the second duration is greater than zero and less than 4 bits in width.

6. The display module according to claim 1, wherein: There is a first duration between the rising edge and the falling edge of the first group of signals, and there is a second duration between the rising edge and the falling edge of the second group of signals, wherein, The first duration is shorter than the second duration.

7. The display module according to any one of claims 1 to 6, characterized in that: The second circuit group includes a third driving circuit and a fourth driving circuit, and the plurality of driving circuit groups further includes a third circuit group; A portion of the third circuit group is located between the first drive circuit and the third drive circuit, and another portion of the third circuit group is located between the second drive circuit and the fourth drive circuit; The second signal also includes a third group of signals, which are the second signals sent by the third circuit group to the display panel. The moment when the display panel receives the third group of signals is a third moment, which is smaller than the second moment.

8. The display module according to claim 7, wherein: The third circuit group includes a fifth driving circuit and a sixth driving circuit, and the plurality of driving circuit groups further includes a fourth circuit group; A portion of the fourth circuit group is located between the fifth drive circuit and the third drive circuit, and another portion of the third circuit group is located between the sixth drive circuit and the fourth drive circuit; The second signal also includes a fourth group of signals, which are the second signals sent by the fourth circuit group to the display panel. The moment when the display panel receives the fourth group of signals is a fourth moment, which is smaller than the third moment.

9. The display module according to claim 8, wherein: The fourth circuit group includes a seventh drive circuit and an eighth drive circuit, and the third circuit group also includes a ninth drive circuit and a tenth drive circuit, wherein the ninth drive circuit is located between the third drive circuit and the seventh drive circuit, and the tenth drive circuit is located between the fourth drive circuit and the eighth drive circuit, the ninth drive circuit and the fifth drive circuit are symmetrical with respect to the seventh drive circuit, and the sixth drive circuit and the tenth drive circuit are symmetrical with respect to the eighth drive circuit. and / or, The second circuit group further includes an eleventh drive circuit and a twelfth drive circuit, wherein the eleventh drive circuit is located between the first drive circuit and the seventh drive circuit, the twelfth drive circuit is located between the second drive circuit and the eighth drive circuit, the eleventh drive circuit and the third drive circuit are symmetrical with respect to the seventh drive circuit, and the twelfth drive circuit and the fourth drive circuit are symmetrical with respect to the eighth drive circuit.

10. The display module according to claim 8, wherein: The first time difference is the time difference between the first moment and the second moment, the second time difference is the time difference between the second moment and the third moment, and the third time difference is the time difference between the third moment and the fourth moment; The first time difference, the second time difference and the third time difference are equal; and / or, The third group of signals has a third slew rate, the fourth group of signals has a fourth slew rate, the first slew rate is smaller than the second slew rate, the second slew rate is smaller than the third slew rate, and the third slew rate is smaller than the fourth slew rate.

11. The display module according to any one of claims 1 to 6, characterized in that: The display module further includes a plurality of differential signal lines; One end of the differential signal line is electrically connected to an output end of the timing control circuit, and the other end of the differential signal line is electrically connected to an input end of the driving circuit; The first signal is a differential signal sent by the timing control circuit to the driving circuit, and the timing at which the timing control circuit sends the differential signal to the plurality of driving circuits is different.

12. The display module according to claim 11, wherein: In a direction away from the central axis, the time difference between the timing control circuit sending the differential signal to two adjacent driving circuits is P bit widths, where P is a positive integer.

13. The display module according to claim 11, wherein: The time when the timing control circuit sends the differential signal to the first circuit group is the fifth time, and the time when the timing control circuit sends the differential signal to the second circuit group is the sixth time; The time difference between the fifth moment and the sixth moment is X bit width, where X is a positive integer.

14. The display module according to claim 11, wherein: The number of the driving circuits is N; N is an odd number, and the driving circuit located on the central axis is the first driving circuit of the timing control circuit to send the differential signal. Alternatively, N is an even number, and the two driving circuits located on both sides of the central axis and closest to the central axis are the first driving circuits of the timing control circuit to send the differential signal.

15. The display module according to any one of claims 1 to 6, characterized in that: The first driving circuit among the plurality of driving circuits that sends the second signal to the display panel is a target driving circuit, and the target driving circuit belongs to the second circuit group; The time when the display panel receives the second signal sent by the target driving circuit is a target time, and the time difference between the first time and the target time is greater than or equal to 15 bit widths and less than 325 bit widths; The time difference between the second moment and the target moment is greater than or equal to 0 and less than a width of 15 bits.

16. The display module according to any one of claims 1 to 6, characterized in that: The driving circuit further comprises a plurality of signal lines; the display panel further comprises a plurality of data lines; the plurality of signal lines are electrically connected to the data lines of the display panel and serve as channels for transmitting source signals; The signal lines in different driving circuits receive the source signal at different times, and / or the signal lines in different driving circuits send the source signal at different times.

17. The display module according to claim 16, wherein: The plurality of signal lines are arranged along the first direction; The first target signal line is one of the plurality of signal lines, and a timing at which the first target signal line sends the source signal is greater than a timing at which the other signal lines in the plurality of signal lines send the source signal; In a direction away from the first target signal line, a time difference between adjacent signal lines in sending the source signal is S bit widths, where S is a positive integer.

18. The display module according to claim 17, wherein: The plurality of signal lines are arranged along the first direction; The first target signal line is the signal line with the largest sequence number among the multiple signal lines, or the first target signal line is the signal line with the smallest sequence number among the multiple signal lines, or the first target signal line is a signal line with a middle sequence number among the multiple signal lines.

19. The display module according to claim 17, wherein: The first signal line among the plurality of signal lines that sends the source signal to the connecting line is a second target signal line; the connecting line is used to connect the signal line of the driving circuit and the data line of the display panel; A time difference between the first target signal line and the second target signal line in sending the source signal is greater than zero and less than a 16-bit width.

20. The display module according to claim 1, wherein: The charging time of the display module is greater than or equal to 1.6 microseconds.

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