Gallium nitride power device with multiple layers of field plates
By adopting a multi-layer field plate structure in the GaN high electron mobility transistor device and controlling the etching rate ratio to 10:1, the problem of electric field concentration caused by etching damage is solved, and the reliability and preparation efficiency of the device are improved.
Patent Information
- Application Number
- CN202422797137.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-09-26
- Estimated Expiration
- 2034-11-18
AI Technical Summary
In existing GaN high electron mobility transistor devices, the etching process of the multi-layer field plate easily leads to excessive electric field strength at the edge of the field plate, which makes breakdown easy to occur. In addition, the dielectric layer quality requirements are high, which affects the reliability of the device.
A multi-layer field plate structure is adopted, in which the etching rate of the lower dielectric layer is lower than that of the upper dielectric layer. By controlling the etching rate ratio to 10:1, additional etching of the barrier layer is avoided, etching damage is reduced, and a good field plate shape forming effect is ensured.
The reliability of the device is improved, the local concentration effect of the electric field is reduced, the preparation process is simplified, and time is saved.
Smart Images
Figure CN223391593U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductor devices, in particular to a gallium nitride power device with a multi-layer field plate. Background Art
[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) offer superior performance and broad application prospects in high-frequency and high-power applications. GaN HEMTs are primarily categorized as depletion-mode (D-mode) and enhancement-mode (E-mode). Depletion-mode HEMTs have a simpler structure, maximizing the high electron concentration and mobility of the GaN heterojunction. They also offer a highly reliable gate.
[0003] In GaN HEMT devices, the introduction of field plates can suppress surface electric field concentration and mitigate electric field spikes. For high-voltage devices, multiple layers of field plates are typically required, and the length and height of each layer are adjusted to achieve the desired electric field distribution. However, this technology has the disadvantage that the electric field intensity is higher at the edges of the field plates, making breakdown more likely to occur prematurely at lower potentials, and potentially at the surface, placing higher demands on the quality of the dielectric layer.
[0004] Existing devices use a contact field plate structure with an etch barrier layer between the dielectric layers. The existing field plate process requires dry etching of the dielectric layer followed by wet etching of the etch barrier layer. Multiple etching steps can easily damage the contact area between the field plate metal, etch barrier layer, and dielectric layer, leading to uneven local electric field distribution and impacting device reliability. Utility Model Content
[0005] The utility model provides a gallium nitride power device with a multi-layer field plate, which can improve the reliability of the device.
[0006] An embodiment of the present invention provides a gallium nitride power device with a multi-layer field plate, comprising:
[0007] GaN substrate;
[0008] a first dielectric layer disposed on the gallium nitride substrate; the first dielectric layer comprising a source ohmic contact hole and a drain ohmic contact hole, wherein a source ohmic electrode is disposed in the source ohmic contact hole, and wherein a drain ohmic electrode is disposed in the drain ohmic contact hole;
[0009] a second dielectric layer, disposed on the first dielectric layer, the source ohmic electrode, and the drain ohmic electrode;
[0010] A lower dielectric layer is provided on the second dielectric layer; a primary field plate is provided between the lower dielectric layer and the second dielectric layer; a lower field plate region and an upper dielectric region are provided on the upper surface of the lower dielectric layer; the lower dielectric layer is provided with a gate setting through hole; a lower field plate is provided in the lower field plate region;
[0011] an upper dielectric layer, directly connected to the lower dielectric layer and located in the upper dielectric region; under the same etching conditions, the etching rate of the lower dielectric layer is lower than the etching rate of the upper dielectric layer; an upper field plate is provided on the upper dielectric layer; and
[0012] The gate metal is arranged in the gate setting through hole, and the top of the gate metal extends to the bottom dielectric layer.
[0013] Wherein, the lower field plate is connected to the upper field plate.
[0014] The lower field plate is connected to the gate metal, or the lower field plate is separated from the gate metal.
[0015] Wherein, the etching rate ratio of the upper dielectric layer and the lower dielectric layer under the same etching conditions is greater than 10:1.
[0016] A protective dielectric layer is provided on the upper dielectric layer and the lower dielectric layer, and the protective dielectric layer is located below the lower field plate and the upper field plate; the top of the gate metal extends above the protective dielectric layer.
[0017] The gate metal penetrates the second dielectric layer and the first dielectric layer, and the bottom of the gate metal is connected to the gallium nitride substrate and is insulated from the source ohmic electrode and the drain ohmic electrode.
[0018] Another embodiment of the present invention provides a gallium nitride power device with a multi-layer field plate, comprising:
[0019] GaN substrate;
[0020] a first dielectric layer disposed on the gallium nitride substrate; the first dielectric layer comprising a source ohmic contact hole and a drain ohmic contact hole, wherein a source ohmic electrode is disposed in the source ohmic contact hole, and wherein a drain ohmic electrode is disposed in the drain ohmic contact hole;
[0021] a second dielectric layer, disposed on the first dielectric layer, the source ohmic electrode, and the drain ohmic electrode;
[0022] A third dielectric layer is provided on the second dielectric layer, a primary field plate is provided between the third dielectric layer and the second dielectric layer; the third dielectric layer is provided with a gate setting through hole;
[0023] A lower dielectric layer is provided on the third dielectric layer; a secondary field plate is provided between the lower dielectric layer and the first dielectric layer; a lower field plate region and an upper dielectric region are provided on the upper surface of the lower dielectric layer; a lower field plate is provided in the lower field plate region;
[0024] an upper dielectric layer disposed at the location of the upper dielectric region; under the same etching conditions, the etching rate of the lower dielectric layer is lower than the etching rate of the upper dielectric layer; an upper field plate is disposed on the upper dielectric layer; and
[0025] A gate metal is disposed in the gate setting through hole, and a top portion thereof extends between the third dielectric layer and the lower dielectric layer.
[0026] The secondary field plate is connected to the gate metal, or the secondary field plate is separated from the gate metal.
[0027] Wherein, a protective dielectric layer is provided on the upper dielectric layer and the lower dielectric layer, and the protective dielectric layer is located below the lower field plate and the upper field plate.
[0028] Yet another embodiment of the present invention provides a gallium nitride power device with a multi-layer field plate, comprising:
[0029] GaN substrate;
[0030] a first dielectric layer disposed on the gallium nitride substrate; the first dielectric layer comprising a source ohmic contact hole and a drain ohmic contact hole, wherein a source ohmic electrode is disposed in the source ohmic contact hole, and wherein a drain ohmic electrode is disposed in the drain ohmic contact hole;
[0031] a second dielectric layer, disposed on the first dielectric layer, the source ohmic electrode, and the drain ohmic electrode;
[0032] a third dielectric layer, disposed on the second dielectric layer, with a primary field plate disposed between the third dielectric layer and the second dielectric layer;
[0033] A lower dielectric layer is provided on the third dielectric layer; a secondary field plate is provided between the lower dielectric layer and the third dielectric layer; a lower field plate region and an upper dielectric region are provided on the upper surface of the lower dielectric layer; the lower dielectric layer is provided with a gate setting through hole; a lower field plate is provided in the lower field plate region;
[0034] an upper dielectric layer disposed at the location of the upper dielectric region; under the same etching conditions, the etching rate of the lower dielectric layer is lower than the etching rate of the upper dielectric layer; an upper field plate is disposed on the upper dielectric layer; and
[0035] The gate metal is disposed within the gate setting through hole, with its top extending above the lower dielectric layer. The gallium nitride power device with a multi-layer field plate provided by the utility model has a lower etching rate for the lower dielectric layer than for the upper dielectric layer under the same etching conditions. After the upper dielectric layer outside the upper dielectric region is completely etched away, only a small portion of the lower dielectric layer is etched away. The upper and lower dielectric layers can be directly connected, eliminating the need for an etch stop layer between the two dielectric layers, reducing the manufacturing process and saving preparation time. Furthermore, the formation of a gap between the two dielectric layers can be avoided, and the field plate has a better shape forming effect at this position, thereby reducing the local concentration effect of the electric field caused by etching damage and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 This is a schematic structural diagram of a gallium nitride power device with a multi-layer field plate provided in Example 1 of the present utility model.
[0037] Figure 2A-2F This is a schematic diagram of the manufacturing process of a gallium nitride power device with a multi-layer field plate provided in Example 1 of the present invention.
[0038] Figure 3 This is a schematic structural diagram of a gallium nitride power device with a multi-layer field plate provided in Example 2 of the present utility model.
[0039] Figure 4 This is a schematic structural diagram of a gallium nitride power device with a multi-layer field plate provided in Example 3 of the present utility model.
[0040] Figure 5 This is a schematic structural diagram of a gallium nitride power device with a multi-layer field plate provided in Example 4 of the present utility model.
[0041] Figure 6 This is a schematic structural diagram of a gallium nitride power device with a multi-layer field plate provided in Example 5 of the present utility model.
[0042] Figure 7 This is a schematic structural diagram of a gallium nitride power device with a multi-layer field plate provided in Example 6 of the present utility model.
[0043] Figure 8 This is a schematic structural diagram of a gallium nitride power device with a multi-layer field plate provided in Example 7 of the present utility model. DETAILED DESCRIPTION
[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.
[0045] In the figures, structurally similar elements are denoted by the same reference numerals.
[0046] Example 1
[0047] The semiconductor device with a multi-layer field plate provided in this embodiment is a D-type gallium nitride high electron mobility transistor, which can be used as a high-power application device such as a switching device or an amplifier device.
[0048] like Figure 1 As shown, the gallium nitride power device with a multi-layer field plate of this embodiment includes a gallium nitride substrate 1 , a first dielectric layer 31 , a second dielectric layer 32 , a lower dielectric layer 51 , an upper dielectric layer 52 and a gate metal 6 .
[0049] The first dielectric layer 31 is disposed on the gallium nitride substrate 1 ; the first dielectric layer 31 includes a source ohmic contact hole 201 and a drain ohmic contact hole 202 . A source ohmic electrode 21 is disposed in the source ohmic contact hole 201 , and a drain ohmic electrode 22 is disposed in the drain ohmic contact hole 202 .
[0050] The second dielectric layer 32 is disposed on the first dielectric layer 31 , the source ohmic electrode 21 , and the drain ohmic electrode 22 .
[0051] The lower dielectric layer 51 is disposed on the second dielectric layer 32; a primary field plate 41 is disposed between the lower dielectric layer 51 and the second dielectric layer 32; a lower field plate region and an upper dielectric region are disposed on the upper surface of the lower dielectric layer 51; a gate placement through hole 60 is disposed in the lower dielectric layer 51; and a lower field plate 71 is disposed in the lower field plate region. In this embodiment, the lower field plate 71 is connected to the gate metal 6 so that the two can be fabricated and formed simultaneously.
[0052] The upper dielectric layer 52 is directly connected to the lower dielectric layer 51 and is located in the upper dielectric region. Under the same etching conditions, the etching rate of the lower dielectric layer 51 is lower than that of the upper dielectric layer 52. An upper field plate is disposed on the upper dielectric layer 52. In this embodiment, the lower field plate 71 is connected to the upper field plate. Of course, in other embodiments, the lower field plate 71 and the upper field plate can also be disposed separately.
[0053] The gate metal 6 is disposed in the gate setting through hole 60 , and the top of the gate metal 6 extends to above the underlying dielectric layer 51 .
[0054] Under the same etching conditions, the etching rate of the lower dielectric layer 51 is lower than the etching rate of the upper dielectric layer 52, so that when the upper dielectric layer 52 is etched, the etching of the lower dielectric layer 51 is reduced. Therefore, there is no need to set an additional etching barrier layer between the upper dielectric layer 52 and the lower dielectric layer 51 to prevent the lower dielectric layer 51 from being etched through, thereby reducing the production process and saving preparation time; at the same time, it can avoid the formation of gaps between the two dielectric layers, thereby reducing the local concentration effect of the electric field caused by etching damage, and improving the reliability of the device.
[0055] Furthermore, preferably, the etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same etching conditions is greater than 10:1, so that the etching rate of the lower dielectric layer 51 is much lower than the etching rate of the upper dielectric layer 52. The upper dielectric layer 52 and the lower dielectric layer 51 can be made of homogeneous or heterogeneous materials. Here, a suitable dielectric material can be selected to achieve the above-mentioned etching rate ratio under the same conditions.
[0056] The gallium nitride power device in this embodiment can be manufactured by the following method.
[0057] Step S110 : providing a gallium nitride substrate 1 , and depositing a first dielectric layer 31 on the gallium nitride substrate 1 .
[0058] In the present utility model, Figure 2A As shown, the gallium nitride substrate 1 includes a silicon substrate 11 , a gallium nitride (GaN) layer 12 , an aluminum gallium nitride (ALGaN) layer 13 , and a silicon nitride (SiN) layer 14 , which are sequentially arranged.
[0059] The first dielectric layer 31 is deposited on a side of the gallium nitride substrate 1 away from the silicon substrate 11 .
[0060] In step S120 , the first dielectric layer 31 and the gallium nitride substrate 1 in the source region and the drain region are etched to form a source ohmic contact hole 201 in the source region and a drain ohmic contact hole 202 in the drain region.
[0061] The source ohmic contact hole 201 and the drain ohmic contact hole 202 both penetrate the first dielectric layer 31 and the silicon nitride layer 14 , and their depths reach the AlGaN layer 13 , so that the fabricated ohmic electrodes can contact the AlGaN layer 13 .
[0062] Step S130 , depositing an ohmic metal layer in the source ohmic contact hole 201 , the drain ohmic contact hole 202 and on the first dielectric layer 31 , and etching the ohmic metal layer to form the source ohmic electrode 21 and the drain ohmic electrode 22 . This step specifically includes the following sub-steps.
[0063] Step S131: Deposit an ohmic metal layer. The ohmic metal layer covers the first dielectric layer 31 and fills the source ohmic contact hole 201 and the drain ohmic contact hole 202. The ohmic metal layer is preferably a stack of titanium and aluminum. Titanium has strong adhesion to the gallium nitride substrate, ensuring the mechanical stability of the ohmic metal contact; aluminum naturally forms an ohmic contact with the gallium nitride substrate. Of course, in other embodiments, the ohmic metal layer can also be a multilayer structure formed by various combinations of metals, such as titanium, aluminum, nickel, and gold.
[0064] Step S132: Anneal the ohmic metal layer. Preferably, the ohmic metal layer can be annealed. An RTP (Rapid Thermal Processing) annealing process can be used to repair lattice defects, eliminate stress, and optimize the material's conductivity. Annealing the ohmic metal layer before etching reduces deformation caused by grain growth and rearrangement during the annealing process, reduces stress, and maintains the overall shape of the ohmic metal layer, effectively addressing the issue of deteriorating ohmic contact resistance.
[0065] In step S133 , preferably, a titanium nitride metal layer (not shown in the figure) may be deposited on the ohmic metal layer. The titanium nitride metal layer covers the ohmic metal layer.
[0066] In step S134 , the titanium nitride metal layer and the ohmic metal layer are etched to form a source ohmic electrode 21 and a drain ohmic electrode 22 .
[0067] In this embodiment, a diffusion barrier layer can be deposited on the first dielectric layer 31 before depositing the ohmic metal layer. The diffusion barrier layer is aluminum nitride or aluminum oxide deposited by atomic vapor deposition or physical vapor deposition, or highly dense silicon oxide, silicon nitride, or silicon oxynitride deposited by chemical vapor deposition. In this embodiment, the diffusion barrier layer is an aluminum nitride layer. This diffusion barrier layer is a highly dense dielectric layer that prevents the ohmic metal layer from diffusing into the underlying first dielectric layer 31 during the annealing process, thereby improving device reliability.
[0068] When etching the titanium nitride metal layer and the ohmic metal layer, the diffusion barrier layer is also etched to expose the first dielectric layer 31 .
[0069] Through the above steps, the source ohmic electrode 21 and the drain ohmic electrode 22 can be formed. Here, the source ohmic electrode 21 and the drain ohmic electrode 22 can also be made by other methods, and the specific structure of the source ohmic electrode 21 and the drain ohmic electrode 22 is not limited to the above embodiment.
[0070] Step S140: depositing a second dielectric layer 32 on the first dielectric layer 31, the source ohmic electrode 21 and the drain ohmic electrode 22. Figure 2AFIG. 1 is a schematic diagram of the structure after the second dielectric layer 32 is deposited.
[0071] Step S150: fabricating a primary field plate 41 on the second dielectric layer 32. This step includes the following sub-steps.
[0072] Step S151, as Figure 2B As shown, a field plate metal is deposited on the second dielectric layer 32 and then a mask is set.
[0073] Step S152, forming a primary field plate 41 on the second dielectric layer 32 by etching, and finally removing the mask, such as Figure 2C , which is a schematic structural diagram after the primary field plate 41 is prepared and formed.
[0074] Step S160, as Figure 2D As shown, a lower dielectric layer 51 and an upper dielectric layer 52 are sequentially deposited on the second dielectric layer 32 and the primary field plate 41. The etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same etching conditions is greater than 10:1.
[0075] Step S170, etching the upper dielectric layer 52 except the upper dielectric region to form an upper field plate region on the upper dielectric layer 52 and a lower field plate region on the lower dielectric layer 51. Figure 2E , which is a schematic diagram of the structure after etching of the upper dielectric layer 52 is completed.
[0076] When etching the upper dielectric layer 52, the upper dielectric layer 52 located in the upper dielectric area is retained, and the rest of the upper dielectric layer 52 is completely etched away. Due to the large difference in etching rates between the upper and lower dielectric layers, after the upper dielectric layer 52 outside the upper dielectric area is completely etched away, only a small portion of the lower dielectric layer 51 is etched away or is almost not etched, ensuring that the thickness of the lower dielectric layer 51 meets the predetermined requirements, thereby eliminating the need to set an etch stop layer between the two dielectric layers.
[0077] Step S180: performing etching in the gate region to form a gate setting through hole 60 on the lower dielectric layer 51. Figure 2F FIG. 1 is a schematic diagram of the structure after the gate through hole 60 is prepared and formed.
[0078] The second dielectric layer 32 and the first dielectric layer 31 are further etched through at the location where the gate through hole 60 is set to expose the silicon nitride layer 14 of the gallium nitride substrate 1, forming a gate contact hole so that the prepared gate metal 6 can contact the silicon nitride layer 14 of the gallium nitride substrate 1.
[0079] In step S190, a gate metal 6 is formed at the gate through-hole 60, a lower field plate 71 is formed on the lower field plate region, and an upper field plate 72 is formed on the upper field plate region. The gate metal 6 penetrates the second dielectric layer 32 and the first dielectric layer 31. The bottom of the gate metal 6 is in contact with the gallium nitride substrate and is insulated from the source ohmic electrode 21 and the drain ohmic electrode 22.
[0080] like Figure 1 , which is a schematic structural diagram after the gate metal 6 , the lower field plate 71 and the upper field plate 72 are prepared and formed.
[0081] Step S190 of this embodiment specifically includes the following sub-steps.
[0082] In step S191 , a field plate metal is deposited to fill the gate contact hole and cover the upper surfaces of the lower dielectric layer 51 and the upper dielectric layer 52 .
[0083] Step S192, etching the field plate metal. Figure 1 , which is a schematic diagram of a double-layer field plate structure formed after etching. The field plate metal filled in the gate contact hole forms the gate metal 6, a lower field plate 71 is formed above the lower dielectric layer 51, and an upper field plate 72 is formed above the upper dielectric layer 52. The lower field plate 71 and the upper dielectric layer 52 are arranged horizontally, and the upper field plate 72 is connected to the lower field plate 71 to form a double-layer field plate structure. In this embodiment, the gate metal 6 is also connected to the lower field plate 71. The lower field plate 71 is located above the primary field plate 41, and the projection of the primary field plate 41 on the horizontal plane is located within the projection of the lower field plate 71 on the horizontal plane.
[0084] Since there is no gap at the connection between the upper dielectric layer 52 and the lower dielectric layer 51, the structural damage caused by etching is small, and the field plate has a better shape forming effect at this position, thereby reducing the local concentration effect of the electric field and improving the reliability of the device.
[0085] The primary field plate 41, the lower field plate 71, and the upper field plate 72 form a multi-layer field plate structure. The upper field plate 72 is offset from the primary field plate 41, meaning their horizontal projections do not overlap. At least a portion of the lower field plate 71 is offset from the primary field plate 41, meaning their horizontal projections do not overlap. This allows each field plate to effectively exert its electric field effect at its corresponding location, effectively regulating the electric field distribution.
[0086] In Example 1 of the present invention, a primary field plate 41 is disposed between the lower dielectric layer 51 and the second dielectric layer 32. The top of the gate metal 6 extends above the lower dielectric layer 51. In this embodiment, the bottom of the gate metal 6 penetrates the first dielectric layer 31 and contacts the silicon nitride layer 14 of the gallium nitride substrate. However, in other embodiments, the bottom of the gate metal 6 may not penetrate the first dielectric layer 31, but may directly contact the first dielectric layer 31. The gate metal 6 may be insulated from the source ohmic electrode 21 and the drain ohmic electrode 22 by the first dielectric layer 31 or the silicon nitride layer 14.
[0087] The source ohmic electrode 21 and the drain ohmic electrode 22 are both located below the second dielectric layer 32 and extend through the first dielectric layer 31. The bottoms of the source ohmic electrode 21 and the drain ohmic electrode 22 are connected to the aluminum gallium nitride layer of the gallium nitride substrate and are insulated from the gate metal 6. The source ohmic electrode 21 and the drain ohmic electrode 22 are preferably a stack of titanium and aluminum metals.
[0088] In this embodiment, in the horizontal direction, the primary field plate 41 is located between the upper field plate 72 and the gate metal 6, and the gate metal 6 is connected to the lower field plate 71, and the lower field plate 71 is connected to the upper field plate 72. The gate metal 6, the lower field plate 71, and the upper field plate 72 can be manufactured simultaneously in the same step to simplify the manufacturing process and improve manufacturing efficiency.
[0089] Example 2
[0090] The method for manufacturing a semiconductor device with a multi-layer field plate provided in this embodiment has a field plate structure of a gallium nitride power device as shown in FIG. Figure 3 As shown, it is a further improvement on the basis of Example 1. The difference from Example 1 is that a protective dielectric layer 8 is provided on the upper dielectric layer 52 and the lower dielectric layer 51, and the protective dielectric layer 8 is located below the lower field plate 71 and the upper field plate; the top of the gate metal 6 extends above the protective dielectric layer 8.
[0091] The manufacturing process is similar to that of Example 1. Before etching the gate region to form the gate setting through hole 60 in step S180, a protective dielectric layer 8 is formed on the upper dielectric layer 52 and the lower dielectric layer 51. The protective dielectric layer 8 is a dielectric layer with good density, preferably higher than that of the lower dielectric layer 51 and the upper dielectric layer 52. The protective dielectric layer 8 can cover the etched damaged area, thereby preventing the etched damaged area from affecting the shape and structure of the field plate, thereby improving device reliability.
[0092] After depositing the protective dielectric layer 8 , etching is performed to form a gate setting through hole 60 , and after depositing the metal layer, the top of the gate metal 6 is extended to the protective dielectric layer 8 .
[0093] Example 3
[0094] In the method for manufacturing the field plate structure of the gallium nitride power device provided in this embodiment, the field plate structure of the gallium nitride power device prepared is as follows: Figure 4 As shown, it is a further improvement on the basis of Example 1. The difference from Example 1 is that the lower field plate 71 is separated from the gate metal 6.
[0095] The manufacturing process is similar to that of Example 1. In step 190, gate metal 6 is deposited, and after etching to form gate metal 6, lower field plate 71, and upper field plate 72, lower field plate 71 is separated from gate metal 6. By isolating lower field plate 71 from gate metal 6, cracking caused by stress when connecting large metal pieces is reduced, thereby ensuring device reliability.
[0096] In this embodiment, since a primary field plate 41 is prepared on the device, the partition position between the lower field plate 71 and the gate metal 6 is located above the primary field plate 41, and the lower field plate 71 and the gate metal 6 are respectively located on both sides of the primary field plate 41; so as to reduce the mutual influence of the electric field between the lower field plate 71 and the primary field plate 41, and at the same time reduce the stress problem between different field plates.
[0097] The width W of the overlapping area between the lower field plate 71 and the primary field plate 41 projected on the horizontal plane is less than 1 / 5 of the width of the primary field plate 41. This relatively small width of the overlapping area can effectively reduce the stress of the lower field plate 71 at the location of the base field plate 4, reduce the mutual influence of the electric fields between the two, and facilitate the regulation of the electric field. It can be understood that the width direction referred to in each embodiment of the present invention is the left and right horizontal direction in the figure.
[0098] In the aforementioned embodiment, the lower field plate 71 is connected to the upper field plate 72 to reduce the problem of unstable electric fields at the adjacent edges of the two. Of course, in other embodiments, the upper field plate 72 and the lower field plate 71 can also be separated by etching, that is, the two are separated and not connected, and arranged in a horizontally spaced manner to avoid excessive stress problems caused by the large area of connection between the two.
[0099] Example 4
[0100] like Figure 5 As shown, the gallium nitride power device with a multi-layer field plate provided in this embodiment includes a gallium nitride substrate, a first dielectric layer 31 , a second dielectric layer 32 , a third dielectric layer 33 , a lower dielectric layer 51 , an upper dielectric layer 52 and a gate metal 6 .
[0101] The first dielectric layer 31 is disposed on the gallium nitride substrate; the first dielectric layer 31 includes a source ohmic contact hole 201 and a drain ohmic contact hole 202 . A source ohmic electrode 21 is disposed in the source ohmic contact hole 201 , and a drain ohmic electrode 22 is disposed in the drain ohmic contact hole 202 .
[0102] The second dielectric layer 32 is disposed on the first dielectric layer 31 , the source ohmic electrode 21 , and the drain ohmic electrode 22 .
[0103] The third dielectric layer 33 is disposed on the second dielectric layer 32 , and a primary field plate 41 is disposed between the third dielectric layer 33 and the second dielectric layer 32 ; the third dielectric layer 33 is provided with a gate arrangement through hole 60 .
[0104] The lower dielectric layer 51 is arranged on the third dielectric layer 33; a secondary field plate 42 is arranged between the lower dielectric layer 51 and the first dielectric layer 31; a lower field plate region and an upper dielectric region are arranged on the upper surface of the lower dielectric layer 51; a lower field plate 71 is arranged in the lower field plate region.
[0105] The upper dielectric layer 52 is positioned in the upper dielectric region. Under the same etching conditions, the etching rate of the lower dielectric layer 51 is lower than that of the upper dielectric layer 52. An upper field plate is disposed on the upper dielectric layer 52. Preferably, the etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same etching conditions is greater than 10:1.
[0106] The gate metal 6 is disposed in the gate through hole 60, with its top extending between the third dielectric layer 33 and the lower dielectric layer 51. The gate metal 6 is connected to the secondary field plate 42, and the two can be prepared and formed at the same time.
[0107] The gallium nitride power device provided in this embodiment can be manufactured by the following manufacturing method.
[0108] Step S410 : providing a gallium nitride substrate, and depositing a first dielectric layer 31 on the gallium nitride substrate 1 .
[0109] In step S420 , the first dielectric layer 31 and the gallium nitride substrate 1 in the source region and the drain region are etched to form a source ohmic contact hole 201 in the source region and a drain ohmic contact hole 202 in the drain region.
[0110] In step S430 , an ohmic metal layer is deposited in the source ohmic contact hole 201 , the drain ohmic contact hole 202 and on the first dielectric layer 31 , and the ohmic metal layer is etched to form a source ohmic electrode 21 and a drain ohmic electrode 22 .
[0111] In step S440 , a second dielectric layer 32 is deposited on the first dielectric layer 31 and the source ohmic electrode 21 and the drain ohmic electrode 22 .
[0112] Step S450 , manufacturing a primary field plate 41 on the second dielectric layer 32 .
[0113] The aforementioned steps S410 to S450 may be identical to the specific contents of steps S110 to S150 in Example 1, and will not be repeated here.
[0114] Step S460 , depositing a third dielectric layer 33 on the second dielectric layer 32 and the primary field plate 41 .
[0115] In step S470, etching is performed in the gate region to form a gate setting through hole 60 in the third dielectric layer 33. At the location of the gate setting through hole 60, the second dielectric layer 32 and the first dielectric layer 31 are further etched to form a gate contact hole so that the gate metal 6 can contact the gallium nitride substrate.
[0116] Step S480 , forming a gate metal 6 at the gate setting through hole 60 , and manufacturing a secondary field plate 42 on the third dielectric layer 33 .
[0117] In this step, after the metal layer is deposited, the gate metal 6 and the secondary field plate 42 can be simultaneously prepared by etching. In this embodiment, the secondary field plate 42 and the gate 6 can be simultaneously prepared by one metal deposition and etching, which simplifies the preparation process and improves the preparation efficiency. In this embodiment, the gate metal 6 is connected to the secondary field plate 42. Furthermore, the end of the secondary field plate 42 away from the gate metal 6 extends to the side of the primary field plate 41 away from the gate metal 6, so that the end of the secondary field plate 42 away from the gate metal 6 does not overlap with the projection of the primary field plate 41 in the horizontal plane, thereby allowing the secondary field plate 42 to better play the role of regulating the electric field.
[0118] In step S490, a lower dielectric layer 51 and an upper dielectric layer 52 are sequentially deposited on the gate metal 6, the secondary field plate 42, and the third dielectric layer 33. Under the same etching conditions, the etching rate of the lower dielectric layer 51 is lower than the etching rate of the upper dielectric layer 52, so that when the upper dielectric layer 52 is etched, the etching of the lower dielectric layer 51 is reduced. As a result, there is no need to set an additional etching barrier layer between the upper dielectric layer 52 and the lower dielectric layer 51 to prevent the lower dielectric layer 51 from being etched through, thereby reducing the manufacturing process and saving preparation time. At the same time, it can avoid the generation of gaps between the two dielectric layers, thereby reducing the local concentration effect of the electric field caused by etching damage, and improving the reliability of the device.
[0119] Furthermore, preferably, the etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same etching conditions is greater than 10:1, so that the etching rate of the lower dielectric layer 51 is much lower than the etching rate of the upper dielectric layer 52. The upper dielectric layer 52 and the lower dielectric layer 51 can be made of homogeneous or heterogeneous materials. Here, a suitable dielectric material can be selected to achieve the above-mentioned etching rate ratio under the same conditions.
[0120] In step S491 , etching is performed on the upper dielectric layer 52 except the upper dielectric region to form an upper field plate region on the upper dielectric layer 52 and a lower field plate region on the lower dielectric layer 51 .
[0121] Step S492: Form a lower field plate 71 on the lower field plate region, and form an upper field plate 72 on the upper field plate region. In this step, field plate metal is first deposited, covering the upper surfaces of the lower dielectric layer 51 and the remaining upper dielectric layer 52. Then, the field plate metal is etched to form the lower field plate 71 above the lower dielectric layer 51 and the upper field plate 72 above the upper dielectric layer 52. The upper field plate 72 is connected to the lower field plate 71 to form a double-layer field plate structure.
[0122] In this embodiment, the upper field plate 72 is staggered with the primary field plate 41 and the secondary field plate 42 , that is, the projections of the three on the horizontal plane do not overlap, so that the upper field plate 72 can better play the role of the electric field at the corresponding position.
[0123] The primary field plate 41, the secondary field plate 42, the lower field plate 71 and the upper field plate 72 form a four-layer field plate structure. In other embodiments, the number of field plates can be increased, and the number of dielectric layers can be increased to achieve a multi-layer field plate structure.
[0124] The bottom of the gate metal 6 of the gallium nitride power device with a multi-layer field plate provided in this embodiment 4 passes through the first dielectric layer 31 and contacts the silicon nitride layer 14 of the gallium nitride substrate 1. Here, in other embodiments, the bottom of the gate metal 6 may not pass through the first dielectric layer 31, and the two may be in direct contact. The gate metal 6 can be insulated from the ohmic electrode 2 by the first dielectric layer 31 or the silicon nitride layer. In the horizontal direction, the primary field plate 41 and the secondary field plate 42 are both located between the upper field plate 72 and the gate metal 6, and the gate metal 6 is connected to the secondary field plate 42, and the lower field plate 71 is connected to the upper field plate 72. The gate metal 6 is connected to the secondary field plate 42 so that the two can be manufactured simultaneously in the same step. The lower field plate 71 and the upper field plate 72 are manufactured simultaneously in the same step to simplify the preparation process and improve preparation efficiency.
[0125] Example 5
[0126] like Figure 6 As shown, this embodiment provides a gallium nitride power device with a multi-layer field plate, which includes a gallium nitride substrate, a first dielectric layer 31 , a second dielectric layer 32 , a third dielectric layer 33 , a lower dielectric layer 51 , an upper dielectric layer 52 and a gate metal 6 .
[0127] The first dielectric layer 31 is disposed on the gallium nitride substrate; the first dielectric layer 31 includes a source ohmic contact hole 201 and a drain ohmic contact hole 202 . A source ohmic electrode 21 is disposed in the source ohmic contact hole 201 , and a drain ohmic electrode 22 is disposed in the drain ohmic contact hole 202 .
[0128] The second dielectric layer 32 is disposed on the first dielectric layer 31 , the source ohmic electrode 21 , and the drain ohmic electrode 22 .
[0129] The third dielectric layer 33 is disposed on the second dielectric layer 32 , and a primary field plate 41 is disposed between the third dielectric layer 33 and the second dielectric layer 32 .
[0130] The lower dielectric layer 51 is arranged on the third dielectric layer 33; a secondary field plate 42 is arranged between the lower dielectric layer 51 and the third dielectric layer 33; a lower field plate region and an upper dielectric region are arranged on the upper surface of the lower dielectric layer 51; a gate setting through hole 60 is provided in the lower dielectric layer 51; and a lower field plate 71 is provided in the lower field plate region.
[0131] The upper dielectric layer 52 is positioned in the upper dielectric region; under the same etching conditions, the etching rate of the lower dielectric layer 51 is lower than that of the upper dielectric layer 52; an upper field plate is provided on the upper dielectric layer 52. The etching rate of the lower dielectric layer 51 is lower than that of the upper dielectric layer 52, so that when the upper dielectric layer 52 is etched, the etching rate of the lower dielectric layer 51 is reduced. Therefore, there is no need to provide an additional etch barrier layer between the upper dielectric layer 52 and the lower dielectric layer 51 to prevent the lower dielectric layer 51 from being etched through, thereby simplifying the manufacturing process and saving preparation time. At the same time, the formation of a gap between the two dielectric layers can be avoided, thereby reducing the local concentration effect of the electric field caused by etching damage and improving the reliability of the device.
[0132] The gate metal 6 is disposed in the gate through hole 60, with its top extending above the lower dielectric layer 51. The gate metal 6, the lower field plate 71 and the upper field plate 72 can be fabricated simultaneously.
[0133] The gallium nitride power device provided in this embodiment can be manufactured by the following manufacturing method.
[0134] In step S510 , a gallium nitride substrate 1 is provided, and a first dielectric layer 31 is deposited on the gallium nitride substrate 1 .
[0135] In step S520 , the first dielectric layer 31 and the gallium nitride substrate 1 in the source region and the drain region are etched to form a source ohmic contact hole 201 in the source region and a drain ohmic contact hole 202 in the drain region.
[0136] In step S530 , an ohmic metal layer is deposited in the source ohmic contact hole 201 , the drain ohmic contact hole 202 and on the first dielectric layer 31 , and the ohmic metal layer is etched to form a source ohmic electrode 21 and a drain ohmic electrode 22 .
[0137] In step S540 , a second dielectric layer 32 is deposited on the first dielectric layer 31 and the source ohmic electrode 21 and the drain ohmic electrode 22 .
[0138] Step S550 , manufacturing a primary field plate 41 on the second dielectric layer 32 .
[0139] The aforementioned steps S510 to S550 may be identical to the specific contents of steps S110 to S150 in Example 1, and will not be repeated here.
[0140] Step S560 , depositing a third dielectric layer 33 on the second dielectric layer 32 and the primary field plate 41 .
[0141] Step S570 , manufacturing a secondary field plate 42 on the third dielectric layer 33 .
[0142] In step S580, a lower dielectric layer 51 and an upper dielectric layer 52 are sequentially deposited on the third dielectric layer 33 and the secondary field plate 42. Preferably, the etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same etching conditions is greater than 10:1, so that the etching rate of the lower dielectric layer 51 is much lower than the etching rate of the upper dielectric layer 52. The upper dielectric layer 52 and the lower dielectric layer 51 can be made of homogeneous or heterogeneous materials. Here, a suitable dielectric material can be selected to achieve the above-mentioned etching rate ratio between the two layers under the same conditions.
[0143] In step S590 , etching is performed on the upper dielectric layer 52 except the upper dielectric region to form an upper field plate region on the upper dielectric layer 52 and a lower field plate region on the lower dielectric layer 51 .
[0144] When etching the upper dielectric layer 52, the upper dielectric layer 52 located in the upper dielectric area is retained, and the rest of the upper dielectric layer 52 is completely etched away. Due to the large difference in etching rates between the upper and lower dielectric layers, after the upper dielectric layer 52 outside the upper dielectric area is completely etched away, only a small portion of the lower dielectric layer 51 is etched away or is almost not etched, ensuring that the thickness of the lower dielectric layer 51 meets the predetermined requirements. Therefore, there is no need to set an etch stop layer between the two dielectric layers, and the lower dielectric layer 51 and the upper dielectric layer 52 can be directly connected.
[0145] In step S591 , an etching operation is performed in the gate region to form a gate setting through hole 60 .
[0146] At the location of the gate through hole 60 , the third dielectric layer 33 , the second dielectric layer 32 , and the first dielectric layer 31 are further etched to form a gate contact hole, the depth of which reaches the silicon nitride layer 14 of the gallium nitride substrate 1 , so that the prepared gate metal 6 can contact the silicon nitride layer 14 of the gallium nitride substrate 1 .
[0147] In step S592, gate metal 6 is formed at the gate setting through hole 60, a lower field plate 71 is formed on the lower field plate region, and an upper field plate 72 is formed on the upper field plate region. This step may be the same as step S190 of embodiment 1 and will not be repeated here.
[0148] In this step, after the metal layer is deposited, etching can be performed to simultaneously form the gate metal 6, the lower field plate 71, and the upper field plate 72. This embodiment can simultaneously form the gate metal 6, the lower field plate 71, and the upper field plate 72 through a single metal deposition and etching process, thereby simplifying the preparation process and improving preparation efficiency.
[0149] In this embodiment, the upper field plate 72 is staggered with the primary field plate 41 and the secondary field plate 42 , that is, the projections of the three on the horizontal plane do not overlap, so that the upper field plate 72 can better play the role of the electric field at the corresponding position.
[0150] The primary field plate 41, the secondary field plate 42, the lower field plate 71 and the upper field plate 72 form a four-layer field plate structure. In other embodiments, the number of field plates can be increased, and the number of dielectric layers can be increased to achieve a multi-layer field plate structure.
[0151] In the gallium nitride power device with a multi-layer field plate provided in Example 5, the top of the gate metal 6 extends above the lower dielectric layer 51 and is connected to the lower field plate 71. The lower field plate 71 is connected to the upper field plate 72. The gate metal 6, the lower field plate 71, and the upper field plate 72 can be fabricated simultaneously in the same step, simplifying the fabrication process and improving fabrication efficiency.
[0152] Example 6
[0153] like Figure 7 , which is a gallium nitride power device with a multi-layer field plate provided in this embodiment. Embodiment 6 is a further improvement on the aforementioned embodiment 4. Specifically, a protective dielectric layer 8 is provided on the upper dielectric layer 52 and the lower dielectric layer 51. The protective dielectric layer 8 is located below the lower field plate 71 and the upper field plate.
[0154] Before forming the lower field plate 71 on the lower field plate region and the upper field plate 72 on the upper field plate region in step S492, and after step S491, a protective dielectric layer 8 is formed on the lower dielectric layer 51 and the upper dielectric layer 52. Protective dielectric layer 8 is a highly dense dielectric layer, preferably having a higher density than that of the lower dielectric layer 51 and the upper dielectric layer 52. Protective dielectric layer 8 can cover the etched damaged areas, thereby preventing the etched damaged areas from affecting the shape and structure of the field plates and improving device reliability. The method and structure for depositing protective dielectric layer 8 are also applicable to Examples 3 and 5.
[0155] Example 7
[0156] like Figure 8 As shown, this embodiment provides a gallium nitride power device with a multi-layer field plate. Embodiment 7 is a further improvement on the aforementioned embodiment 4. Its main difference is that the secondary field plate 42 is separated from the gate field plate to isolate the two, thereby reducing cracking caused by stress problems when connecting large metal pieces together, thereby ensuring device reliability.
[0157] The production process mainly consists of steps S480 and S492, which are specifically as follows.
[0158] Step S480 , forming a gate metal 6 on the gate setting through hole 60 , and manufacturing a secondary field plate 42 on the third dielectric layer 33 .
[0159] In this step, after the metal layer is deposited, the gate metal 6 and the secondary field plate 42 are separated during etching to isolate them. This isolation reduces stress-induced cracking caused by connecting large pieces of metal together, ensuring device reliability. The gate metal 6 and the secondary field plate 42 are isolated above the primary field plate 41. The gate metal 6 and the secondary field plate 42 are located on either side of the primary field plate 41 in the width direction, effectively avoiding stress issues caused by connecting large pieces of metal.
[0160] In step S492, a lower field plate 71 is formed on the lower field plate region, and an upper field plate 72 is formed on the upper field plate region. In this step, when etching is performed after depositing the metal layer, the lower field plate 71 only partially overlaps with the secondary field plate 42 after etching. The width of the overlapping area between the projections of the lower field plate 71 and the secondary field plate 42 on the horizontal plane is less than 1 / 5 of the width of the secondary field plate 42. The relatively small width of the overlapping area facilitates the regulation of the electric field distribution of the lower field plate 71 and the secondary field plate 42, and can reduce the stress of the lower field plate 71 at the position of the primary field plate 41.
[0161] In the gallium nitride power device with a multi-layer field plate provided by the present invention, the etching rate ratio of the upper dielectric layer 52 to the lower dielectric layer 51 under the same conditions is greater than 10:1. Due to the large difference in etching rates between the upper and lower dielectric layers, after the upper dielectric layer 52 outside the upper dielectric region is completely etched away, only a small portion of the lower dielectric layer 51 is etched away. This eliminates the need for an etch stop layer between the two dielectric layers, reduces the manufacturing process, and saves preparation time. At the same time, it can avoid the formation of a gap between the two dielectric layers. The field plate has a better shape forming effect at this position, thereby reducing the local concentration effect of the electric field caused by etching damage and improving the reliability of the device.
[0162] The lower dielectric layer 51 and the upper dielectric layer 52 may be covered with a protective dielectric layer 8. The protective dielectric layer 8 is a dielectric layer with good density, preferably higher than that of the lower dielectric layer 51 and the upper dielectric layer 52. The protective dielectric layer 8 can cover the etched damaged area, thereby preventing the etched damaged area from affecting the shape and structure of the field plate, thereby improving device reliability.
[0163] The gate metal 6 can be prepared and formed simultaneously with the secondary field plate 42 or the lower field plate 71 to simplify the preparation process.
[0164] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.
Claims
1. A gallium nitride power device with a multi-layer field plate, characterized in that: include: GaN substrate; A first dielectric layer is provided on the gallium nitride substrate; The first dielectric layer includes a source ohmic contact hole and a drain ohmic contact hole, wherein a source ohmic electrode is disposed in the source ohmic contact hole, and wherein a drain ohmic electrode is disposed in the drain ohmic contact hole; a second dielectric layer, disposed on the first dielectric layer, the source ohmic electrode, and the drain ohmic electrode; A lower dielectric layer is provided on the second dielectric layer; a primary field plate is provided between the lower dielectric layer and the second dielectric layer; a lower field plate region and an upper dielectric region are provided on the upper surface of the lower dielectric layer; the lower dielectric layer is provided with a gate setting through hole; a lower field plate is provided in the lower field plate region; an upper dielectric layer, directly connected to the lower dielectric layer and located in the upper dielectric region; under the same etching conditions, an etching rate of the lower dielectric layer is lower than an etching rate of the upper dielectric layer; An upper field plate is provided on the upper dielectric layer; and The gate metal is arranged in the gate setting through hole, and the top of the gate metal extends to the bottom dielectric layer.
2. The gallium nitride power device with a multi-layer field plate according to claim 1, characterized in that: The lower field plate is connected to the upper field plate.
3. The gallium nitride power device with a multi-layer field plate according to claim 1 or 2, characterized in that: The lower field plate is connected to the gate metal, or the lower field plate is separated from the gate metal.
4. The gallium nitride power device with a multi-layer field plate according to claim 1, characterized in that: The etching rate ratio of the upper dielectric layer and the lower dielectric layer under the same etching conditions is greater than 10:
1.
5. The gallium nitride power device with a multi-layer field plate according to claim 1, characterized in that: A protective dielectric layer is provided on the upper dielectric layer and the lower dielectric layer, and the protective dielectric layer is located below the lower field plate and the upper field plate; the top of the gate metal extends above the protective dielectric layer.
6. The gallium nitride power device with a multi-layer field plate according to claim 1, characterized in that: The gate metal penetrates the second dielectric layer and the first dielectric layer. The bottom of the gate metal is connected to the gallium nitride substrate and is insulated from the source ohmic electrode and the drain ohmic electrode.
7. A gallium nitride power device with a multilayer field plate, characterized in that: include: GaN substrate; A first dielectric layer is provided on the gallium nitride substrate; The first dielectric layer includes a source ohmic contact hole and a drain ohmic contact hole, wherein a source ohmic electrode is disposed in the source ohmic contact hole, and wherein a drain ohmic electrode is disposed in the drain ohmic contact hole; a second dielectric layer, disposed on the first dielectric layer, the source ohmic electrode, and the drain ohmic electrode; A third dielectric layer is provided on the second dielectric layer, a primary field plate is provided between the third dielectric layer and the second dielectric layer; the third dielectric layer is provided with a gate setting through hole; A lower dielectric layer is provided on the third dielectric layer; a secondary field plate is provided between the lower dielectric layer and the first dielectric layer; and a lower field plate region and an upper dielectric region are provided on the upper surface of the lower dielectric layer; A lower-level field plate is provided in the lower-level field plate region; an upper dielectric layer, disposed at the location of the upper dielectric region; under the same etching conditions, an etching rate of the lower dielectric layer is lower than an etching rate of the upper dielectric layer; An upper field plate is provided on the upper dielectric layer; and A gate metal is disposed in the gate setting through hole, and a top portion thereof extends between the third dielectric layer and the lower dielectric layer.
8. The gallium nitride power device with a multi-layer field plate according to claim 7, characterized in that: The secondary field plate is connected to the gate metal, or the secondary field plate is separated from the gate metal.
9. The gallium nitride power device with a multi-layer field plate according to claim 7 or 8, characterized in that: A protective dielectric layer is provided on the upper dielectric layer and the lower dielectric layer, and the protective dielectric layer is located below the lower field plate and the upper field plate.
10. A gallium nitride power device with a multi-layer field plate, characterized in that: include: GaN substrate; A first dielectric layer is provided on the gallium nitride substrate; The first dielectric layer includes a source ohmic contact hole and a drain ohmic contact hole, wherein a source ohmic electrode is disposed in the source ohmic contact hole, and wherein a drain ohmic electrode is disposed in the drain ohmic contact hole; a second dielectric layer, disposed on the first dielectric layer, the source ohmic electrode, and the drain ohmic electrode; a third dielectric layer, disposed on the second dielectric layer, with a primary field plate disposed between the third dielectric layer and the second dielectric layer; a lower dielectric layer, disposed on the third dielectric layer; A secondary field plate is provided between the lower dielectric layer and the third dielectric layer; a lower field plate region and an upper dielectric region are provided on the upper surface of the lower dielectric layer; a gate setting through hole is provided in the lower dielectric layer; a lower field plate is provided in the lower field plate region; an upper dielectric layer, disposed at the location of the upper dielectric region; under the same etching conditions, an etching rate of the lower dielectric layer is lower than an etching rate of the upper dielectric layer; An upper field plate is provided on the upper dielectric layer; and The gate metal is arranged in the gate setting through hole, and the top of the gate metal extends above the lower dielectric layer.