Electronic component carrier tape
By setting a gate residue clearance area with increased width, an inclined surface, and a boss structure in the second area of the carrier cavity, the problems of material jamming and insufficient limiting caused by gate residue after carrier tape winding are solved, and the stability and safety of components are achieved.
Patent Information
- Application Number
- CN202422699267.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-05
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2034-11-05
AI Technical Summary
After winding, existing electronic component carrier tapes are prone to material jamming when the gate residue is large, and cannot effectively limit the position when the gate residue is small, causing the components to shift and shake.
A gate residue clearance area with increased width is set in the second area of the carrier cavity to accommodate gate residues of different degrees, avoid material jamming, and effectively limit the components through structures such as inclined surfaces and bosses.
It effectively avoids the problem of material jamming caused by excessive gate residue, and at the same time effectively limits the components with smaller gate residue to prevent deviation and shaking, thereby improving the stability of the components.
Smart Images
Figure CN223396703U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductor packaging, in particular to an electronic component carrier tape. Background Art
[0002] Carrier tape is a strip-shaped product used in the field of electronic packaging. The carrier cavity for loading electronic components is formed on the carrier tape. By sealing the cover tape on top of the carrier tape, a closed package is formed to protect the electronic components in the carrier cavity, avoid contamination and reduce loss.
[0003] To save space, carrier tape is typically wound onto a reel. Electronic components with large gate residues placed on the tape can become stuck when placed on the tape, and there's a risk of the nozzle failing to pick them up during pickup. Electronic components with small gate residues can shift and wobble within the tape, making them susceptible to damage. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide an electronic component carrier that is compatible with electronic components with different degrees of gate residues, and can avoid the defects of material jamming caused by excessive gate residues and the inability to effectively limit electronic components caused by small gate residues.
[0005] In order to solve the above problems, the utility model provides an electronic component carrier, including a main body, a carrier cavity on the surface of the main body, in the height direction of the carrier cavity, the carrier cavity is divided into a first area and a second area located on the first area, in the width direction of the carrier cavity, in the second area, partial areas of the opposite side walls of the carrier cavity protrude away from the carrier cavity, forming a gate residual clearance area.
[0006] In one embodiment, the gate residue clearance zone is only located in the second region, and the width of the carrier cavity in the first region is smaller than the width of the carrier cavity in the gate residue clearance zone.
[0007] In one embodiment, in the length direction of the carrier cavity, the second area is divided into the gate residue clearance area and the non-gate residue clearance area, and the width of the carrier cavity in the non-gate residue clearance area is smaller than the width of the carrier cavity in the gate residue clearance area.
[0008] In one embodiment, in the height direction of the carrier cavity, the gate residue clearance area extends from the top of the carrier cavity to a part of or the entire area of the first region.
[0009] In one embodiment, the sidewall surface in the first region is an inclined surface, and / or the sidewall surface in the second region is an inclined surface.
[0010] In one embodiment, the carrier tape further includes a boss disposed on the side wall, and the boss is located in the first area.
[0011] In one embodiment, the bosses on the two opposite side walls are flush with each other.
[0012] In one embodiment, the bosses on the two opposite side walls are staggered.
[0013] In one embodiment, the boss is arranged below the gate residue clearance area.
[0014] In one embodiment, the boss is disposed at the junction of the side wall and the bottom of the carrier cavity.
[0015] In one embodiment, a portion of the bottom of the carrier cavity protrudes into the carrier cavity to form a recessed area on the bottom surface of the main body.
[0016] In one embodiment, in the recessed area, an opening passes through the main body.
[0017] In one embodiment, the carrier tape further includes a cover tape, and the cover tape is capable of covering the top surface of the carrier cavity to close the carrier cavity.
[0018] The electronic component carrier provided by the embodiment of the present invention is provided with a gate residue clearance area with an increased width in the second area (i.e., the top area) of the carrier cavity, which is used to accommodate the gate residues of the electronic components. The gate residues are prevented from being too large and contacting or even pressing against the side walls of the carrier cavity without increasing the width of the carrier cavity, thereby avoiding the defect of material jamming; and, since the width of other areas outside the gate residue clearance area of the carrier cavity is not increased, it can effectively limit the electronic components with smaller gate residues, thereby avoiding the defects of electronic components shifting and shaking in the carrier cavity. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following is a brief introduction to the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts.
[0020] Figure 1 This is a cross-sectional diagram of an electronic component with a large gate residue placed in a carrier tape;
[0021] Figure 2 This is a cross-sectional diagram of an electronic component with a small gate residue placed in a carrier tape;
[0022] Figure 3 It is a top view schematic diagram of electronic components;
[0023] Figure 4 This is a top view of an electronic component carrier provided by one embodiment of the present utility model;
[0024] Figure 5 It is along Figure 4 Schematic diagram of the cross section along line A-A1;
[0025] Figure 6 It is along Figure 4 Schematic diagram of the cross section of line B-B1;
[0026] Figure 7 It is along Figure 4 Schematic diagram of the cross section along line C-C1;
[0027] Figure 8 The electronic components are placed on the rear edge of the electronic component carrier provided by an embodiment of the present invention. Figure 4 Schematic diagram of the cross section along line A-A1;
[0028] Figure 9 Another embodiment of the present invention provides an electronic component carrier tape. Figure 4 Schematic diagram of the cross section along line A-A1;
[0029] Figure 10 The electronic components are placed on the rear edge of the electronic component carrier provided in another embodiment of the present invention. Figure 4 Schematic diagram of the cross section along line A-A1. DETAILED DESCRIPTION
[0030] The specific implementation of the electronic component carrier provided by the present invention is described in detail below with reference to the accompanying drawings.
[0031] Figure 1 This is a cross-sectional view of an electronic component 100 with a large gate residue placed in a carrier tape. Figure 2 This is a cross-sectional view of an electronic component 100 with a small gate residue placed in a carrier tape. Figure 3 is a schematic top view of the electronic component 100, such as Figure 1 、 Figure 2 and Figure 3As shown, the electronic component 100 includes a top area 101, a gate residue area 102, and a bottom area 103, which are arranged in sequence. The top area 101 is arranged above the gate residue area 102, and the bottom area 103 is arranged below the gate residue area 102. Part of the edge of the gate residue area 102 has a gate residue 110. The width of the electronic component 100 is the largest in the gate residue area 102, so different degrees of gate residue 110 will result in different maximum widths of the electronic component 100. Figure 1 As shown, if the gate residue 110 is large, in the gate residue area 102 of the electronic component 100, the periphery of the electronic component 100 contacts the inner wall of the carrier cavity 200 and even presses against the inner wall of the carrier cavity 200. Then, after the carrier tape is wrapped, the inner wall of the carrier cavity 200 is deformed, and the material is stuck. When the terminal sucks, there is a risk that the suction nozzle will not be able to suck it up. In order to solve the problem of material sticking, some carrier tapes increase the width of the carrier cavity 200. However, the increase in the width of the carrier cavity 200 will cause the electronic component 100 with a smaller gate residue 110 to be unable to be effectively limited. Specifically, Figure 2 As shown, the width of the carrier cavity 200 is relatively large, and the gate residue 110 of the electronic component 100 is relatively small. In the gate residue area 102 of the electronic component 100, the outer periphery of the electronic component 100 does not contact the inner wall of the carrier cavity 200, and the distance between the outer periphery of the electronic component 100 and the inner wall of the carrier cavity 200 is relatively large, and the electronic component 100 cannot be effectively limited. The electronic component 100 is offset and shakes greatly in the carrier cavity 200, and is easily damaged.
[0032] In view of the defects of the above-mentioned carrier, an embodiment of the present invention provides an electronic component carrier, which is compatible with electronic components with different degrees of gate residues, and can avoid the defects of excessive gate residues causing material jamming and small gate residues causing inability to effectively limit electronic components.
[0033] Figure 4 This is a top view of an electronic component carrier provided by an embodiment of the present invention. Figure 5 It is along Figure 4 Schematic diagram of the cross section of line A-A1, Figure 6 It is along Figure 4 Schematic diagram of the cross section of line B-B1, Figure 7 It is along Figure 4 Schematic diagram of the cross section of line C-C1, Figure 8 The electronic component 500 is placed on the rear edge of the electronic component carrier provided in one embodiment of the present invention. Figure 4 For a schematic diagram of the cross section of line A-A1, please refer to Figures 4 to 8The carrier tape includes a main body 400, and a carrier cavity 410 is provided on the surface of the main body 400. In the height direction of the carrier cavity 410, the carrier cavity 410 is divided into a first area 411 and a second area 412 located on the first area 411. In the width direction of the carrier cavity 410, in the second area 412, partial areas of the opposite side walls of the carrier cavity 410 protrude away from the carrier cavity 410, forming a gate residual clearance area 413.
[0034] The electronic component carrier provided by the embodiment of the present invention is provided with a gate residue clearance area 413 with an increased width in the second area 412 (i.e., the top area) of the carrier cavity 410, which is used to accommodate the gate residue 510 of the electronic component 500. There is no need to increase the width of the carrier cavity 410 to avoid the gate residue 510 being too large and contacting or even pressing against the side wall of the carrier cavity 410, thereby avoiding the defect of material jamming; and, since the width of other areas outside the gate residue clearance area 413 of the carrier cavity 410 is not increased, it can effectively limit the electronic component 500 with a smaller gate residue 510, thereby avoiding the defect of the electronic component 500 being offset or shaking greatly in the carrier cavity 410.
[0035] In this embodiment, the main body 400 has a plurality of carrier cavities 410 disposed on its surface. The plurality of carrier cavities 410 are spaced apart along a first direction D1, and each carrier cavity 410 extends along a second direction D2. The first direction D1 is perpendicular to the second direction D2. In other embodiments, the plurality of carrier cavities 410 are distributed in an array along both the first direction D1 and the second direction D2.
[0036] In the embodiment of the present invention, the first direction D1 is the width direction of the carrier cavity 410 , the second direction D2 is the length direction of the carrier cavity 410 , and the third direction D3 is perpendicular to the first direction D1 and the second direction D2 and is the height direction of the carrier cavity 410 .
[0037] In the height direction of the carrier cavity 410 (i.e., the third direction D3), the carrier cavity 410 is divided into a first area 411 and a second area 412 located on the first area 411, wherein the first area 411 is the bottom area of the carrier cavity 410, and the second area 412 is the top area of the carrier cavity 410.
[0038] In the width direction of the carrier cavity 410 (i.e., the first direction D1), portions of the two opposing side walls of the carrier cavity 410 in the second region 412 protrude away from the carrier cavity 410, forming the gate residue clearance area 413. After the electronic component 500 is placed in the carrier tape, the carrier cavity 410 accommodates the electronic component 500. The gate residue clearance area 413 provides space for the gate residue 510 of the electronic component 500, thereby preventing the gate residue 510 of the electronic component 500 from contacting or pressing against the side walls of the carrier cavity 410.
[0039] In this example, see Figure 5 The gate residue clearance area 413 is only located in the second area 412, and the width W1 of the carrier cavity 410 in the first area 411 is smaller than the width W2 of the carrier cavity 410 in the gate residue clearance area 413. The width W1 of the first area 411 is small and can be used to limit the bottom area of the electronic component 500, thereby achieving effective limitation of the electronic component 500.
[0040] In the second area 412, part of the two opposite side walls of the carrier cavity 410 protrudes in a direction away from the carrier cavity 410 to form a gate residue clearance area 413. That is, in the second area 412, the two opposite side walls of the carrier cavity 410 are not fully protruded, but only partially protruded to form the gate residue clearance area 413, and the other area is a non-gate residue clearance area, so that the gate residue 510 can be limited in the second direction, thereby achieving the limitation of the electronic component 500 in the second direction. Specifically, please refer to Figure 4 、 Figure 5 and Figure 6 In the length direction of the carrier cavity 410 (i.e., the second direction D2), the second area 412 is divided into the gate residue clearance area 413 and the non-gate residue clearance area 414. The width W3 of the carrier cavity 410 in the non-gate residue clearance area 414 is smaller than the width W2 of the carrier cavity 410 in the gate residue clearance area 413, thereby limiting the electronic component 500 in the second direction D2.
[0041] In some embodiments, see Figure 8After the electronic component 500 is placed in the carrier tape, the gate residue 510 of the electronic component 500 does not contact the bottom surface of the gate residue clearance area 413, and the gate residue 510 of the electronic component 500 is higher than the bottom surface of the gate residue clearance area 413. In other embodiments, after the electronic component 500 is placed in the carrier tape, the gate residue 510 of the electronic component 500 contacts the bottom surface of the gate residue clearance area 413, and the gate residue clearance area 413 is used to support the gate residue 510.
[0042] In some embodiments, the sidewall surface in the first region 411 is an inclined surface, and / or the sidewall surface in the second region 412 is an inclined surface, so as to guide the electronic component 500 to be smoothly placed into the carrier cavity 410. For example, see Figure 5 and Figure 6 In this embodiment, in the first region 411 and the second region 412 , the sidewall surfaces are both inclined surfaces.
[0043] In some embodiments, as Figure 7 As shown, a portion of the bottom of the carrier cavity 410 protrudes into the carrier cavity 410, forming a recessed area 415 on the bottom surface of the main body 400. The protruding area of the bottom of the carrier cavity 410, which protrudes into the carrier cavity 410, is used to support the bottom surface of the electronic component 500. For some electronic components 500 with pins on their edges, the pins can be placed in the non-protruding area of the bottom of the carrier cavity 410.
[0044] In some embodiments, an opening 416 extends through the body 400 within the recessed area 415. The opening 416 allows protruding parts from the bottom surface of the electronic component 500 to pass through. The opening 416 cooperates with the recessed area 415 to prevent the protruding parts from the bottom surface of the electronic component 500 from protruding beyond the bottom of the body 400, thereby preventing the carrier tape from wrapping around and damaging the electronic component 500.
[0045] In some embodiments, see Figure 8 The carrier tape further includes a cover tape 800 , which can cover the top surface of the carrier cavity 410 to close the carrier cavity 410 , thereby preventing the electronic component 500 from detaching from the carrier tape.
[0046] In the above embodiment, the gate residue clearance area 413 is only located in the second area 412, but in another embodiment, the gate residue clearance area 413 also extends to the first area 411, so as to be applicable to electronic components 500 with different gate residue 510 positions. Figure 9As shown, it is an electronic component carrier provided by another embodiment of the present invention. Figure 4 In the cross-sectional view of the line A-A1 in the height direction of the carrier cavity 410, the gate residue clearance area 413 extends from the top of the carrier cavity 410 to the entire area of the first area 411, that is, the gate residue clearance area 413 extends from the top to the bottom of the carrier cavity 410. In the height direction of the carrier cavity 410, there is no Figure 5 The steps shown are used to limit the position of the electronic components 500, thereby further enabling the carrier tape to be suitable for electronic components 500 with different gate residue 510 positions. Figure 9 The dotted line schematically illustrates the position of the non-gate remnant clearance area 414. In other embodiments, the gate remnant clearance area 413 may also extend from the top of the carrier cavity 410 to a portion of the first region 411. That is, the gate remnant clearance area 413 extends from the top to the bottom of the carrier cavity 410, but does not extend to the bottom.
[0047] In order to further limit the position of the electronic component 500, please refer to Figure 10 , which is the electronic component 500 placed on the rear edge of the electronic component carrier provided in another embodiment of the present invention Figure 4 The cross-sectional schematic diagram of the A-A1 line in the middle, in other embodiments, the carrier tape further includes a boss 900 arranged on the side wall, and the boss 900 is located in the first area 411. After the electronic component 500 is placed in the carrier cavity 410, the boss 900 is located between the electronic component 500 and the side wall, so as to avoid the electronic component 500 from shaking due to the gap between the electronic component 500 and the side wall being too large, thereby further realizing effective positioning of the electronic component 500.
[0048] In this embodiment, the boss 900 is disposed at the junction of the sidewall and the bottom of the carrier cavity 410. In other embodiments, the boss 900 may also be disposed on the sidewall above the bottom of the carrier cavity 410, that is, the boss 900 is not disposed on the bottom edge of the carrier cavity 410.
[0049] In this embodiment, if Figure 10 As shown, the bosses 900 located on the two opposite side walls are arranged flush, that is, the bosses 900 located on the two opposite side walls are located in the same horizontal plane; while in other embodiments, the bosses 900 located on the two opposite side walls are staggered, that is, the bosses 900 located on the two opposite side walls are not located in the same horizontal plane, so as to adapt to the different requirements of the electronic components 500.
[0050] In this embodiment, if Figure 10As shown, the boss 900 is arranged below the gate residue clearance area 413. In other embodiments, the boss 900 may also be arranged above the non-gate residue clearance area 414 (marked at Figure 4 ) below.
[0051] The electronic component carrier provided by the present invention is provided with a gate residue clearance area with an increased width in the second area (i.e., the top area) of the carrier cavity. This can prevent the gate residue from being too large and contacting or even pressing against the side wall of the carrier cavity without increasing the width of the carrier cavity, thereby avoiding the defect of material jamming; and it can effectively limit the electronic components with smaller gate residues, thereby avoiding the defects of electronic components being offset and shaking greatly in the carrier cavity.
[0052] It should be noted that the terms "including" and "having" and their variations used in the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence, unless the context clearly indicates otherwise. It should be understood that the terms used in this manner are interchangeable where appropriate. The term "one or more" may be used to describe a feature, structure, or characteristic in the singular, or in the plural, depending at least in part on the context. The term "based on" may be understood as not necessarily intended to express an exclusive set of factors, but may alternatively, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features therein may be combined with each other unless there is a conflict. In addition, in the above description, descriptions of well-known components and technologies have been omitted to avoid unnecessary confusion about the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from the other embodiments, and the same / similar parts between the embodiments can be referred to in detail.
[0053] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.
Claims
1. An electronic component carrier tape, characterized in that: The invention comprises a main body, wherein the surface of the main body has a carrier cavity. In the height direction of the carrier cavity, the carrier cavity is divided into a first area and a second area located on the first area. In the width direction of the carrier cavity, in the second area, partial areas of the opposite side walls of the carrier cavity protrude away from the carrier cavity to form a gate residual clearance area.
2. The electronic component carrier tape according to claim 1, wherein: The gate residue clearance zone is only located in the second region, and the width of the carrier cavity in the first region is smaller than the width of the carrier cavity in the gate residue clearance zone.
3. The electronic component carrier tape according to claim 1, wherein: In the length direction of the carrier cavity, the second area is divided into the gate residue clearance area and the non-gate residue clearance area, and the width of the carrier cavity in the non-gate residue clearance area is smaller than the width of the carrier cavity in the gate residue clearance area.
4. The electronic component carrier tape according to claim 1, wherein: In the height direction of the carrier cavity, the gate residue clearance area extends from the top of the carrier cavity to a part of or the entire area of the first area.
5. The electronic component carrier tape according to claim 1, wherein: The sidewall surface is an inclined surface in the first region, and / or the sidewall surface is an inclined surface in the second region.
6. The electronic component carrier tape according to claim 1, characterized in that: The carrier tape further includes a boss disposed on the side wall, and the boss is located in the first area.
7. The electronic component carrier tape according to claim 6, wherein: The bosses on the two opposite side walls are arranged flush with each other.
8. The electronic component carrier tape according to claim 6, wherein: The bosses on the two opposite side walls are staggered.
9. The electronic component carrier tape according to claim 6, characterized in that: The boss is arranged below the gate residue clearance area.
10. The electronic component carrier tape according to claim 6, characterized in that: The boss is arranged at the junction of the side wall and the bottom of the carrier cavity.
11. The electronic component carrier tape according to claim 1, wherein: A partial area of the bottom of the carrier cavity protrudes into the carrier cavity to form a recessed area on the bottom surface of the main body.
12. The electronic component carrier tape according to claim 11, wherein: In the recessed area, an opening passes through the main body.
13. The electronic component carrier tape according to claim 1, wherein: The carrier tape further includes a cover tape, which can cover the top surface of the carrier cavity to close the carrier cavity.