Electronic package and electronic structure
By setting a nanowire array metal layer between the thermal interface material and the back metal layer, the problem of thermal interface material slipping is solved, the heat dissipation efficiency of the semiconductor package is improved, and a better heat dissipation effect is achieved.
Patent Information
- Application Number
- CN202422672998.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-24
- Filing Date
- 2024-11-04
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2034-11-04
AI Technical Summary
In the prior art, the thermal conductivity of semiconductor chip packaging colloid is low, resulting in poor heat dissipation efficiency. In addition, the thermal interface material is prone to slipping or overflowing during high-temperature processes, affecting the heat dissipation effect and reducing the heat dissipation capacity of the package.
A nanowire array metal layer is set between the thermal interface material and the back-end metal layer. A rough structure is formed by electroplating to increase friction, ensure that the thermal interface material is firmly bonded, avoid offset, and improve the close fit between the heat sink and the electronic components.
The heat dissipation efficiency of semiconductor packages is improved, ensuring that the thermal interface material is not easy to slide during high-temperature processes, maintaining good bonding, and improving the overall heat dissipation effect without adding new materials or process costs.
Smart Images
Figure CN223401601U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a semiconductor device, and more particularly to an electronic package and an electronic structure. Background Art
[0002] As the demand for functionality and processing speed in electronic products increases, semiconductor chips, the core components of these products, must incorporate higher densities of electronic circuits and components. Consequently, these chips generate greater amounts of heat during operation. Furthermore, the encapsulant used to encapsulate these chips is a poor heat transfer material with a thermal conductivity of only 0.8W / mK (i.e., poor heat dissipation efficiency). Therefore, if the heat generated by the semiconductor chip cannot be effectively dissipated, it can damage the chip and compromise product reliability.
[0003] Therefore, in order to quickly dissipate heat to the outside, the industry usually configures a heat sink (heat spreader) in the semiconductor package. The heat sink is combined with the back side of the semiconductor chip to dissipate the heat generated by the semiconductor chip through the heat sink.
[0004] Figure 1 Figure 1 is a cross-sectional view of a conventional semiconductor package 1, which includes a package substrate 11, a semiconductor chip 12 flip-chip mounted on the package substrate 11, and a heat sink 13. The heat sink 13 is made of copper, and the semiconductor chip 12 is made of silicon. To enhance the bonding and heat dissipation between the heat sink 13 and the semiconductor chip 12, the industry typically adds a back side metallization (BSM) 15 and a thermal interface material (TIM) 14 to the back of the semiconductor chip 12.
[0005] Specifically, when the industry places a low-melting-point thermal conductive interface material 14 on the back of the semiconductor chip 12, it is necessary to add a back-metal layer 15 on the back of the semiconductor chip 12. However, after the low-melting-point thermal conductive interface material 14 is placed, it is easily affected by the machine movement before entering the high-temperature process, causing the low-melting-point thermal conductive interface material 14 to slide or overflow from the edge of the back of the semiconductor chip 12 (e.g. Figure 1 As shown), the heat conducting interface material 14 between the heat sink 13 and the semiconductor chip 12 is insufficient, resulting in poor heat dissipation effect and reducing the heat dissipation capacity of the semiconductor package 1.
[0006] To address this issue, the current industry solution involves using polymer glue to bond the backside metal layer and the thermal interface material. However, this polymer glue, when welding the low-melting-point thermal interface material to the backside metal layer, can hinder the reaction of metal ions, leading to holes and cracks at the weld interface and reducing heat dissipation.
[0007] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Utility Model Content
[0008] In view of the various deficiencies of the above-mentioned prior art, the present application provides an electronic package, comprising: a carrier; an electronic component disposed on the carrier; a heat sink covering the electronic component; a thermally conductive interface material for the heat sink to be connected to the electronic component through the thermally conductive interface material; a back-end metal layer disposed on the electronic component; and a nanowire array metal layer disposed between the thermally conductive interface material and the back-end metal layer and combined with the thermally conductive interface material.
[0009] The present application also provides an electronic structure, comprising: an electronic component; a back-end metal layer disposed on the electronic component; and a nanowire array metal layer disposed on the back-end metal layer.
[0010] In the aforementioned electronic package and electronic structure, the electronic component has an active surface and an inactive surface opposite to each other, and the active surface is electrically connected to the carrier through a plurality of conductive bumps in a flip chip manner.
[0011] In the aforementioned electronic package and electronic structure, the heat sink comprises a top sheet and supporting legs, one end of the supporting legs is coupled to the top sheet, and the other end is disposed on the carrier.
[0012] In the aforementioned electronic package and electronic structure, the thermally conductive interface material is a metal layer with a low melting point.
[0013] In the aforementioned electronic package and electronic structure, the thermally conductive interface material is indium or gallium.
[0014] In the aforementioned electronic package and electronic structure, the back metal layer is one of the group consisting of aluminum, titanium, nickel, vanadium and gold.
[0015] In the aforementioned electronic package and electronic structure, the nanowire array metal layer is formed on the outermost metal layer of the back-end metal layer of the multi-layer metal layer structure by electroplating.
[0016] In the aforementioned electronic package and electronic structure, the material of the nanowire array metal layer is one of gold (Au), silver (Ag), copper (Cu), and nickel (Ni).
[0017] In the aforementioned electronic package and electronic structure, the nanowire array metal layer forms a rough structure on the surface of the back-end metal layer.
[0018] In the aforementioned electronic package and electronic structure, the thermally conductive interface material is deformed and sunk into the nanowire array of the nanowire array metal layer, so that the nanowire array metal layer is combined with the thermally conductive interface material.
[0019] Through the implementation of this application, the nanowire array metal layer is primarily positioned between the thermal interface material and the backside metal layer. This nanowire array metal layer creates a roughened surface structure on the backside metal layer, increasing friction. This prevents the thermal interface material from shifting during subsequent manufacturing processes, which could lead to poor bonding between the heat sink and the electronic component, thus affecting the heat dissipation efficiency of the electronic package. Furthermore, the thermal interface material is firmly anchored within the nanowire array metal layer, effectively bonding to the nanowire array metal layer and closely adhering to the surface of the electronic component, thereby improving the heat dissipation efficiency of the electronic package. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 Schematic cross-sectional view of a conventional semiconductor package.
[0021] Figure 2 Schematic cross-sectional view of the electronic package of the present application.
[0022] Figure 3 It is a partial cross-sectional schematic diagram of the electronic structure of this application.
[0023] Description of Reference Numerals
[0024] 1 Semiconductor Package
[0025] 11 Package substrate
[0026] 12 semiconductor chips
[0027] 13 heat sink
[0028] 14 Thermal Interface Materials
[0029] 15. Backside metal layer
[0030] 2 Electronic packaging
[0031] 2a Electronic structure
[0032] 21 bearing parts
[0033] 22 Electronic components
[0034] 22a Active surface
[0035] 22b Non-active surface
[0036] 220 conductive bumps
[0037] 23 heat sink
[0038] 231 top sheet
[0039] 232 support legs
[0040] 24 Thermal Interface Materials
[0041] 25 backside metal layer
[0042] 26-nanowire array metal layer. DETAILED DESCRIPTION
[0043] The following describes the implementation of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.
[0044] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in this application without affecting the efficacy and purpose that can be achieved by this application. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of this application. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of this application without substantially changing the technical content.
[0045] Figure 2 The figure is a schematic cross-sectional view of an electronic package 2 of the present application. The electronic package 2 includes a carrier 21; an electronic component 22 disposed on and electrically connected to the carrier 21; a heat sink 23 covering the electronic component 22; a thermal interface material (TIM) 24 through which the heat sink 23 is connected to the electronic component 22; a back-end metal layer 25 disposed on the electronic component 22 and connected to the TIM 24; and a nanowire array metal layer 26 disposed between the TIM 24 and the back-end metal layer 25 and bonded to the TIM 24.
[0046] The carrier 21 is, for example, a package substrate having a core layer and a circuit structure, or a coreless circuit structure including a dielectric layer and a circuit layer (such as a redistribution layer). The carrier 21 may also be a lead frame, a silicon interposer, a wafer, or other board with metal routing, but is not limited to the above.
[0047] The aforementioned electronic component 22 is mounted on the carrier 21 and electrically connected to the circuit layer. The electronic component 22 may be an active component, a passive component, a package structure, or a combination thereof. Active components may be semiconductor chips such as application processors (APs) used in mobile devices such as mobile phones or other computing chips, while passive components may be resistors, capacitors, and inductors. In this embodiment, the electronic component 22 is a semiconductor chip having an active surface 22a and an inactive surface 22b opposite to each other. The active surface 22a is electrically connected to the carrier 21 via a plurality of conductive bumps 220 in a flip-chip manner.
[0048] The heat sink 23 is, for example, a heat sink, heat cover (Lid), or other component with equivalent functionality. In this embodiment, the heat sink 23 comprises a top plate 231 and supporting legs 232. One end of the supporting legs 232 is coupled to the top plate 231, while the other end is positioned on the carrier 21, with the bottom surface of the top plate 231 facing the inactive surface 22b of the electronic component 22. The heat sink 23 is made of copper.
[0049] A thermally conductive interface material 24 is further disposed between the inactive surface 22b of the electronic component 22 and the bottom surface of the top plate 231 of the heat sink 23. This allows heat generated by the electronic component 22 to be more efficiently transferred to the heat sink 23 and then dissipated into the environment. In this embodiment, the thermally conductive interface material 24 is a low-melting-point metal layer, such as indium (In) or gallium (Ga).
[0050] The back metal layer 25 is disposed on the electronic component 22 and connected to the thermally conductive interface material 24. The back metal layer 25 may be a multi-layer metal structure, such as one of the group consisting of aluminum (Al), titanium (Ti), nickel (Ni), vanadium (V), and gold (Au).
[0051] The aforementioned nanowire array metal layer 26 is disposed between the thermally conductive interface material 24 and the backside metal layer 25 and is bonded to the thermally conductive interface material 24. The nanowire array metal layer 26 is formed by electroplating the outermost metal layer of the backside metal layer 25 in the multi-layer metal structure. The nanowire array metal layer 26 is made of a material such as gold (Au), silver (Ag), copper (Cu), or nickel (Ni). This creates a rough surface on the backside metal layer 25 to increase friction, thereby preventing the thermally conductive interface material 24 (e.g., a low-melting-point indium metal layer) from sliding during the manufacturing process. Furthermore, due to the soft metal properties of the low-melting-point thermal interface material 24, an external force can be applied when placing it on the nanowire array metal layer 26 on the surface of the backside metal layer 25 during the manufacturing process. This causes the low-melting-point thermal interface material 24 to deform and sink into the nanowire array of the nanowire array metal layer 26, thereby firmly fixing it without affecting the quality of the welding process, thereby effectively bonding the nanowire array metal layer 26 to the thermal interface material 24.
[0052] Please also refer to Figure 3 The present application also discloses an electronic structure 2a, comprising an electronic element 22, a backside metal layer 25 and a nanowire array metal layer 26.
[0053] The backside metal layer 25 is disposed on the electronic element 22 and can be a multi-layer metal layer structure.
[0054] The nanowire array metal layer 26 is formed by electroplating on the outermost metal layer of the back metal layer 25 of the multi-layer metal layer structure, so that the surface of the back metal layer 25 has a rough structure to increase friction for bonding with thermal conductive interface materials.
[0055] In summary, the electronic package and electronic structure of the present application mainly place the nanowire array metal layer between the thermal interface material and the back-end metal layer. This is because the nanowire array metal layer can form a rough structure on the surface of the back-end metal layer to increase friction to prevent the thermal interface material from being offset in subsequent processes, resulting in poor bonding between the heat sink and the electronic component, thereby affecting the heat dissipation efficiency of the electronic package. At the same time, the thermal interface material can be sunk into the nanowire array metal layer and firmly fixed, so that the thermal interface material can effectively combine with the nanowire array metal layer and can closely fit the surface of the electronic component to improve the heat dissipation efficiency of the electronic package. Furthermore, the aforementioned structure does not require the addition of new development processes and materials or the purchase of equipment. Existing technical problems in the industry can be solved with existing materials, old processes and equipment, so there will be no large amount of additional cost expenditure.
[0056] The above embodiments are intended to illustrate the principles and effects of this application and are not intended to limit this application. Those skilled in the art may modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application shall be as set forth in the claims.
Claims
1. An electronic package, characterized in that: include: bearing members; an electronic component disposed on the carrier; a heat sink covering the electronic component; A thermally conductive interface material, through which the heat sink is connected to the electronic component; A back-end metal layer is provided on the electronic components; as well as The nanowire array metal layer is disposed between the thermally conductive interface material and the back-side metal layer and is combined with the thermally conductive interface material.
2. The electronic package according to claim 1, wherein The electronic component has an active surface and an inactive surface opposite to each other, and the active surface is electrically connected to the carrier through a plurality of conductive bumps in a flip chip manner.
3. The electronic package according to claim 1, wherein: The heat dissipation component comprises a top sheet and a supporting leg. One end of the supporting leg is combined with the top sheet, and the other end is arranged on the supporting component.
4. The electronic package according to claim 1, wherein: The thermal conductive interface material is a metal layer with a low melting point.
5. The electronic package according to claim 1, wherein: The thermal conductive interface material is indium or gallium.
6. The electronic package according to claim 1, wherein: The backside metal layer is one of the group consisting of aluminum, titanium, nickel, vanadium and gold.
7. The electronic package according to claim 1, wherein: The nanowire array metal layer is formed on the outermost metal layer of the back-end metal layer of the multi-layer metal layer structure by electroplating.
8. The electronic package according to claim 1, wherein: The material of the nanowire array metal layer is one of gold, silver, copper and nickel.
9. The electronic package according to claim 1, wherein: The nanowire array metal layer forms a rough structure on the surface of the back-end metal layer.
10. The electronic package according to claim 1, wherein The thermally conductive interface material is deformed and sunk into the nano-array of the nano-wire array metal layer, so that the nano-wire array metal layer is combined with the thermally conductive interface material.
11. An electronic structure, characterized in that include: electronic components; A back-end metal layer is provided on the electronic components; as well as The nanowire array metal layer is disposed on the backside metal layer.
12. The electronic structure according to claim 11, wherein The nanowire array metal layer is combined with a heat-conducting interface material, and the heat-conducting interface material is a metal layer with a low melting point.
13. The electronic structure according to claim 12, wherein The thermal conductive interface material is indium or gallium.
14. The electronic structure according to claim 12, wherein The thermally conductive interface material is deformed and sunk into the nano-array of the nano-wire array metal layer, so that the nano-wire array metal layer is combined with the thermally conductive interface material.
15. The electronic structure according to claim 11, wherein The backside metal layer is one of the group consisting of aluminum, titanium, nickel, vanadium and gold.
16. The electronic structure according to claim 11, wherein The nanowire array metal layer is formed on the outermost metal layer of the back-end metal layer of the multi-layer metal layer structure by electroplating.
17. The electronic structure according to claim 11, wherein The material of the nanowire array metal layer is one of gold, silver, copper and nickel.
18. The electronic structure according to claim 11, wherein The nanowire array metal layer forms a rough structure on the surface of the back-end metal layer.