Package structure
By using the bottom and top air gap design and rigid structure fixation in the packaging structure, the problem of die offset in the first chip process is solved, and low-cost and efficient multi-chip packaging is achieved.
Patent Information
- Application Number
- CN202422668207.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2034-11-01
AI Technical Summary
In the existing chip-first process, the multi-chip fan-out packaging structure is prone to die offset and relative displacement due to tape deformation during the molding process, which makes it impossible to effectively fix the relative positions of multiple dies, and the use of highly viscous tape will lead to residual glue problems.
The packaging structure design includes a bottom and an upper part. The bottom and the upper part are connected by the same material with an air gap between them. A rigid structure is used to fix the position of the upper part to reduce the displacement, and electrical connection is achieved through a dielectric layer and a redistribution layer.
The displacement of the upper part is effectively reduced, the rigidity of the packaging structure and the reliability of the electrical connection are improved, and the cost and process complexity are reduced.
Smart Images
Figure CN223414071U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a packaging structure. Background Art
[0002] Currently, fan-out packaging is divided into chip-first (CF) process structure and chip-last (CL) process structure. Compared with the chip-last process, the chip-first process has the advantages of low cost, fewer process steps and better electrical properties (no solder is used).
[0003] Figures 1 to 2 The process of making a fan-out multi-chip module (FOMCM) using a chip-first process is shown. Figure 1 The figure shows that a plurality of dies 2 obtained by cutting the wafer 1 are placed on a carrier wafer 3 and a tape 4, wherein the active surface of the dies 2 faces downward. Figure 2 shows the use of encapsulation layer 5 encapsulation Figure 1 The structure shown is used to form a wafer level package (WLP).
[0004] Figure 3 Shown is the corresponding Figure 2 The top view of the step shown in FIG. 4 shows the outer contours of the carrier wafer 3 and the tape 4, which are not visible due to being covered by the encapsulation layer 5. In the chip-first process, the die 2 is placed on the tape 4, which is relatively soft. When the encapsulation layer 4 is formed by molding, the soft tape 4 will be deformed. In the high-temperature and high-pressure molding environment, the die 2 will be deformed radially and irregularly. When a low-viscosity tape 4 is used, the impact of the mold flow on the die 2 will be as follows: Figure 2 The arrow in the figure pushes die 2 in the direction of movement, causing it to shift. Bump shifting can compensate for deformation when there's only one die 2, but it can't compensate for the complex deformations that occur with multiple dies / chips. Using a more viscous tape would also create the problem of residual adhesive remaining on the active surface of die 2 after removal.
[0005] Figure 4 Shown Figure 3 In area A, three packages 8 are each packaged with two dies 2. Because the dies 2 are offset as indicated by the arrows, the relative offset difference between the two dies 2 is too large. When connecting the two dies 2 using redistribution layer 6, for example, redistribution layer 6 cannot be successfully aligned with the dies 2 at area 7. Therefore, in the prior art, the FOMCM structure cannot be used in the chip-first process. Utility Model Content
[0006] In view of the problems existing in the related art, the purpose of the present invention is to provide a packaging structure to at least reduce the displacement of electronic components in the packaging structure.
[0007] To achieve the above objectives, the present invention provides a packaging structure, comprising: an electronic component comprising a bottom and an upper portion located on the bottom, wherein the active surface of the electronic component is the upper surface of the upper portion; and a packaging layer located above the bottom and packaging the upper portion.
[0008] In some embodiments, the sidewalls of the bottom portion are flush with the sidewalls of the encapsulation layer.
[0009] In some embodiments, the sidewalls of the upper portion are recessed relative to the sidewalls of the bottom portion.
[0010] In some embodiments, an upper surface of the encapsulation layer is concave relative to an upper surface of the upper portion.
[0011] In some embodiments, the concave portion of the upper surface of the encapsulation layer is a curved surface.
[0012] In some embodiments, the curved surface connects the upper surface of the upper portion.
[0013] In some embodiments, there is an air gap between the upper portion and the bottom portion.
[0014] In some embodiments, a plurality of air gaps are spaced apart from each other between the upper portion and the bottom portion.
[0015] In some embodiments, the air gap has a larger dimension in the horizontal direction than in the vertical direction.
[0016] In some embodiments, the bottom portion and the upper portion comprise the same material.
[0017] In some embodiments, the base material is silicon.
[0018] In some embodiments, the packaging structure further includes: a dielectric layer located on the electronic component and the packaging layer.
[0019] In some embodiments, a portion of the bottom surface of the dielectric layer that contacts the encapsulation layer protrudes downward relative to a portion that contacts the upper portion.
[0020] In some embodiments, the sidewalls of the dielectric layer are aligned with the sidewalls of the encapsulation layer and the sidewalls of the bottom.
[0021] In some embodiments, the upper surface of the upper portion has a solder pad.
[0022] In some embodiments, the encapsulation layer completely covers the sides of the upper portion.
[0023] An embodiment of the present application also provides a packaging structure, including: an electronic component, including a bottom and an upper part protruding from the bottom, the active surface of the electronic component being the upper surface of the upper part; and a packaging layer, packaging the upper part.
[0024] In some embodiments, a central area of the upper surface of the base contacts the upper portion, and a peripheral area contacts the encapsulation layer.
[0025] In some embodiments, the upper portion and the bottom portion are not continuously in contact.
[0026] In some embodiments, a plurality of air gaps of different sizes are located between the upper portion and the bottom portion.
[0027] The beneficial technical effects of the present utility model are:
[0028] In the embodiment of the present application, the displacement of the upper portion is reduced by fixing the upper portion with the bottom portion. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without inventive work. It is worth noting that, according to standard industry practices, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the clarity of discussion, the sizes of the various components can be arbitrarily increased or decreased.
[0030] Figure 1 The plurality of dies diced from the wafer are shown placed on a carrier wafer and tape.
[0031] Figure 2 shows the use of encapsulation layers Figure 1 The structure shown is used to form an embedded wafer-level package.
[0032] Figure 3 Shown is the corresponding Figure 2 Top view of the steps shown.
[0033] Figure 4 Shown Figure 3 Three packages in area A.
[0034] Figure 5 It is shown that a carrier wafer and tape are provided.
[0035] Figure 6 It shows that a plurality of chips / dies are placed on the tape and a rigid structure is formed on the upper passive side.
[0036] Figure 7shows the use of encapsulation layers Figure 6 The structure shown.
[0037] Figure 8 Shown is the corresponding Figure 7 Top view of the steps shown.
[0038] Figure 9 An embodiment of the prior art shows a simulation diagram of the deformation of one of a plurality of tube cores after being impacted by mold flow.
[0039] Figure 10 For the embodiment of the present application, a deformation amount simulation diagram of one of the plurality of upper parts is shown.
[0040] Figure 11 A top view of the rigid structure of the first embodiment is shown.
[0041] Figure 12 A top view of the rigid structure of the second embodiment is shown.
[0042] Figure 13 A bottom view of the rigid structure of the second embodiment and its upper portion on the surface is shown.
[0043] Figure 14 The carrier wafer is shown removed.
[0044] Figure 15 The tape is shown removed.
[0045] Figure 16 The formation of a dielectric layer is shown.
[0046] Figure 17 The formation of a first additional dielectric layer is shown.
[0047] Figure 18 The formation of a redistribution layer is shown.
[0048] Figure 19 The formation of a second additional dielectric layer is shown.
[0049] Figure 20 The formation of under bump metallurgy and bumps / solder balls is shown.
[0050] Figure 21 The package structure according to the embodiment of the present application is shown. DETAILED DESCRIPTION
[0051] In order to better understand the spirit of the embodiments of the present application, some preferred embodiments of the present application are further described below.
[0052] The embodiments of the present application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are represented by similar reference numerals. The embodiments described herein with respect to the accompanying drawings are illustrative and diagrammatic and are intended to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.
[0053] As used herein, the terms "substantially," "substantially," and "approximately" are used to describe and illustrate small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred precisely as well as instances where the event or circumstance occurred very approximately.
[0054] In this specification, unless otherwise specified or limited, relative terms such as "central", "longitudinal", "lateral", "front", "rear", "right", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below", "above", "below", "top", "bottom" and their derivatives (such as "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the directions described in the discussion or depicted in the drawings. These relative terms are used for convenience of description only and do not require that the present application be constructed or operated in a specific orientation.
[0055] For ease of description, “first,” “second,” “third,” etc. may be used herein to distinguish different components in a figure or a series of figures. “First,” “second,” “third,” etc. are not intended to describe the corresponding components.
[0056] Figures 5 to 20 A method for forming the package structure 100 according to an embodiment of the present application is shown.
[0057] Figure 5 It is shown that a carrier wafer 80 is provided, and a lamination process is performed, for example, to form the tape 70 on the carrier wafer 80 .
[0058] Figure 6 It shows that a plurality of chips / die cut from a wafer 120 (constituting the upper portion 20 of the subsequent electronic component) are placed on a tape 70 with the active surface facing downward, and a stiffness structure 110 is formed on the passive surface of the upper portion 20, wherein the material of the stiffness structure 110 is, for example, silicon or copper.
[0059] Figure 7 The encapsulation layer 50 is shown. Figure 6In the structure shown, the encapsulation layer 50 is, for example, epoxy molding compound (EMC).
[0060] Figure 8 Shown is the corresponding Figure 7 The top view of the step is shown, in which the outer contours of the upper portion 20 , the rigid structure 110 , the carrier wafer 80 and the tape 70 that are covered by the encapsulation layer 50 and cannot be seen are shown using dotted lines.
[0061] Figure 9 To correspond to Figures 1 to 4 1 is an embodiment of the prior art, showing a simulation diagram of the deformation amount of one of the plurality of tube cores 2 after being impacted by mold flow. Figure 10 To correspond to Figure 7 and Figure 8 According to an embodiment of the present application, a deformation simulation diagram of one of the plurality of upper portions 20 is shown. Figure 9 and Figure 10 The diagram is shown in a top-down perspective, with arrows indicating the direction of mold flow impacting the tube core 2 and upper portion 20. It can be seen that the sidewalls 9 and 24 of the tube core 2 and upper portion 20, which are directly subjected to the mold flow impact, experience the greatest deformation. The maximum deformation of the embodiment of the present application is smaller than that of the prior art. Letting the displacement of the tube core 2 in the prior art be x, the displacement of the upper portion 20 in the present application is 0.32x. As can be seen from the above, the displacement of the upper portion 20 is reduced by 68% compared to the prior art. Furthermore, the embodiment of the present application also reduces relative movement within the upper portion 20.
[0062] Figure 11 A top view of the rigid structure 110 of the first embodiment is shown, wherein the rigid structure 110 is a one-piece circular structure in the top view.
[0063] Figure 12 A top view of the rigid structure 111 of the second embodiment is shown, wherein the rigid structure 111 has a square shape corresponding to the upper portion 20 in the top view, and mesh grooves 112 are opened therein.
[0064] Figure 13 A bottom view of the rigid structure 111 and the upper portions 20 on its surface in the second embodiment is shown. Mesh grooves 112 are defined between adjacent upper portions 20. Although the rigid structure 111 of the second embodiment includes mesh grooves 112, the rigid structure 111 still has a continuous portion to ensure the relative position of the upper portions 20 is fixed. For the rigid structure 111 of the second embodiment, the mesh grooves 112 are filled in the encapsulation layer 50 after the encapsulation layer 50 is molded, thereby strengthening the bonding between the encapsulation layer 50, the rigid structure 111, and the upper portion 20.
[0065] Figure 14The carrier wafer 80 is shown being debonded under heated conditions.
[0066] Figure 15 The tape 70 is shown to be removed under heating conditions. The heating conditions facilitate debonding of the carrier wafer 80 , the packaging layer 50 , the upper portion 20 and the tape 70 , avoid damaging components, and facilitate clean removal of the tape 70 .
[0067] Figures 16 to 20 The structure after the tape 70 is removed is shown as a partial diagram. Figure 16 It is shown that a dielectric layer 40 is formed on the active surface of the upper portion 20, an opening is opened in the dielectric layer 40 to expose the pad 22 of the upper portion 20, and the opening is cleaned.
[0068] Figure 17 It is shown that a first additional dielectric layer 41 is formed on the dielectric layer 40 and patterned to expose the pad 22 . In some embodiments, the first additional dielectric layer 41 is a coating of a polymer material.
[0069] Figure 18 It is shown that, for example, a sputtering process and a patterning process (eg, etching) are performed to form a redistribution layer 60 on the first additional dielectric layer 41 . The redistribution layer 60 contacts and electrically connects the pads 22 to fan out the upper portion 20 .
[0070] Figure 19 A second additional dielectric layer 42 is shown formed on the redistribution layer 60 and patterned to expose portions of the redistribution layer 60 . In some embodiments, the second additional dielectric layer 42 is a coating of a polymer material.
[0071] Figure 20 It is shown that an under-bump metallization 62 and a bump / solder ball 64 are formed on the exposed portion of the redistribution layer 60, thereby obtaining a fan-out packaging structure having a reinforcement / rigidity structure 110 that is conducive to bump positioning according to an embodiment of the present application, wherein the packaging structure is, for example, a wafer level (WL) packaging structure, a 300*300mm or 600*600mm panel level (PNL) packaging structure.
[0072] Figure 21 The package structure 100 is shown as a single piece (eg obtained by cutting) according to an embodiment of the present application, wherein the corresponding Figure 16 After singulation, the rigid structure 110 becomes the lower portion 10 of the electronic component. It is understood that the package structure 100 may also include Figures 17 to 20 A first additional dielectric layer 41 , a redistribution layer 60 , a second additional dielectric layer 42 , an under bump metallurgy 62 and solder balls 64 are formed.
[0073] An embodiment of the present application provides a packaging structure 100, comprising an electronic component and a packaging layer 50. The electronic component comprises a bottom portion 10 and an upper portion 20 located on (protruding from) the bottom portion 10. The active surface of the electronic component is the upper surface of the upper portion 20. The packaging layer 50 is located above the bottom portion 10 and encapsulates the upper portion 20. The embodiment of the present application reduces the displacement of the upper portion 20 by fixing the upper portion 20 using the bottom portion 10. The packaging structure 100 of the embodiment of the present application is not limited to the number of upper portions 20. When the packaging structure 100 includes a plurality of upper portions 20, the bottom portion 10 can fix the relative positions of the plurality of upper portions 20.
[0074] In some embodiments, the upper portion 20 has a smaller lateral dimension than the bottom portion 10, and the sidewalls of the upper portion 20 are recessed relative to the sidewalls of the bottom portion 10. The encapsulation layer 50 completely covers the side surfaces of the upper portion 20. The central area of the upper surface of the bottom portion 10 contacts the upper portion 20, while the peripheral area contacts the encapsulation layer 50. After the singulation process, the sidewalls of the dielectric layer 40, the sidewalls of the bottom portion 10, and the sidewalls of the encapsulation layer 50 are flush / aligned.
[0075] exist Figure 6 In the steps shown, since the tape 70 is soft, the upper portion 20 is sunken into the tape 70. Figure 7 After the encapsulation layer 50 is formed in the steps shown, the encapsulation layer 50 is conformed to the tape 70, and the final Figure 21 The upper surface of the encapsulation layer 50 of the illustrated encapsulation structure 100 is concave relative to the upper surface of the upper portion 20. In some embodiments, the concave portion of the upper surface of the encapsulation layer 50 is a curved surface 52, which is connected to the upper surface of the upper portion 20. Furthermore, the portion of the bottom surface of the dielectric layer 40 that contacts the encapsulation layer 50 is convex downward relative to the portion that contacts the upper portion 20.
[0076] In some embodiments, the bottom portion 10 and the upper portion 20 are made of the same material to reduce the problem of thermal expansion coefficient mismatch. The contacting portions of the bottom portion 10 and the upper portion 20 are made of the same material. For example, the material of the bottom portion 10 and the contacting portion of the upper portion 20 are both made of silicon. Therefore, due to van der Waals forces, the two portions are bonded together to fix the upper portion 20. The bottom portion 10 and the upper portion 20 are fused together, so the interface between the two portions is not obvious. In some embodiments, a plurality of air gaps 30 of different sizes are provided between the upper portion 20 and the bottom portion 10 at the unfused portion. The plurality of air gaps 30 are separated from each other, and the horizontal dimension of the air gaps 30 is greater than the vertical dimension. Due to the presence of the air gaps 30, the upper portion 20 and the bottom portion 10 are not in continuous contact.
[0077] In the embodiment of the present application, a rigid structure 110 is first attached to the passive surface of the upper portion 20 before forming the encapsulation layer 50 to fix the relative position between the upper portions 20. The embodiment of the present application uses a rigid structure 110 to replace the prior art Figure 2 The volume of the encapsulation layer is shown as part of the volume of the encapsulation layer. Therefore, the volume of the encapsulation layer 50 of the present application (having a different thermal expansion coefficient from the upper portion 50) is smaller than that of the encapsulation layer of the prior art. This reduces the warping of the encapsulation structure 100, improves the rigidity of the encapsulation structure 100, and makes it less likely for the encapsulation structure 100 to deform in the direction of the encapsulation layer 50. The embodiment of the present application uses a chip-first process, which has the advantages of low cost and fewer process steps.
[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.
Claims
1. A packaging structure, characterized in that: include: An electronic component comprising a bottom portion and an upper portion located on the bottom portion, wherein the active surface of the electronic component is an upper surface of the upper portion; The encapsulation layer is located above the bottom portion and encapsulates the upper portion.
2. The packaging structure according to claim 1, wherein: The sidewall of the bottom is flush with the sidewall of the packaging layer.
3. The packaging structure according to claim 2, wherein: The side walls of the upper portion are recessed relative to the side walls of the bottom portion.
4. The packaging structure according to claim 1, wherein: An upper surface of the encapsulation layer is concave relative to an upper surface of the upper portion.
5. The packaging structure according to claim 4, wherein: The concave portion of the upper surface of the packaging layer is a curved surface.
6. The packaging structure according to claim 1, wherein: An air gap is provided between the upper portion and the bottom portion.
7. The packaging structure according to claim 1, wherein: The bottom portion and the upper portion include the same material.
8. The packaging structure according to claim 1, wherein: Also includes: A dielectric layer is located on the electronic component and the packaging layer.
9. The packaging structure according to claim 8, wherein: A portion of the bottom surface of the dielectric layer that contacts the encapsulation layer protrudes downward relative to a portion that contacts the upper portion.
10. The packaging structure according to claim 1, wherein: The upper surface of the upper portion has a pad.