Display panel

Abstract

A display panel includes: a driving device layer including a pixel driver; a light emitting device disposed on the driving device layer and including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a pixel defining film disposed on the driving device layer; and a connection electrode disposed on the pixel defining film and electrically connected to the pixel driver and the second electrode, in which the intermediate layer includes a functional layer having a first area and a light emitting layer having a second area smaller than the first area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0145250 filed on October 27, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display panel having improved contact reliability. Background Art

[0004] Multimedia electronic devices such as televisions (TVs), mobile phones, computers (such as tablet personal computers (PCs)), navigation systems, and game consoles include display panels for displaying images. The display panel includes a light-emitting device and a circuit for driving the light-emitting device. The light-emitting device included in the display panel emits light according to a voltage applied from the circuit and produces an image. Research has been conducted on the connection between the light-emitting device and the circuit to improve the reliability of the display panel. Utility Model Content

[0005] Embodiments of the present disclosure provide a display panel with improved contact reliability.

[0006] According to an embodiment, a display panel may include: a driving device layer including a pixel driver; a light-emitting device arranged on the driving device layer and including a first electrode, an intermediate layer arranged on the first electrode, and a second electrode arranged on the intermediate layer; a pixel defining film arranged on the driving device layer; and a connecting electrode arranged on the pixel defining film and electrically connected to the pixel driver and the second electrode, wherein the intermediate layer may include a functional layer having a first area and a light-emitting layer having a second area that may be smaller than the first area.

[0007] The pixel defining film defines an opening through which at least a portion of the first electrode may be exposed, wherein the connecting electrode may have an annular shape surrounding the opening, or a connection area where the second electrode and the connecting electrode may be electrically connected may surround at least a portion of the opening.

[0008] A lower surface of the second electrode may be in contact with an upper surface of the connection electrode.

[0009] The functional layer may include: a first intermediate functional layer disposed on the first electrode; and a second intermediate functional layer disposed on the light emitting layer, wherein the light emitting layer may be disposed between the first intermediate functional layer and the second intermediate functional layer.

[0010] The display panel may further include a spacer disposed on the connection electrode, wherein the second electrode and the connection electrode may be electrically connected to each other in a region adjacent to the spacer.

[0011] The display panel may further include: a first dummy layer disposed on the partition, the first dummy layer and the functional layer including the same material; and a second dummy layer disposed on the first dummy layer, the second dummy layer and the second electrode including the same material.

[0012] The connection electrode may include a first edge and a second edge surrounding the first edge, and the second edge may overlap the spacer.

[0013] The light-emitting device may be provided as a plurality of light-emitting devices, the pixel driver may be provided as a plurality of pixel drivers, and the connecting electrode may be provided as a plurality of connecting electrodes, the plurality of connecting electrodes may electrically connect the plurality of light-emitting devices and the plurality of pixel drivers, respectively, and gaps between adjacent connecting electrodes among the plurality of connecting electrodes may overlap with the partition.

[0014] A through hole may be defined in the pixel defining film, and the connecting electrode may be electrically connected to the pixel driver through the through hole, wherein the light-emitting layer may not overlap with the through hole and the functional layer may overlap with the through hole, or the light-emitting layer and the functional layer may overlap with the through hole.

[0015] The pixel defining film defines an opening, and at least a portion of the first electrode may be exposed through the opening. The connecting electrode may include a protruding portion protruding in a direction away from the opening, and the protruding portion may not overlap with the light-emitting layer. The protruding portion of the connecting electrode and the light-emitting layer may be spaced apart from each other, and the functional layer may overlap with an area between the protruding portion and the light-emitting layer.

[0016] According to an embodiment, a display panel may include: a driving device layer including a pixel driver; a light-emitting device arranged on the driving device layer and including a first electrode, a light-emitting layer arranged on the first electrode, and a second electrode arranged on the light-emitting layer, wherein a light-emitting portion can be defined as corresponding to a portion of the first electrode; and a connecting electrode electrically connected to the pixel driver and the second electrode, wherein the connecting electrode includes a first edge surrounding the light-emitting portion, and a portion of the first edge does not overlap with the light-emitting layer, and the portion of the first edge can be spaced apart from an edge of the light-emitting layer.

[0017] The display panel may further include: a pixel defining film disposed on the driving device layer, wherein an opening and a through hole spaced apart from the opening may be defined in the pixel defining film, the opening defining the light-emitting portion by exposing the portion of the first electrode, and the connecting electrode may be disposed on the pixel defining film, and the connecting electrode may be electrically connected to the pixel driver through the through hole.

[0018] The connecting electrode also includes a second edge surrounding the first edge, wherein the display panel may further include: a partition disposed on the pixel defining film and overlapping the second edge, wherein the second electrode and the connecting electrode may be electrically connected to each other in an area adjacent to the partition.

[0019] The light emitting layer may overlap with the opening and may not overlap with the through hole, or the light emitting layer may overlap with the opening and the through hole.

[0020] The portion of the first edge may protrude in a direction away from the opening.

[0021] The light-emitting device may further include: a first intermediate functional layer, disposed between the first electrode and the light-emitting layer; and a second intermediate functional layer, disposed between the light-emitting layer and the second electrode, wherein an area of ​​each of the first intermediate functional layer and the second intermediate functional layer may be greater than an area of ​​the light-emitting layer, or the first intermediate functional layer and the second intermediate functional layer may overlap with the portion of the first edge.

[0022] According to an embodiment, a display panel may include: a driving device layer including a plurality of pixel drivers; a plurality of light-emitting devices arranged on the driving device layer and electrically connected to the plurality of pixel drivers, respectively; a plurality of connecting electrodes electrically connected to the plurality of pixel drivers and the plurality of light-emitting devices; and a plurality of partitions arranged between the plurality of light-emitting devices, wherein each of the plurality of light-emitting devices includes a first electrode, an intermediate layer arranged on the first electrode, and a second electrode arranged on the intermediate layer, and the intermediate layer includes a plurality of layers, some of the plurality of layers can be arranged in a first region of the intermediate layer, and all of the plurality of layers can be arranged in a second region of the intermediate layer adjacent to the first region.

[0023] The gap between adjacent connecting electrodes among the multiple connecting electrodes can overlap with a corresponding one of the multiple partitions, and the display panel can further include: a pixel defining film, which is arranged on the driving device layer and defines an opening in the pixel defining film that exposes at least a portion of the first electrode of each of the multiple light-emitting devices, wherein a portion of each of the multiple connecting electrodes can be arranged on the pixel defining film, and the multiple partitions can be arranged on the pixel defining film.

[0024] The plurality of light-emitting devices may include a first light-emitting device, a second light-emitting device spaced apart from the first light-emitting device in a first direction, and a third light-emitting device spaced apart from the first light-emitting device and the second light-emitting device in a second direction intersecting the first direction. A first opening exposing at least a portion of the first electrode of the first light-emitting device, a second opening exposing at least a portion of the first electrode of the second light-emitting device, and a third opening exposing at least a portion of the first electrode of the third light-emitting device may be defined in the pixel defining film, and the plurality of connecting electrodes may include a first connecting electrode surrounding the first opening, a second connecting electrode surrounding the second opening, and a third connecting electrode surrounding the third opening.

[0025] The first region of the first light emitting device and the first region of the second light emitting device may be disposed between the first opening and the second opening, and may be spaced apart from each other in the second direction.

[0026] The multiple pixel drivers may include a first pixel driver electrically connected to the first light-emitting device, a second pixel driver electrically connected to the second light-emitting device, and a third pixel driver electrically connected to the third light-emitting device. A first through hole, a second through hole, and a third through hole may be defined in the pixel defining film, and the first connecting electrode may be electrically connected to the first pixel driver through the first through hole, the second connecting electrode may be electrically connected to the second pixel driver through the second through hole, and the third connecting electrode may be electrically connected to the third pixel driver through the third through hole.

[0027] The first region of the first light emitting device may overlap with the first through hole, the first region of the second light emitting device may overlap with the second through hole, and the first region of the third light emitting device may overlap with the third through hole.

[0028] The first region of the first light-emitting device may not overlap with the first through hole, the first region of the second light-emitting device may not overlap with the second through hole, and the first region of the third light-emitting device may overlap with the third through hole, wherein the first region of the first light-emitting device or the first region of the second light-emitting device may be adjacent to the first region of the third light-emitting device in the second direction.

[0029] The gaps between adjacent connecting electrodes among the multiple connecting electrodes may overlap with corresponding one of the multiple partitions, and the multiple layers of the intermediate layer may include: a first intermediate functional layer, arranged on the first electrode; a light-emitting layer, arranged on the first intermediate functional layer; and a second intermediate functional layer, arranged on the light-emitting layer, and the first region of the intermediate layer may include the first intermediate functional layer and the second intermediate functional layer, and the second region of the intermediate layer may include the first intermediate functional layer, the light-emitting layer and the second intermediate functional layer.

[0030] According to an embodiment, a display panel may include: a driving device layer including a pixel driver; a light-emitting device arranged on the driving device layer and including a first electrode, an intermediate layer arranged on the first electrode, and a second electrode arranged on the intermediate layer; a pixel-defining film arranged on the driving device layer and defining an opening, through which at least a portion of the first electrode may be exposed; and a connecting electrode arranged on the pixel-defining film and electrically connected to the pixel driver and the second electrode, wherein the intermediate layer may include a functional layer having a first area and a light-emitting layer having a second area that may be smaller than the first area.

[0031] The connection electrode may have a ring shape surrounding the opening.

[0032] A lower surface of the second electrode may be in contact with an upper surface of the connection electrode.

[0033] A connection region in which the second electrode and the connection electrode may be electrically connected may surround at least a portion of the opening.

[0034] The functional layer may include: a first intermediate functional layer disposed on the first electrode; and a second intermediate functional layer disposed on the light emitting layer, wherein the light emitting layer may be disposed between the first intermediate functional layer and the second intermediate functional layer.

[0035] The display panel may further include a spacer disposed on the connection electrode, wherein the second electrode and the connection electrode may be electrically connected to each other in a region adjacent to the spacer.

[0036] The display panel may further include a first dummy layer disposed on the spacer, the first dummy layer and the functional layer including the same material. The display panel may further include a second dummy layer disposed on the first dummy layer, the second dummy layer and the second electrode including the same material.

[0037] The connection electrode may include a first edge and a second edge surrounding the first edge, and the second edge may overlap the spacer.

[0038] The light-emitting device may be provided as a plurality of light-emitting devices, the pixel driver may be provided as a plurality of pixel drivers, and the connecting electrode may be provided as a plurality of connecting electrodes, the plurality of connecting electrodes may electrically connect the plurality of light-emitting devices and the plurality of pixel drivers, respectively, and gaps between adjacent connecting electrodes among the plurality of connecting electrodes may overlap with the partition.

[0039] A through hole may be defined in the pixel defining film, and the connection electrode may be electrically connected to the pixel driver through the through hole.

[0040] The light emitting layer may not overlap with the through hole, and the functional layer may overlap with the through hole.

[0041] The light emitting layer and the functional layer may overlap with the through hole.

[0042] The connection electrode may include a protrusion portion protruding in a direction away from the opening, and the protrusion portion may not overlap with the light emitting layer.

[0043] The protrusion portion of the connection electrode and the light emitting layer may be spaced apart from each other, and the functional layer may overlap a region between the protrusion portion and the light emitting layer.

[0044] According to an embodiment, a display panel may include: a driving device layer including a pixel driver; a light-emitting device arranged on the driving device layer and including a first electrode, a light-emitting layer arranged on the first electrode, and a second electrode arranged on the light-emitting layer, wherein the light-emitting portion can be defined as corresponding to a portion of the first electrode; and a connecting electrode electrically connected to the pixel driver and the second electrode, wherein the connecting electrode includes a first edge surrounding the light-emitting portion and a second edge surrounding the first edge, and a portion of the first edge does not overlap with the light-emitting layer, and the portion of the first edge can be spaced apart from an edge of the light-emitting layer.

[0045] The display panel may further include a pixel defining film disposed on the driving device layer, wherein an opening for defining the light-emitting portion by exposing the portion of the first electrode and a through hole spaced apart from the opening may be defined in the pixel defining film, and the connecting electrode may be disposed on the pixel defining film, and the connecting electrode may be electrically connected to the pixel driver through the through hole.

[0046] The display panel may further include a spacer disposed on the pixel defining film and overlapping the second edge, wherein the second electrode and the connection electrode may be electrically connected to each other in a region adjacent to the spacer.

[0047] The light emitting layer may overlap with the opening and may not overlap with the through hole.

[0048] The light emitting layer may overlap with the opening and the through hole.

[0049] The portion of the first edge may protrude in a direction away from the opening.

[0050] The light emitting device may further include a first intermediate functional layer disposed between the first electrode and the light emitting layer, and a second intermediate functional layer disposed between the light emitting layer and the second electrode.

[0051] An area of ​​each of the first intermediate functional layer and the second intermediate functional layer may be greater than an area of ​​the light emitting layer.

[0052] The first intermediate functional layer and the second intermediate functional layer may overlap the portion of the first edge.

[0053] According to an embodiment, a display panel may include: a driving device layer including a plurality of pixel drivers; a plurality of light-emitting devices arranged on the driving device layer and electrically connected to the plurality of pixel drivers, respectively; a plurality of connecting electrodes electrically connected to the plurality of pixel drivers and the plurality of light-emitting devices; and a plurality of partitions arranged between the plurality of light-emitting devices, wherein each of the plurality of light-emitting devices includes a first electrode, an intermediate layer arranged on the first electrode, and a second electrode arranged on the intermediate layer, a gap between adjacent connecting electrodes among the plurality of connecting electrodes may overlap with a corresponding one of the plurality of partitions, and the intermediate layer includes a plurality of layers, some of the plurality of layers may be arranged in a first region of the intermediate layer, and all of the plurality of layers may be arranged in a second region of the intermediate layer adjacent to the first region.

[0054] The display panel may further include a pixel-defining film, which may be disposed on the driving device layer and may define an opening in the pixel-defining film that exposes at least a portion of the first electrode of each of the plurality of light-emitting devices, wherein a portion of each of the plurality of connecting electrodes may be disposed on the pixel-defining film, and the plurality of spacers may be disposed on the pixel-defining film.

[0055] The plurality of light-emitting devices may include a first light-emitting device, a second light-emitting device spaced apart from the first light-emitting device in a first direction, and a third light-emitting device spaced apart from the first light-emitting device and the second light-emitting device in a second direction intersecting the first direction. A first opening exposing at least a portion of the first electrode of the first light-emitting device, a second opening exposing at least a portion of the first electrode of the second light-emitting device, and a third opening exposing at least a portion of the first electrode of the third light-emitting device may be defined in the pixel defining film, and the plurality of connecting electrodes may include a first connecting electrode surrounding the first opening, a second connecting electrode surrounding the second opening, and a third connecting electrode surrounding the third opening.

[0056] The first region of the first light emitting device and the first region of the second light emitting device may be disposed between the first opening and the second opening, and may be spaced apart from each other in the second direction.

[0057] The multiple pixel drivers may include a first pixel driver electrically connected to the first light-emitting device, a second pixel driver electrically connected to the second light-emitting device, and a third pixel driver electrically connected to the third light-emitting device. A first through hole, a second through hole, and a third through hole may be defined in the pixel defining film, and the first connecting electrode may be electrically connected to the first pixel driver through the first through hole, the second connecting electrode may be electrically connected to the second pixel driver through the second through hole, and the third connecting electrode may be electrically connected to the third pixel driver through the third contact hole.

[0058] The first region of the first light emitting device may overlap with the first through hole, the first region of the second light emitting device may overlap with the second through hole, and the first region of the third light emitting device may overlap with the third through hole.

[0059] The first region of the first light emitting device may not overlap with the first through hole, the first region of the second light emitting device may not overlap with the second through hole, and the first region of the third light emitting device may overlap with the third through hole.

[0060] The first region of the first light emitting device or the first region of the second light emitting device may be adjacent to the first region of the third light emitting device in the second direction.

[0061] The multiple layers of the intermediate layer may include a first intermediate functional layer arranged on the first electrode, a light-emitting layer arranged on the first intermediate functional layer, and a second intermediate functional layer arranged on the light-emitting layer, and the first region of the intermediate layer may include the first intermediate functional layer and the second intermediate functional layer, and the second region of the intermediate layer may include the first intermediate functional layer, the light-emitting layer, and the second intermediate functional layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0063] Figure 1 is a schematic block diagram of a display device according to an embodiment of the present disclosure.

[0064] Figure 2A is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure.

[0065] Figure 2B is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure.

[0066] Figure 2C is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure.

[0067] Figure 3A is a schematic plan view illustrating a display panel according to an embodiment of the present disclosure.

[0068] Figure 3B is a schematic plan view illustrating a display panel according to an embodiment of the present disclosure.

[0069] Figure 4A is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0070] Figure 4B is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0071] Figure 4C is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0072] Figure 4D is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0073] Figure 4E is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0074] Figure 5 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0075] Figure 6A is an enlarged schematic cross-sectional view illustrating a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0076] Figure 6B is an image obtained by photographing a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0077] Figure 6C is an enlarged schematic cross-sectional view illustrating a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0078] Figure 7 is an enlarged schematic cross-sectional view illustrating a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0079] Figure 8 is an enlarged schematic cross-sectional view illustrating a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0080] Figure 9 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0081] Figure 10A is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0082] Figure 10B is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0083] Figure 11A is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0084] Figure 11B is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0085] Figure 12 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0086] In the following description, for the purpose of illustration, many specific details are set forth to provide a thorough understanding of the various embodiments or embodiments of the present disclosure. As used herein, "embodiment" and "embodiment" are interchangeable words that are non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, the various embodiments are not necessarily exclusive and do not necessarily limit the present disclosure. For example, the specific shape, configuration, and characteristics of the embodiment may be used or implemented in another embodiment.

[0087] Unless otherwise specified, the embodiments shown will be understood to provide features of the present disclosure. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0088] The use of cross hatching and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same figure numerals and / or figure numerals indicate the same elements.

[0089] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical, electrical and / or fluid connection with or without an intervening element. In addition, the X-axis (first direction DR1), the Y-axis (second direction DR2) and the Z-axis (third direction DR3) are not limited to the three axes of a rectangular coordinate system, such as the x-axis, the y-axis and the z-axis, and may be interpreted in a broader sense. For example, the X-axis (first direction DR1), the Y-axis (second direction DR2) and the Z-axis (third direction DR3) may be perpendicular to each other, or may be different directions that are not perpendicular to each other.

[0090] For the purposes of this disclosure, “at least one of A and B” may be interpreted as only A, only B, or any combination of A and B. Additionally, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0091] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0092] For descriptive purposes, spatially relative terms such as "under," "beneath," "beneath," "down," "over," "up," "above (throughout)," "higher," and "side" (e.g., in a "sidewall") may be used herein to describe the relationship of one element to another element (or elements) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the term "under" can encompass both "over" and "under" orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0093] The terms used in this document are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. In addition, when used in this specification, the terms "comprises, comprising" and / or "includes, including" illustrate the presence of stated features, wholes, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as terms of approximation rather than terms of degree, and therefore, are used to illustrate the inherent deviations of measurements, calculations and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0094] Various embodiments are described herein with reference to cross-sections and / or exploded views that are schematic illustrations of embodiments and / or intervening structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the particular shapes of the regions shown, but rather include deviations in shape due to, for example, manufacturing. In this manner, the regions shown in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore, are not necessarily intended to be limiting.

[0095] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings according to functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements and wiring connections, and these circuits can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, software (e.g., microcode) can be used to program and control them to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing certain functions and a processor performing other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, without departing from the scope of the present invention, each block, unit and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules.

[0096] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an ideal or overly formal sense.

[0097] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0098] Figure 1 is a schematic block diagram of a display device DD according to an embodiment of the present disclosure.

[0099] refer to Figure 1 The display device DD may include a display panel DP, a panel driver SDC, an EDC, and a DDC, a power supply PWS, and a timing controller TC. In an embodiment, the display panel DP may be described as a light-emitting display panel. Light-emitting display panels may include organic light-emitting display panels, inorganic light-emitting display panels, and quantum dot light-emitting display panels. In an embodiment, the organic light-emitting display panel will be described in detail as an example. The panel drivers SDC, EDC, and DDC may include a scan driver SDC, an emission driver EDC, and a data driver DDC.

[0100] The display panel DP may include scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm. The display panel DP may include a plurality of pixels (where m and n are integers greater than 1) connected to the scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, the emission lines ESL1 to ESLn, and the data lines DL1 to DLm.

[0101] For example, the pixel PXij (wherein, i can be an integer greater than or equal to 1 and less than or equal to n, and j can be an integer greater than or equal to 1 and less than or equal to m) located at the i-th horizontal line (or i-th pixel row) and the j-th vertical line (or j-th pixel column) can be connected to the i-th first scan line GWLi (or write scan line GWLi), the i-th second scan line GCLi (or compensation scan line GCLi), the i-th third scan line GILi (or first initialization scan line GILi), the i-th fourth scan line GBLi (or second initialization scan line GBLi), the i-th fifth scan line GRLi (or reset scan line GRLi), the j-th data line DLj and the i-th emission line ESLi.

[0102] The pixel PXij may include a plurality of light-emitting devices, a plurality of transistors, and a plurality of capacitors. The pixel PXij may receive a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VREF (or a reference voltage VREF), a fourth power supply voltage VINT1 (or a first initialization voltage VINT1), a fifth power supply voltage VINT2 (or a second initialization voltage VINT2), and a sixth power supply voltage VCOMP (or a compensation voltage VCOMP) through a power supply PWS.

[0103] The voltage values ​​of the first power supply voltage VDD and the second power supply voltage VSS can be set so that current can flow in the light emitting device to emit light. For example, the first power supply voltage VDD can be set to a voltage higher than the second power supply voltage VSS.

[0104] The third power supply voltage VREF may be a voltage for initializing the gate of the driving transistor included in the pixel PXij. The third power supply voltage VREF may be used to implement a grayscale (e.g., a predetermined or selectable grayscale) using a voltage difference between the third power supply voltage VREF and the data signal. To this end, the third power supply voltage VREF may be set to a voltage within the voltage range of the data signal (e.g., a predetermined or selectable voltage).

[0105] The fourth power supply voltage VINT1 may be a voltage for initializing a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be set to a voltage lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 may be set to a voltage lower than the difference (e.g., voltage difference) between the third power supply voltage VREF and the threshold voltage of the driving transistor. However, the present disclosure is not limited thereto.

[0106] The fifth power supply voltage VINT2 may be a voltage for initializing a cathode of a light emitting device included in a pixel PXij. The fifth power supply voltage VINT2 may be set to a voltage lower than the first power supply voltage VDD or the fourth power supply voltage VINT1, or may be set to a voltage close to or equal to the third power supply voltage VREF, but the present disclosure is not limited thereto, and the fifth power supply voltage VINT2 may also be set to a voltage close to or equal to the first power supply voltage VDD.

[0107] The sixth power supply voltage VCOMP may supply a current (eg, a predetermined or selectable current) to the driving transistor while compensating for a threshold voltage of the driving transistor.

[0108] Figure 1 Although the first power supply voltage VDD, the second power supply voltage VSS, the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP can all be supplied from the power supply PWS, the present disclosure is not limited thereto. For example, both the first power supply voltage VDD and the second power supply voltage VSS can be supplied regardless of the structure of the pixel PXij, and at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP can be not supplied to correspond to the structure of the pixel PXij.

[0109] In an embodiment of the present disclosure, signal lines connected to the pixels PXij may be variously set to correspond to the circuit structure of the pixels PXij.

[0110] The scan driver SDC may receive a first control signal SCS from the timing controller TC and may supply scan signals to the first to GWLn, second to GCL1 to GCLn, third to GIL1 to GILn, fourth to GBL1 to GBLn, and fifth to GRL1 to GRLn based on the first control signal SCS.

[0111] The scan signal may be set to a voltage at which a transistor receiving the scan signal may be turned on. For example, the scan signal supplied to the P-type transistor may be set to a logic low level, and the scan signal supplied to the N-type transistor may be set to a logic high level. Hereinafter, the wording "a scan signal may be supplied" may be understood as the scan signal may be supplied at a logic level at which a transistor controlled by the scan signal may be turned on.

[0112] exist Figure 1 , for ease of description, the scan driver SDC may be illustrated as a single component, but the present disclosure is not limited thereto. According to an embodiment, a plurality of scan drivers may be included to supply scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn.

[0113] The emission driver EDC may supply the emission signals to the emission lines ESL1 to ESLn based on the second control signal ECS. For example, the emission signals may be sequentially supplied to the emission lines ESL1 to ESLn.

[0114] The transistors connected to the emission lines ESL1 to ESLn according to the present disclosure may be N-type transistors. The emission signals supplied to the emission lines ESL1 to ESLn may be set to a gate-off voltage. The transistors receiving the emission signals may be turned off when the emission signals are supplied, and may be turned on otherwise.

[0115] The second control signal ECS may include a light emitting start signal and a clock signal, and the emission driver EDC may be implemented as a shift register that sequentially shifts the light emitting start signal in a pulse form using the clock signal to sequentially generate and output light emitting signals in a pulse form.

[0116] The data driver DDC may receive a third control signal DCS and image data RGB from the timing controller TC. The data driver DDC may convert the digital image data RGB into analog data signals (i.e., data signals). The data driver DDC may supply data signals to the data lines DL1 to DLm to correspond to the third control signal DCS.

[0117] The third control signal DCS may include a data enable signal instructing output of a valid data signal, a horizontal start signal, a data clock signal, etc. For example, the data driver DDC may include a shift register generating a sampling signal by shifting the horizontal start signal in synchronization with the data clock signal, a latch latching the image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) converting the latched image data RGB (e.g., data in digital form) into an analog data signal, and a buffer (or amplifier) ​​outputting the data signal to the data lines DL1 to DLm.

[0118] The power supply PWS may supply the display panel DP with first, second, and third power voltages VDD, VSS, and VREF for driving the pixels PXij. Furthermore, the power supply PWS may supply the display panel DP with at least one of fourth, fifth, and sixth power voltages VINT1, VINT2, and VCOMP.

[0119] For example, the power supply PWS may be connected to a first power line VDL (see FIG. Figure 2A ), the second power line VSL (see Figure 2A ), the third power line VRL (or reference voltage line VRL; see Figure 2A ), the fourth power line (or the first initialization voltage line VIL1; see Figure 2A ), the fifth power line (or the second initialization voltage line VIL2; see Figure 2A ) and the sixth power line (or compensation voltage line VCL; see Figure 2A ) supplies a first power voltage VDD, a second power voltage VSS, a third power voltage VREF, a fourth power voltage VINT1, a fifth power voltage VINT2 and a sixth power voltage VCOMP to the display panel DP.

[0120] The power supply PWS may be implemented as a power management integrated circuit, but the present disclosure is not limited thereto.

[0121] The timing controller TC can generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on input image data IRGB, synchronization signals Sync (e.g., vertical synchronization signals and horizontal synchronization signals), a data enable signal DE, and a clock signal. The first control signal SCS can be supplied to a scan driver SDC, the second control signal ECS can be supplied to an emission driver EDC, the third control signal DCS can be supplied to a data driver DDC, and the fourth control signal PCS can be supplied to a power supply PWS. The timing controller TC can rearrange the input image data IRGB to correspond to the arrangement of pixels PXij in the display panel DP to generate image data RGB (or frame data).

[0122] The scan driver SDC, emission driver EDC, data driver DDC, power supply PWS, and / or timing controller TC may be provided in the display panel DP or in the form of a separate driver chip and thus may be connected to the display panel DP. Furthermore, at least two of the scan driver SDC, emission driver EDC, data driver DDC, power supply PWS, and timing controller TC may be provided as one driver chip. For example, the data driver DDC and timing controller TC may be provided as one driver chip.

[0123] In the above, reference has been made to Figure 1 The display device DD according to the embodiment has been described, but the display device DD according to the present disclosure is not limited thereto. Signal lines may be further added or omitted depending on the configuration of the pixels. In addition, the connection relationship between a pixel and a signal line may be changed. If one of the signal lines can be omitted, the omitted signal line may be replaced with another signal line.

[0124] Figure 2A 、 Figure 2B and Figure 2C is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure. Figure 2A 、 Figure 2B and Figure 2C is a schematic diagram of an equivalent circuit of pixels PXij, PXij-1, and PXij-2 connected to the i-th first scan line GWLi (hereinafter, referred to as the first scan line GWLi) and the j-th data line DLj (hereinafter, referred to as the data line DLj).

[0125] like Figure 2A As shown in FIG, the pixel PXij includes a light emitting device LD and a pixel driver PDC. The light emitting device LD may be electrically connected to the first power line VDL and the pixel driver PDC.

[0126] The pixel driver PDC can be connected to the scan lines GWLi, GCLi, GILi, GBLi, and GRLi, the data line DLj, the i-th emission line ESLi, and the power supply voltage lines VDL, VSL, VIL1, VIL2, VRL, and VCL. The pixel driver PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, a first capacitor C1, and a second capacitor C2. Hereinafter, as an example, a case will be described in which the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may all be N-type transistors. However, the present disclosure is not limited thereto. Some of the first transistor T1 to the eighth transistor T8 may be N-type transistors, and the other transistors may be P-type transistors. All of the first transistor T1 to the eighth transistor T8 may be P-type transistors. The present disclosure is not limited to the embodiments.

[0127] The gate of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a second node N2, and the second electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power line VDL to the second power line VSL via the light emitting device LD in response to the voltage of the first node N1. The first power supply voltage VDD may be set to a voltage having a higher potential than the second power supply voltage VSS.

[0128] In the specification, the expression “electrically connected between a transistor and a signal line or between transistors” means “the source, drain, and gate of the transistor have an integral shape with the signal line or can be connected through a connection electrode”.

[0129] The second transistor T2 may include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to a write scan signal GW transmitted through the write scan line GWLi. The second transistor T2 may be turned on when the write scan signal GW is supplied to the write scan line GWLi, thereby electrically connecting the data line DLj and the first node N1.

[0130] The third transistor T3 may be connected between the first node N1 and the reference voltage line VRL. A first electrode of the third transistor T3 may receive a reference voltage VREF via the reference voltage line VRL, and a second electrode of the third transistor T3 may be connected to the first node N1. In an embodiment, a gate electrode of the third transistor T3 may receive a reset scan signal GR via an i-th fifth scan line GRLi (hereinafter referred to as the reset scan line GRLi). The third transistor T3 may be turned on when the reset scan signal GR is supplied to the reset scan line GRLi, and thus provide the reference voltage VREF to the first node N1.

[0131] The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. A first electrode of the fourth transistor T4 may be connected to the third node N3, and a second electrode of the fourth transistor T4 may be connected to the first initialization voltage line VIL1 that provides the first initialization voltage VINT1. The fourth transistor T4 may be referred to as a first initialization transistor. A gate of the fourth transistor T4 may receive a first initialization scan signal GI via an i-th third scan line GILi (hereinafter referred to as the first initialization scan line GILi). The fourth transistor T4 may be turned on when the first initialization scan signal GI is supplied to the first initialization scan line GILi, and supplies the first initialization voltage VINT1 to the third node N3.

[0132] The fifth transistor T5 may be connected between a compensation voltage line VCL and a second node N2. A first electrode of the fifth transistor T5 may receive a compensation voltage VCOMP via the compensation voltage line VCL, and a second electrode of the fifth transistor T5 may be connected to the second node N2 and electrically connected to the first electrode of the first transistor T1. A gate of the fifth transistor T5 may receive a compensation scan signal GC via an i-th second scan line GCLi (hereinafter referred to as the compensation scan line GCLi). The fifth transistor T5 may be turned on when the compensation scan signal GC is supplied to the compensation scan line GCLi and provide the compensation voltage VCOMP to the second node N2. Furthermore, the fifth transistor T5 may compensate for the threshold voltage of the first transistor T1 during a compensation period.

[0133] The sixth transistor T6 can be connected between the first transistor T1 and the light-emitting device LD. Specifically, the gate of the sixth transistor T6 can receive a light emission signal EM via an i-th emission line ESLi (hereinafter, referred to as the emission line ESLi). A first electrode of the sixth transistor T6 can be connected to the cathode of the light-emitting device LD via a fourth node N4, and a second electrode of the sixth transistor T6 can be connected to the first electrode of the first transistor T1 via a second node N2. The sixth transistor T6 can be referred to as a first light emission control transistor. When the light emission signal EM is supplied to the emission line ESLi, the sixth transistor T6 can be turned on, thereby electrically connecting the light-emitting device LD and the first transistor T1.

[0134] The seventh transistor T7 can be connected between the second power line VSL and the third node N3. A first electrode of the seventh transistor T7 can be connected to the second electrode of the first transistor T1 via the third node N3, and a second electrode of the seventh transistor T7 can receive the second power supply voltage VSS via the second power line VSL. The gate of the seventh transistor T7 can be electrically connected to the emission line ESLi. The seventh transistor T7 can be referred to as a second emission control transistor. When an emission signal EM is supplied to the emission line ESLi, the seventh transistor T7 can be turned on, thereby electrically connecting the second electrode of the first transistor T1 to the second power line VSL.

[0135] In the embodiment, it may be shown that the sixth transistor T6 and the seventh transistor T7 can be connected to the same emission line ESLi and can be turned on by the same emission signal EM, but this may be only an example, and the sixth transistor T6 and the seventh transistor T7 may be turned on independently by different signals that may be different from each other. In addition, in the embodiment of the present disclosure, in the pixel driver PDC, either the sixth transistor T6 or the seventh transistor T7 may be omitted.

[0136] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. The eighth transistor T8 may include a gate connected to the i-th fourth scan line GBLi (hereinafter referred to as the second initialization scan line GBLi), a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may supply a second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light-emitting device LD in response to a second initialization scan signal GB transmitted via the second initialization scan line GBLi. The cathode of the light-emitting device LD may be initialized by the second initialization voltage VINT2.

[0137] In an embodiment, some of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be turned on simultaneously by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 can be turned on simultaneously by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 can be operated by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 can be turned on / off simultaneously by the same compensation scan signal GC. The compensation scan line GCLi and the second initialization scan line GBLi can be basically provided as a single scan line. Therefore, the initialization of the cathode of the light-emitting device LD and the compensation of the threshold voltage of the first transistor T1 can be performed at the same timing. However, this may be merely an example, and the present disclosure is not limited to the embodiment.

[0138] Furthermore, according to the present disclosure, the cathode of the light-emitting device LD can be initialized and the threshold voltage of the first transistor T1 can be compensated by applying the same power supply voltage. For example, the compensation voltage line VCL and the second initialization voltage line VIL2 can be provided as a single power supply voltage line. A single power supply voltage can be used to initialize the cathode and compensate for the threshold voltage of the drive transistor, thereby simplifying the design of the driver portion. However, this is merely an example, and the present disclosure is not limited to this embodiment.

[0139] The first capacitor C1 may be provided between the first node N1 and the third node N3. The first capacitor C1 may store a voltage difference between a voltage of the first node N1 and a voltage of the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0140] The second capacitor C2 may be provided between the third node N3 and the second power line VSL. One electrode of the second capacitor C2 may be connected to the second power line VSL receiving the second power supply voltage VSS, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to the voltage difference between the second power supply voltage VSS and the voltage of the third node N3. The second capacitor C2 may be referred to as a holding capacitor. The second capacitor C2 may have a higher storage capacity than the first capacitor C1. Therefore, the second capacitor C2 may minimize changes in the voltage of the third node N3 in response to changes in the voltage of the first node N1.

[0141] In an embodiment, the light-emitting device LD may be connected to the pixel driver PDC via a fourth node N4. The light-emitting device LD may include an anode connected to the first power line VDL and a cathode corresponding to the anode. In an embodiment, the light-emitting device LD may be connected to the pixel driver PDC via the cathode. In a pixel PXij according to the present disclosure, the connection node via which the light-emitting device LD and the pixel driver PDC may be connected may be a fourth node N4, and the fourth node N4 may correspond to a connection node between the first electrode of the sixth transistor T6 and the cathode of the light-emitting device LD. Therefore, the potential of the fourth node N4 may substantially correspond to the potential of the cathode of the light-emitting device LD.

[0142] In detail, the anode of the light-emitting device LD can be connected to the first power line VDL to receive the first power supply voltage VDD, which can be a constant voltage, and the cathode of the light-emitting device LD can be connected to the first transistor T1 through the sixth transistor T6. In an embodiment where the first transistor T1 to the eighth transistor T8 can be N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which can be a driving transistor, can be unaffected by (e.g., directly affected by) the characteristics of the light-emitting device LD. Therefore, even in the case of deterioration of the light-emitting device LD, the impact on the gate-source voltage (Vgs) of the transistors (especially the driving transistor) constituting the pixel driver PDC can be reduced. Because the amount of change in the drive current caused by the deterioration of the light-emitting device LD can be reduced, the afterimage defect that occurs in the display panel over time can be reduced, and the life of the display panel can be improved.

[0143] like Figure 2B As shown in FIG, the pixel PXij-1 may include a pixel driver PDC-1 including two transistors T1 and T2 and a first capacitor C1. The pixel driver PDC-1 may be connected to the light emitting device LD, the write scan line GWLi, the data line DLj and the second power line VSL. Figure 2B The pixel driver PDC-1 shown in FIG may correspond to the pixel driver PDC-1 shown in FIG. Figure 2A Components of the third to eighth transistors T3 to T8 and the second capacitor C2 are omitted from the pixel driver PDC shown in FIG.

[0144] The first transistor T1 and the second transistor T2 may be N-type or P-type. In the embodiment, as an example, a case where the first transistor T1 and the second transistor T2 may be N-type transistors will be described.

[0145] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to the first power line VDL, and the third node N3 may be a node connected to the second power line VSL. The first transistor T1 may be connected to the light emitting device LD via the second node N2, and to the second power line VSL via the third node N3. The first transistor T1 may be a driving transistor.

[0146] The second transistor T2 may include a gate receiving a write scan signal GW through the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0147] The first capacitor C1 may include an electrode connected to the first node N1 and an electrode connected to the third node N3. The first capacitor C1 may store the data signal DATA transmitted to the first node N1.

[0148] The light emitting device LD may include an anode and a cathode. In an embodiment, the anode of the light emitting device LD may be connected to the first power line VDL, and the cathode of the light emitting device LD may be connected to the pixel driver PDC-1 via the second node N2. In an embodiment, the cathode of the light emitting device LD may be connected to the first transistor T1. The light emitting device LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driver PDC-1.

[0149] In an embodiment where the first transistor T1 and the second transistor T2 may be N-type transistors, the second node N2 through which the cathode of the light-emitting device LD and the pixel driver PDC-1 may be connected to each other may correspond to the drain of the first transistor T1. This prevents variations in the gate-source voltage (Vgs) of the first transistor T1 caused by the light-emitting device LD. Therefore, since variations in the drive current due to degradation of the light-emitting device LD can be reduced, afterimage defects that occur in the display panel over time can be reduced, and the lifespan of the display panel can be improved.

[0150] like Figure 2C As shown in FIG, the pixel PXij-2 may include a pixel driver PDC-2 including six transistors T1, T2, T3, T4a, T5a and T6a and two capacitors C1 and C2.

[0151] The pixel driver PDC-2 can be connected to the light emitting device LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first emission line ESL1i (hereinafter referred to as the first emission line ESL1i), the i-th second emission line ESL2i (hereinafter referred to as the second emission line ESL2i), the data line DLj, the first power line VDL, the second power line VSL, the third power line VRL and the initialization voltage line VIL.

[0152] Figure 2C The pixel driver PDC-2 shown in FIG can be similar to the pixel driver PDC-2 shown in FIG. Figure 2A The pixel driver PDC shown in FIG. 1 is configured to remove the fourth transistor T4 and the fifth transistor T5. Figure 2C The area of ​​the pixel driver PDC-2 shown in FIG can be smaller than Figure 2A The area of ​​the pixel driver PDC shown in is reduced, so high resolution can be achieved more easily.

[0153] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a may be an N-type or a P-type. In the embodiment, as an example, a case where each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a may be an N-type will be described.

[0154] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to the first power line VDL, and the third node N3 may be a node connected to the second power line VSL. The first transistor T1 may be connected to the light emitting device LD via the second node N2, and to the second power line VSL via the third node N3. The first transistor T1 may be a driving transistor.

[0155] The second transistor T2 may include a gate receiving a write scan signal GW through the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0156] The third transistor T3 may be connected between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 may receive a reference voltage VREF via the reference voltage line VRL, and a second electrode of the third transistor T3 may be connected to the first node N1. In an embodiment, a gate electrode of the third transistor T3 may receive a reset scan signal GR via a reset scan line GRLi. The third transistor T3 may be turned on when the reset scan signal GR is supplied to the reset scan line GRLi, thereby providing the reference voltage VREF to the first node N1.

[0157] The fourth transistor T4a can be connected between the first transistor T1 and the light-emitting device LD. Specifically, the gate of the fourth transistor T4a can receive the first light-emitting signal EM1 via the first emission line ESL1i. A first electrode of the fourth transistor T4a can be connected to the cathode of the light-emitting device LD via a fourth node N4, and a second electrode of the fourth transistor T4a can be connected to the first electrode of the first transistor T1 via a second node N2. The fourth transistor T4a can be referred to as a first light-emission control transistor. When the first light-emitting signal EM1 is supplied to the first emission line ESL1i, the fourth transistor T4a can be turned on, thereby electrically connecting the light-emitting device LD and the first transistor T1.

[0158] The fifth transistor T5a may be connected between the second power line VSL and the third node N3. A first electrode of the fifth transistor T5a may be connected to the second electrode of the first transistor T1 via the third node N3, and a second electrode of the fifth transistor T5a may receive the second power supply voltage VSS via the second power line VSL. A gate of the fifth transistor T5a may be electrically connected to the second emission line ESL2i. The fifth transistor T5a may be referred to as a second emission control transistor. When the second emission signal EM2 is supplied to the second emission line ESL2i, the fifth transistor T5a may be turned on, thereby electrically connecting the second electrode of the first transistor T1 to the second power line VSL.

[0159] In an embodiment, the fourth transistor T4a and the fifth transistor T5a can be connected to a first emission line ESL1i and a second emission line ESL2i that can be distinguished from each other, and can be turned on by a first emission signal EM1 and a second emission signal EM2 that can be distinguished from each other. The fourth transistor T4a and the fifth transistor T5a can be turned on independently of each other. However, this is merely an example, and the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the fourth transistor T4a and the fifth transistor T5a can be connected to the same emission line and can be controlled by the same emission signal. In addition, in an embodiment of the present disclosure, in the pixel driver PDC-2, either the fourth transistor T4a or the fifth transistor T5a can be omitted.

[0160] The sixth transistor T6a may be connected between the initialization voltage line VIL and the fourth node N4. The sixth transistor T6a may include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a may be referred to as an initialization transistor. The sixth transistor T6a may supply an initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light-emitting device LD in response to the compensation scan signal GC transmitted via the compensation scan line GCLi. The cathode of the light-emitting device LD may be initialized by the initialization voltage VINT.

[0161] The first capacitor C1 may be provided between the first node N1 and the third node N3. The first capacitor C1 may store a voltage difference between a voltage of the first node N1 and a voltage of the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0162] The second capacitor C2 may be provided between the third node N3 and the second power line VSL. One electrode of the second capacitor C2 may be connected to the second power line VSL receiving the second power supply voltage VSS, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to the voltage difference between the second power supply voltage VSS and the voltage of the third node N3. The second capacitor C2 may be referred to as a holding capacitor.

[0163] The light emitting device LD may include an anode and a cathode. In an embodiment, the anode of the light emitting device LD may be connected to the first power line VDL, and the cathode of the light emitting device LD may be connected to the pixel driver PDC-2 via a fourth node N4. In an embodiment, the cathode of the light emitting device LD may be connected to the first transistor T1 via a fourth transistor T4a. The light emitting device LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driver PDC-2.

[0164] In an embodiment where the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a may be N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which may be a driving transistor, may not be affected (e.g., directly affected) by the characteristics of the light-emitting device LD. Therefore, even if the light-emitting device LD degrades, the impact on the gate-source voltage (Vgs) of the transistors (particularly the driving transistor) constituting the pixel driver PDC-2 may be reduced. Because the amount of change in the drive current caused by the degradation of the light-emitting device LD is reduced, afterimage defects that occur in the display panel over time may be reduced, and the life of the display panel may be improved.

[0165] Figure 2A 、 Figure 2B and Figure 2C 1 and 2. The circuits for the pixel drivers PDC, PDC-1, and PDC-2 according to the embodiment of the present disclosure are shown. In the case where the pixel driver of the display panel according to the embodiment of the present disclosure may be a circuit connected to the cathode of the light-emitting device LD, the number or arrangement of transistors and the number or arrangement of capacitors may be designed differently and are not limited to the embodiment.

[0166] Figure 3A and Figure 3B 1 is a schematic plan view showing a display panel DP according to an embodiment of the present disclosure. Figure 3A and Figure 3B In the following, reference will be made to Figure 3A and Figure 3B The present disclosure is described.

[0167] refer to Figure 3A The display panel DP according to the embodiment may be divided into a display area DA and a peripheral area NDA (or a non-display area NDA). The display area DA may include a plurality of light emitting parts EP.

[0168] The light emitting portion EP may be a pixel PXij (see Figure 1 ) area where light is emitted. In detail, each of the light emitting portions EP may correspond to a light emitting opening OP-PDL (see Figure 5 ). The light emitting opening OP-PDL may be referred to as an opening or an opening portion.

[0169] The peripheral area NDA may be provided adjacent to the display area DA. In the embodiment, the peripheral area NDA may be shown to have a shape surrounding the edge of the display area DA. However, this may be merely an example, and the peripheral area NDA may be provided on one side of the display area DA or may be omitted, and the present disclosure is not limited to the embodiment.

[0170] In an embodiment, a scan driver SDC and a data driver DDC may be mounted on the display panel DP. In an embodiment, the scan driver SDC may be disposed in the display area DA, and the data driver DDC may be disposed in the peripheral area NDA. The scan driver SDC may overlap at least some of the light-emitting portions EP arranged in the display area DA in a plan view. Because the scan driver SDC may be disposed in the display area DA, the area of ​​the peripheral area NDA may be reduced compared to display panels according to related art in which the scan driver may be disposed in the peripheral area, and a display device with a thin bezel may be easily implemented.

[0171] and Figure 3AUnlike the illustration, the scan driver SDC may be provided as two different parts. The two scan drivers SDC may be spaced apart from each other in the left-right direction, with the center of the display area DA disposed between the two scan drivers SDC. The scan driver SDC may be provided as two or more scan drivers SDC, and the present disclosure is not limited to this embodiment.

[0172] Figure 3A An example of the display panel DP is shown, but the present disclosure is not limited thereto. In one or more embodiments, the data driver DDC may be disposed in the display area DA. Some of the light emitting portions EP arranged in the display area DA may overlap with the data driver DDC in a plan view.

[0173] In an embodiment, the data driver DDC may be provided in the form of a separate driver chip that is independent of and connected to the display panel DP. However, this may be merely an example, and the data driver DDC may be formed in the same process as the scan driver SDC to constitute the display panel DP, but the present disclosure is not limited to the embodiment.

[0174] like Figure 3B As shown in FIG, the length of the display panel DP in the first direction DR1 may be greater than the length of the display panel DP in the second direction DR2. It may be shown that a plurality of pixels PX11 to PXnm arranged in n rows and m columns may be arranged in the display area DA. In an embodiment, the display panel DP may include a plurality of scan drivers SDC1 and SDC2. It may be shown that the scan drivers SDC1 and SDC2 include a first scan driver SDC1 and a second scan driver SDC2 spaced apart from each other in the first direction DR1.

[0175] The first scan driver SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to the other scan lines GL1 to GLn. For example, the first scan driver SDC1 may be connected to odd-numbered scan lines among the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to even-numbered scan lines among the scan lines GL1 to GLn.

[0176] For ease of description, Figure 3B The pads PD of the data lines DL1 to DLm are shown. The pads PD may be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to the data driver DDC (see FIG. Figure 3A ).

[0177] According to the present disclosure, the pads PD may be divided and arranged at positions spaced apart from each other in the peripheral area NDA, with the display area DA provided between the pads PD. For example, some pads PD may be arranged on the upper side, i.e., on the side adjacent to the first scan line GL1 among the scan lines GL1 to GLn, and other pads PD may be arranged on the lower side, i.e., on the side adjacent to the last scan line GLn among the scan lines GL1 to GLn. In an embodiment, the pads PD connected to the odd-numbered data lines among the data lines DL1 to DLm may be arranged on the upper side, and the pads PD connected to the even-numbered data lines among the data lines DL1 to DLm may be arranged on the lower side.

[0178] Although not shown, the display panel DP may include a plurality of upper data drivers connected to the pads PD arranged on the upper side and / or a plurality of lower data drivers connected to the pads PD arranged on the lower side. However, this may be merely an example, and the display panel DP may further include one upper data driver connected to the pads PD arranged on the upper side and / or one lower data driver connected to the pads PD arranged on the lower side. The pads PD according to an embodiment of the present disclosure may be arranged only on one side of the display panel DP and connected to a single data driver, but the present disclosure is not limited to the embodiment.

[0179] In addition, if Figure 3A As shown in Figure 3B In the display panel DP, the scan driver and / or the data driver may also be arranged in the display area DA. Therefore, some of the light emitting parts arranged in the display area DA may overlap with the scan driver and / or the data driver in a plan view.

[0180] Figures 4A to 4E is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0181] Figure 4A The light emitting units UT11, UT12, UT21 and UT22 are shown in two rows and two columns. Figure 4A The light-emitting parts in the first row Rk include the light-emitting parts constituting the first row and first column light-emitting parts UT11 and the first row and second column light-emitting parts UT12, and the light-emitting parts in the second row Rk+1 include the light-emitting parts constituting the second row and first column light-emitting parts UT21 and the second row and second column light-emitting parts UT22.

[0182] Each of the light emitting portions EP1, EP2, and EP3 may correspond to a light emitting opening OP-PDL (see Figure 5). Each of the light emitting parts EP1, EP2, and EP3 may be a region in which light may be emitted by the light emitting device. The light emitting parts EP1, EP2, and EP3 may correspond to a region formed on the display panel DP (see Figure 1 ) In more detail, each of the light emitting portions EP1, EP2, and EP3 may correspond to an area defined by a light emitting opening OP-PDL to be described below, specifically, an area defined by a lower surface of the light emitting opening OP-PDL.

[0183] The light-emitting parts EP1, EP2, and EP3 may include a first light-emitting part EP1, a second light-emitting part EP2, and a third light-emitting part EP3. The first light-emitting part EP1, the second light-emitting part EP2, and the third light-emitting part EP3 may emit light having different colors. For example, the first light-emitting part EP1 may emit red light, the second light-emitting part EP2 may emit green light, and the third light-emitting part EP3 may emit blue light. However, the combination of colors is not limited thereto. In addition, at least two of the first light-emitting part EP1, the second light-emitting part EP2, and the third light-emitting part EP3 may emit light having the same color. For example, the first light-emitting part EP1, the second light-emitting part EP2, and the third light-emitting part EP3 may all emit blue light, or may emit white light.

[0184] Among the first, second, and third light-emitting parts EP1, EP2, and EP3, the third light-emitting part EP3, which displays light emitted by the third light-emitting device, may include two sub-light-emitting parts EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is an example, and the third light-emitting part EP3 may be provided as a pattern having the same integral shape as the first and second light-emitting parts EP1, EP2, and at least one of the first and second light-emitting parts EP1, EP2, and EP3a, wherein the sub-light-emitting parts are spaced apart from each other. However, the present disclosure is not limited to this embodiment. Similarly, among the first, second, and third light-emitting parts EP1, EP2, and EP3a, the third light-emitting part EP3a, which displays light emitted by the third light-emitting device, may include two sub-light-emitting parts EP32 and EP31 spaced apart from each other in the second direction DR2. However, this is an example, and the present disclosure is not limited to this embodiment.

[0185] The light-emitting parts in the first row Rk may include the first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3 constituting the first row and first column light-emitting part UT11 and the first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3a constituting the first row and second column light-emitting part UT12, and the light-emitting parts in the second row Rk+1 may include the first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3a constituting the second row and first column light-emitting part UT21 and the first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3 constituting the second row and second column light-emitting part UT22.

[0186] In the embodiment of the present disclosure, the shape of the light-emitting portion constituting the first row and first column light-emitting unit UT11 can be substantially the same as the shape of the light-emitting portion constituting the second row and second column light-emitting unit UT22. Furthermore, the shape of the light-emitting portion constituting the first row and second column light-emitting unit UT12 can be substantially the same as the shape of the light-emitting portion constituting the second row and first column light-emitting unit UT21. The shape of the light-emitting portion constituting the first row and first column light-emitting unit UT11 can be different from the shape of the light-emitting portion constituting the first row and second column light-emitting unit UT12. For example, some light-emitting portions in the first row Rk and some light-emitting portions in the second row Rk+1 can have symmetrical shapes.

[0187] In an embodiment of the present disclosure, the third light emitting portion EP3a of the second row and first column light emitting portion UT21 and the third light emitting portion EP3 of the first row and first column light emitting portion UT11 may have shapes and arrangements that are line-symmetrical with respect to an axis parallel to the first direction DR1, and the third light emitting portion EP3 of the second row and second column light emitting portion UT22 and the third light emitting portion EP3a of the first row and second column light emitting portion UT12 may have shapes and arrangements that are line-symmetrical with respect to an axis parallel to the first direction DR1. However, this is exemplary and the present disclosure is not limited thereto.

[0188] Figure 4B The light emitting parts are arranged in a row. Figure 4B A plurality of second electrodes EL2_1 , EL2_2 , and EL2_3 , a plurality of pixel drivers PDC1 , PDC2 , and PDC3 , first to third connection electrodes CNE1 , CNE2 , and CNE3 , and a spacer SPR are shown. Figure 4C 1 and 2. The display panel includes a spacer SPR, light emitting parts EP1, EP2, and EP3 arranged in regions partitioned by the spacer SPR (see FIG. 1 ). Figure 4B ) and connecting electrodes CNE1, CNE2 and CNE3.

[0189] refer to Figure 4B and Figure 4C , the second electrodes EL2_1, EL2_2, and EL2_3 can be separated from each other and electrically disconnected by a separator SPR. In an embodiment, one light-emitting unit UT11 may include three light-emitting parts EP1, EP2, and EP3. Therefore, the light-emitting unit UT11 may include three second electrodes EL2_1, EL2_2, and EL2_3 (hereinafter referred to as a first cathode EL2_1, a second cathode EL2_2, and a third cathode EL2_3), three pixel drivers PDC1, PDC2, and PDC3, and three connection electrodes CNE1, CNE2, and CNE3. However, this is merely an example, and the number and arrangement of the light-emitting parts included in the light-emitting unit UT11 may be designed differently, and the present disclosure is not limited to the embodiment.

[0190] The first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be electrically connected to the first light emitting device LD1, the second light emitting device LD2, and the third light emitting device LD3 including the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3, respectively. In the specification, the wording "connected" includes not only a case of physical connection through direct contact but also a case of electrical connection.

[0191] In addition, if Figure 4B As shown in FIG, the area where the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be defined in a plan view may correspond to the pixel driver PDCs in which the light emitting devices constituting the pixels for driving the pixels can be repeatedly arranged (see FIG. Figure 2A ) of the transistor and capacitor components.

[0192] The first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be sequentially arranged in the first direction DR1. The arrangement positions of the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be independently designed regardless of the positions or shapes of the first light emitting part EP1, the second light emitting part EP2, and the third light emitting part EP3.

[0193] For example, the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be arranged in an area separated and defined by the partition SPR, that is, they can be arranged in a position different from the position where the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 are arranged, or can be designed to have a shape and area different from the shape and area of ​​the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3. The first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be arranged in an area that can be arranged to overlap with the position where the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 are located, and can be separated and defined by the partition SPR, for example, they can be designed to have a shape and area similar to the shape and area of ​​the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3.

[0194] In an embodiment, the first pixel driver PDC1, the second pixel driver PDC2 and the third pixel driver PDC3 can be shown in a rectangular shape, the first light-emitting portion EP1, the second light-emitting portion EP2 and the third light-emitting portion EP3 can be arranged in an area smaller than the area of ​​the first pixel driver PDC1, the second pixel driver PDC2 and the third pixel driver PDC3 and have a shape different from the shapes of the first pixel driver PDC1, the second pixel driver PDC2 and the third pixel driver PDC3, and the first cathode EL2_1, the second cathode EL2_2 and the third cathode EL2_3 can be arranged at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2 and the third light-emitting portion EP3 and shown in an irregular shape.

[0195] Therefore, if Figure 4B As shown in the figure, the first pixel driver PDC1 can be set at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2 and another adjacent light-emitting portion (adjacent multiple light-emitting portions). The second pixel driver PDC2 can be set at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2 and the third cathode EL2_3. The third pixel driver PDC3 can be set at a position overlapping with the third light-emitting portion EP3. As shown, the positions of the first pixel driver PDC1, the second pixel driver PDC2 and the third pixel driver PDC3 can be designed in various shapes and arrangements independently of the light-emitting portions EP1, EP2 and EP3, but the present disclosure is not limited to the embodiments.

[0196] The light emitting unit UT11 may include a first connection electrode CNE1, a second connection electrode CNE2, and a third connection electrode CNE3. The first connection electrode CNE1 may electrically connect the first light emitting device LD1 forming the first light emitting portion EP1 (or the first light emitting portion EP1 may be defined therein) to the first pixel driver PDC1, the second connection electrode CNE2 may electrically connect the second light emitting device LD2 forming the second light emitting portion EP2 to the second pixel driver PDC2, and the third connection electrode CNE3 may electrically connect the third light emitting device LD3 forming the third light emitting portion EP3 to the third pixel driver PDC3.

[0197] In detail, the first, second, and third connection electrodes CNE1, CNE2, and CNE3 may electrically connect the first, second, and third cathodes EL2_1, EL2_2, and EL2_3 with the first, second, and third pixel drivers PDC1, PDC2, and PDC3 in one-to-one correspondence.

[0198] The first, second, and third connection electrodes CNE1, CNE2, and CNE3 may be disposed on a pixel defining layer PDL (see FIG. Figure 5 ). The first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may have a ring shape surrounding the corresponding first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3. In the embodiment of the present disclosure, each of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 is shown as having a closed-line ring (or closed) shape, but the present disclosure is not limited thereto. For example, at least some of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may have an open ring shape with disconnected portions.

[0199] Because the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can have a ring shape, the degree of freedom of the portion where the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 are connected to the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be improved. For example, the first connection electrode CNE1 can be connected to the first pixel driver PDC1 via the first connection portion CE1, the second connection electrode CNE2 can be connected to the second pixel driver PDC2 via the second connection portion CE2, and the third connection electrode CNE3 can be connected to the third pixel driver PDC3 via the connection wiring line CN3. The connection wiring line that is separately connected to the first connection electrode CNE1 and the second connection electrode CNE2 can be omitted.

[0200] A connection wiring line CN3 can electrically connect the third pixel driver PDC3 and the third light emitting device LD3 constituting the third light emitting part EP3. In detail, the connection wiring line CN3 can correspond to the light emitting device LD (see Figure 2A ) can be connected to the pixel driver ( Figure 2A Pixel driver PDC, Figure 2B Pixel driver PDC-1 or Figure 2C pixel driver PDC-2) node (see Figure 2A The fourth node N4, Figure 2B The second node N2 or Figure 2C The fourth node N4).

[0201] The connection wiring line CN3 may include a third connection portion CE3 and a driver connection portion CD3. The third connection portion CE3 may be provided on one side of the connection wiring line CN3, and the driver connection portion CD3 may be provided on the other side of the connection wiring line CN3.

[0202] The driver connection portion CD3 may be a portion of the connection wiring line CN3 connected to the third pixel driver PDC3. In an embodiment, the driver connection portion CD3 may be connected to an electrode of a transistor constituting the third pixel driver PDC3. In detail, the driver connection portion CD3 may be connected to Figure 2A The drain of the sixth transistor T6 shown in FIG. Figure 2B The drain of the first transistor T1 shown in Figure 2C . The drain of the fourth transistor T4a shown in FIG. Therefore, the position of the driver connection portion CD3 may correspond to the position of the transistor physically connected to the connection wiring line CN3 in the pixel driver. The third connection portion CE3 may be the portion of the connection wiring line CN3 connected to the third light-emitting device LD3. In an embodiment, the third connection portion CE3 may be connected to the third connection electrode CNE3.

[0203] The first connection electrode CNE1 may include a first edge EG11 surrounding at least a portion of the first light emitting portion EP1 and a second edge EG12 surrounding the first edge EG11. The second connection electrode CNE2 may include a first edge EG21 surrounding at least a portion of the second light emitting portion EP2 and a second edge EG22 surrounding the first edge EG21. The third connection electrode CNE3 may include a first edge EG31 surrounding at least a portion of the third light emitting portion EP3 and a second edge EG32 surrounding the first edge EG31.

[0204] The first, second, and third connection electrodes CNE1, CNE2, and CNE3 may be spaced apart from each other. For example, gaps GP1, GP2, and GP3 between adjacent connection electrodes among the first, second, and third connection electrodes CNE1, CNE2, and CNE3 may overlap with the spacer SPR. For example, first edges EG11, EG21, and EG31 of the first, second, and third connection electrodes CNE1, CNE2, and CNE3 may not be covered by the spacer SPR, and second edges EG12, EG22, and EG32 of the first, second, and third connection electrodes CNE1, CNE2, and CNE3 may overlap with the spacer SPR. Second edges EG12, EG22, and EG32 of the first, second, and third connection electrodes CNE1, CNE2, and CNE3 may be covered by the spacer SPR.

[0205] In an embodiment of the present disclosure, the first connection portion CE1, the second connection portion CE2, and the third connection portion CE3 may be arranged at a position where the first connection portion CE1, the second connection portion CE2, and the third connection portion CE3 may not overlap with the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 in a plan view. For example, the light emitting opening OP-PDL (see Figure 5 ) and the through hole OP-P spaced apart from the light emitting opening OP-PDL (see Figure 5 ) can be defined in the pixel definition layer PDL.

[0206] The through hole OP-P may include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first connection portion CE1, the second connection portion CE2, and the third connection portion CE3 may be arranged to correspond to the first through hole OP-P1, the second through hole OP-P2, and the third through hole OP-P3, respectively. The light-emitting opening OP-PDL may include a first light-emitting opening OP-PDL1, a second light-emitting opening OP-PDL2, and a third light-emitting opening OP-PDL3. The first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 may be defined to correspond to the first light-emitting opening OP-PDL1, the second light-emitting opening OP-PDL2, and the third light-emitting opening OP-PDL3, respectively. Therefore, the first connection portion CE1, the second connection portion CE2, and the third connection portion CE3 may be arranged at a position spaced apart from the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3.

[0207] The first link electrode CNE1, the second link electrode CNE2, and the third link electrode CNE3 may be disposed on a pixel defining layer PDL (see Figure 5In a plan view, the first connection electrode CNE1 may surround the first light emitting opening OP-PDL1, the second connection electrode CNE2 may surround the second light emitting opening OP-PDL2, and the third connection electrode CNE3 may surround the third light emitting opening OP-PDL3.

[0208] According to an embodiment of the present disclosure, the connection wiring line CN3 can be connected to the transistor TR of the third pixel driver PDC3 (see Figure 5 ) may be defined at a position that does not overlap with the third connection portion CE3 and overlaps with the third light emitting portion EP3 in a plan view. For example, the connection wiring line CN3 may correspond to Figure 9 The connection wiring line CN-ad shown in FIG. 1 , the driver connection portion CD3 may correspond to the connection wiring line CN-ad shown in FIG. Figure 9 The portion of the intermediate connection electrode CN shown in FIG. 1 may contact the intermediate connection electrode CN, and the third connection portion CE3 may correspond to the portion of the intermediate connection electrode CN shown in FIG. Figure 9 Because the third cathode EL2_3 and the third pixel driver PDC3 can be connected through the connection wiring line CN3, when designing the third pixel driver PDC3, restrictions on the position or shape of the third light emitting part EP3 can be reduced, and thus the degree of freedom can be improved.

[0209] The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively. For example, the lower surfaces of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be connected to (or in contact with) the upper surfaces of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively. Therefore, the contact reliability (or connection stability) between the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 and the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can be further improved.

[0210] In addition, the connection region in which the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can surround at least a portion of the first light emitting opening OP-PDL1, the second light emitting opening OP-PDL2, and the third light emitting opening OP-PDL3. The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 and the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can be connected in a region adjacent to the separator SPR, and each of the contact regions can be defined as being adjacent to the separator SPR. The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 and the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can be connected not at a specific point but over a relatively large region, for example, in a region having a shape similar to that of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3. The area of ​​the connection region increases, and thus connection can be performed stably.

[0211] Figure 4D The light emitting parts EP1, EP2 and EP3 (see FIG. Figure 4B ), connecting electrodes CNE1, CNE2 and CNE3 and multiple intermediate layers IML1, IML2 and IML3.

[0212] refer to Figure 4C and Figure 4D , also refer to Figure 1 and Figure 4B The intermediate layers IML1, IML2 and IML3 may be separated from each other by separators SPR. The intermediate layers IML1, IML2 and IML3 may include a first cathode EL2_1 and a first electrode EL1 (see Figure 4E ), a first intermediate layer IML1 disposed between the second cathode EL2_2 and the first electrode EL1, a second intermediate layer IML2 disposed between the second cathode EL2_2 and the first electrode EL1, and a third intermediate layer IML3 disposed between the third cathode EL2_3 and the first electrode EL1.

[0213] The first intermediate layer IML1 may include a first functional layer FNL1 having a first area and a first light-emitting layer EML1 having a second area that may be smaller than the first area. The second intermediate layer IML2 may include a second functional layer FNL2 having a third area and a second light-emitting layer EML2 having a fourth area that may be smaller than the third area. The third intermediate layer IML3 may include a third functional layer FNL3 having a fifth area and a third light-emitting layer EML3 having a sixth area that may be smaller than the fifth area.

[0214] The first functional layer FNL1, the second functional layer FNL2, and the third functional layer FNL3 can be formed by being deposited in common in the pixel through an open mask. The first functional layer FNL1, the second functional layer FNL2, and the third functional layer FNL3 can be divided by a separator SPR. The separator SPR can have a closed line shape for each light-emitting portion, and therefore, the first functional layer FNL1, the second functional layer FNL2, and the third functional layer FNL3 can have a divided shape for each light-emitting portion. Each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 can be formed by being deposited in the corresponding pixel through a fine metal mask. Therefore, at least a portion of each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may not overlap with the separator SPR or be spaced apart from the separator SPR.

[0215] According to an embodiment of the present disclosure, at least a portion of a first edge EG11 of the first connection electrode CNE1 may not overlap with the first light-emitting layer EML1 and may be spaced apart from the edge EG1 of the first light-emitting layer EML1. At least a portion of a first edge EG21 of the second connection electrode CNE2 may not overlap with the second light-emitting layer EML2 and may be spaced apart from the edge EG2 of the second light-emitting layer EML2. At least a portion of a first edge EG31 of the third connection electrode CNE3 may not overlap with the third light-emitting layer EML3 and may be spaced apart from the edge EG3 of the third light-emitting layer EML3.

[0216] Unlike the embodiment of the present disclosure, if portions of the first, second, and third connection electrodes CNE1, CNE2, and CNE3 that may not be covered by the separator SPR and may be exposed and covered by the first, second, and third light-emitting layers EML1, EML2, and EML3, the contact stability between the first, second, and third cathodes EL2_1, EL2_2, and EL2_3 and the first, second, and third connection electrodes CNE1, CNE2, and CNE3 may deteriorate. According to the embodiment of the present disclosure, at least a portion of the first, second, and third connection electrodes CNE1, CNE2, and CNE3 may not overlap with the first, second, and third light-emitting layers EML1, EML2, and EML3. This allows for stable coverage of the exposed areas of the first, second, and third connection electrodes CNE1, CNE2, and CNE3. Therefore, the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be stably connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively, and thus, the contact reliability can be improved. As a result, the appearance defects caused by the contact defects, such as the spot defects found when the lamp is turned on, can be reduced or eliminated. The display panel DP and the display device DD including the display panel DP (see Figure 1 ) image quality or manufacturing yield.

[0217] According to an embodiment of the present disclosure, the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may overlap with the first light-emitting opening OP-PDL1, the second light-emitting opening OP-PDL2, and the third light-emitting opening OP-PDL3, respectively. Furthermore, the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may not overlap with the first through hole OP-P1, the second through hole OP-P2, and the third through hole OP-P3, respectively. The first functional layer FNL1, the second functional layer FNL2, and the third functional layer FNL3 may overlap with the first light-emitting opening OP-PDL1, the second light-emitting opening OP-PDL2, and the third light-emitting opening OP-PDL3, respectively, and may overlap with the first through hole OP-P1, the second through hole OP-P2, and the third through hole OP-P3, respectively. Thus, the first functional layer FNL1 may overlap with at least a portion of the first edge EG11 of the first connection electrode CNE1, the second functional layer FNL2 may overlap with at least a portion of the first edge EG21 of the second connection electrode CNE2, and the third functional layer FNL3 may overlap with at least a portion of the first edge EG31 of the third connection electrode CNE3.

[0218] The first intermediate layer IML1 may include a first area AR11 and a second area AR12 adjacent to the first area AR11. The second intermediate layer IML2 may include a first area AR21 and a second area AR22 adjacent to the first area AR21. The third intermediate layer IML3 may include a first area AR31 and a second area AR32 adjacent to the first area AR31. For example, the first areas AR11, AR21, and AR31 may be areas in which some of the multiple layers constituting the first intermediate layer IML1, the second intermediate layer IML2, and the third intermediate layer IML3 may be arranged, and the second areas AR12, AR22, and AR32 may be areas in which all of the layers constituting the first intermediate layer IML1, the second intermediate layer IML2, and the third intermediate layer IML3 may be arranged.

[0219] In an embodiment of the present disclosure, the first light emitting device LD1 including the first light emitting portion EP1 and the second light emitting device LD2 including the second light emitting portion EP2 may be spaced apart from each other in the second direction DR2. The third light emitting device LD3 including the third light emitting portion EP3 may be spaced apart from the first light emitting device LD1 and the second light emitting device LD2 in the first direction DR1.

[0220] In an embodiment of the present disclosure, the first area AR11 of the first light emitting device LD1 and the first area AR21 of the second light emitting device LD2 may be arranged between the first light emitting opening OP-PDL1 and the second light emitting opening OP-PDL2. The first area AR11 of the first light emitting device LD1 and the first area AR21 of the second light emitting device LD2 may be spaced apart from each other in the first direction DR1. The first area AR11 of the first light emitting device LD1 may overlap with the first through hole OP-P1, the first area AR21 of the second light emitting device LD2 may overlap with the second through hole OP-P2, and the first area AR31 of the third light emitting device LD3 may overlap with the third through hole OP-P3.

[0221] Figure 4E The separator SPR, the light emitting parts EP1 , EP2 and EP3 , and the first electrode EL1 are shown.

[0222] refer to Figure 4E , also refer to Figure 3A , the light emitting device LD according to the embodiment of the present disclosure (see Figure 5The first electrode EL1 (hereinafter referred to as the anode EL1) of the light emitting device LD may be commonly provided to the first light emitting part EP1, the second light emitting part EP2, and the third light emitting part EP3. The anode EL1 and the entire display area DA may be integrated with each other, and therefore, the layer of the anode EL1 may be provided to overlap with the partition SPR. The anodes EL1 of the light emitting device LD may be formed as independent conductive patterns spaced apart from each other and may be electrically connected to each other through another conductive layer, and therefore, the pattern in the anode EL1 may be arranged so as not to overlap with the partition SPR.

[0223] As mentioned above, the first power supply voltage VDD (see Figure 2A ) may be applied to the anode EL1, and a common voltage may be applied to all light emitting portions. The anode EL1 may be connected to a first power line VDL (see FIG. 1 ) that provides a first power supply voltage VDD in the peripheral area NDA. Figure 2A ) or connected to the first power line VDL in the display area DA (see Figure 2A ), but the present disclosure is not limited to the embodiments.

[0224] A plurality of openings may be defined in the anode EL1 according to the embodiment, and the openings may pass through the layer of the anode EL1. The openings in the layer of the anode EL1 may be arranged so as not to overlap with the light emitting portion EP (see FIG. 1 ). Figure 3A ) and may be generally defined at a position overlapping with the separator SPR. The opening may facilitate discharge of electric current from an organic layer (eg, a sixth insulating layer 60 (see FIG. 1 ) to be described below) disposed below the anode EL1. Figure 5 )) generated. Therefore, in the process of manufacturing the display panel, the gas in the organic layer provided below the light-emitting device can be fully discharged, and after manufacturing, the gas discharged from the organic layer can be reduced, and thus the degradation rate of the light-emitting device can be reduced.

[0225] Figure 5 is a schematic cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Figure 6A FIG. 1 is a diagram showing a display panel DP (see FIG. 2 ) according to an embodiment of the present disclosure. Figure 5 ) is an enlarged schematic cross-sectional view of a partial area. Figure 6B is an image obtained by photographing a partial area of ​​the display panel DP according to an embodiment of the present disclosure. Figure 6C is an enlarged schematic cross-sectional view illustrating a partial area of ​​the display panel DP according to an embodiment of the present disclosure.

[0226] Figure 5 is shown with Figure 4A Schematic cross-sectional view of the portion corresponding to line II'. Figure 6A yes Figure 5An enlarged schematic cross-sectional view of a portion AA' of Figure 6B It is through shooting Figure 6A The image is obtained from a partial area. Figure 6C yes Figure 5 Hereinafter, reference will be made to Figures 5 to 6C The present disclosure is described.

[0227] refer to Figure 5 and Figure 6A The display panel DP according to the embodiment may include a base layer BS, a driving device layer DDL, a light emitting device layer LDL, an encapsulation layer ECL, and a sensing layer ISL. However, this is only an example, and in the embodiment of the present disclosure, the display panel DP may not include the sensing layer ISL.

[0228] The driving device layer DDL may include a plurality of insulating layers 10, 20, 30, 40, 50, and 60 disposed on the base layer BS and a plurality of conductive patterns and a plurality of semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60. The conductive patterns and the semiconductor patterns may be disposed between the insulating layers 10, 20, 30, 40, 50, and 60 to constitute a pixel driver PDC. For ease of description, Figure 5 A cross section of one of the regions where a light emitting portion may be provided is shown.

[0229] The base layer BS may be a member that provides a base surface, and the pixel driver PDC may be disposed on the base surface. The base layer BS may be a rigid substrate or a flexible substrate that can be bent, folded, and rolled. The base layer BS may be a glass substrate, a metal substrate, a polymer substrate, or the like. However, the embodiments of the present disclosure are not limited thereto, and the base layer BS may also be an inorganic layer, an organic layer, or a composite material layer.

[0230] The base layer BS may have a multi-layer structure. The base layer BS may include a first polymer resin layer, a silicon oxide (SiO x ) layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a substrate barrier layer.

[0231] The polymer resin layer may include a polyimide resin. Furthermore, the polymer resin layer may include at least one of an acrylate resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a polyurethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In the specification, an "XYZ-based" resin refers to a resin containing an "XYZ" functional group.

[0232] The insulating layer, conductive layer, and semiconductor layer disposed on the base layer BS may be formed by methods such as coating and deposition. Thereafter, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned through multiple photolithography processes, thereby forming holes in the insulating layer or forming semiconductor patterns, conductive patterns, signal lines, and the like therein.

[0233] The driving device layer DDL may include first, second, third, fourth, fifth, and sixth insulating layers 10 , 20 , 30 , 40 , 50 , and 60 and a pixel driver PDC sequentially stacked on the base layer BS. Figure 5 One transistor TR and two capacitors C1 and C2 of the pixel driver PDC are shown.

[0234] The transistor TR may correspond to a transistor connected to the light emitting device LD through the intermediate connection electrode CN and the connection electrode CNE, that is, connected to a node ( ) corresponding to the cathode of the light emitting device LD. Figure 2A The fourth node N4, Figure 2B The second node N2 or Figure 2C In detail, the transistor TR may correspond to the fourth node N4 of the transistor. Figure 2A The sixth transistor T6, Figure 2B The first transistor T1 or Figure 2C Although not shown, other transistors constituting the pixel driver PDC may have the same Figure 5 The structure of the transistor TR (hereinafter referred to as the connection transistor TR) shown in FIG. However, this may be just an example, and other transistors constituting the pixel driver PDC may have a different structure from the connection transistor TR, and the present disclosure is not limited to the embodiment.

[0235] The first insulating layer 10 may be provided on the base layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may be shown as a single silicon oxide layer. The insulating layer to be described below may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but the present disclosure is not limited thereto.

[0236] The first insulating layer 10 may cover the bottom conductive layer BCL. The display panel DP may further include a bottom conductive layer BCL disposed to overlap with the connection transistor TR. The bottom conductive layer BCL may prevent the potential caused by polarization of the base layer BS from affecting the connection transistor TR. Furthermore, the bottom conductive layer BCL may block light from entering the connection transistor TR from the bottom side. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the bottom conductive layer BCL and the base layer BS.

[0237] The bottom conductive layer BCL may include a reflective metal and a metal nitride. For example, the bottom conductive layer BCL may include titanium (Ti), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), etc., or a combination thereof.

[0238] In an embodiment, the bottom conductive layer BCL can be connected to the source of the transistor TR (or transistor TR) through the source electrode pattern W1. The bottom conductive layer BCL can be synchronized with the source of the transistor TR. However, this is only an example, and the bottom conductive layer BCL can be connected to the gate of the transistor TR and synchronized with the gate. The bottom conductive layer BCL can be connected to another electrode to independently receive a constant voltage or pulse signal. The bottom conductive layer BCL can be provided in a form isolated from other conductive patterns. The bottom conductive layer BCL according to an embodiment of the present disclosure can be provided in various forms and is not limited to the embodiment.

[0239] The connection transistor TR may be provided on the first insulating layer 10. The connection transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be provided on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. For example, the oxide semiconductor may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), or a combination thereof. However, the present disclosure is not limited thereto, and the semiconductor pattern SP may include amorphous silicon, polycrystalline silicon (such as low-temperature polysilicon), or a combination thereof.

[0240] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR, each distinguishable by its degree of conductivity. The channel region CR may be a portion overlapping the gate electrode GE in a plan view. The source region SR and the drain region DR may be spaced apart from each other, with the channel region CR disposed therebetween. If the semiconductor pattern SP is an oxide semiconductor, the source region SR and the drain region DR may be reduced regions. Therefore, the source region SR and the drain region DR may have a relatively high reduced metal content compared to the channel region CR. If the semiconductor pattern SP is polycrystalline silicon, the source region SR and the drain region DR may be regions doped at a high concentration.

[0241] The source region SR and the drain region DR may have relatively higher conductivity than that of the channel region CR. The source region SR may correspond to a source electrode of the connection transistor TR, and the drain region DR may correspond to a drain electrode of the connection transistor TR. Figure 5 As shown in FIG, a separate source electrode pattern W1 and a separate drain electrode pattern W2 connected to the source region SR and the drain region DR, respectively, may be further provided. In detail, the separate source electrode pattern W1, the separate drain electrode pattern W2 and the pixel driver ( Figure 2A PDC, Figure 2B PDC-1 or Figure 2C One of the lines of PDC-2) may be integrated with each other, and the present disclosure is not limited thereto.

[0242] The second insulating layer 20 may overlap with the pixels and cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the second insulating layer 20 may be a single silicon oxide layer or a combination thereof.

[0243] The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate of the connection transistor TR. In addition, the gate electrode GE may also be disposed on the semiconductor pattern SP. However, this may be merely an example, and the gate electrode GE may be disposed below the semiconductor pattern SP, and the present disclosure is not limited to this embodiment.

[0244] The gate electrode GE may include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), alloys thereof, or combinations thereof, but the present disclosure is not particularly limited thereto.

[0245] The third insulating layer 30 may be provided on the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The third insulating layer 30 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, or a combination thereof.

[0246] The first and second capacitor electrodes CPE1 and CPE2 among the conductive patterns W1, W2, CPE1, CPE2, and CPE3 constitute a first capacitor C1. The first and second capacitor electrodes CPE1 and CPE2 may be spaced apart from each other with the first and second insulating layers 10 and 20 disposed therebetween.

[0247] In an embodiment of the present disclosure, the first capacitor electrode CPE1 and the bottom conductive layer BCL may also have an integral shape. In addition, the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape.

[0248] The third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2, with the third insulating layer 30 disposed between the third capacitor electrode CPE3 and the second capacitor electrode CPE2. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 may overlap in a plan view. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 may constitute a second capacitor C2.

[0249] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, or a combination thereof.

[0250] A source electrode pattern W1 and a drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to the source region SR of the connection transistor TR through a first contact hole CNT1, and the source electrode pattern W1 and the source region SR of the semiconductor pattern SP may function as the source of the connection transistor TR. The drain electrode pattern W2 may be connected to the drain region DR of the connection transistor TR through a second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP may function as the drain of the connection transistor TR. A fifth insulating layer 50 may be disposed on the source electrode pattern W1 and the drain electrode pattern W2.

[0251] The intermediate connection electrode CN may be provided on the fifth insulating layer 50. The intermediate connection electrode CN may electrically connect the pixel driver PDC and the light emitting device LD. The intermediate connection electrode CN may electrically connect the connection transistor TR and the light emitting device LD. The intermediate connection electrode CN may be a connection node connecting the pixel driver PDC and the light emitting device LD. The intermediate connection electrode CN may correspond to Figure 2A The fourth node N4 shown in Figure 2A ), corresponding to Figure 2B The second node N2 shown in Figure 2B ), or corresponding to Figure 2C The fourth node N4 shown in Figure 2C ).

[0252] The sixth insulating layer 60 may be disposed on the intermediate connecting electrode CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover at least a portion of the intermediate connecting electrode CN. The fifth insulating layer 50 and the sixth insulating layer 60 may be organic layers. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), a general polymer such as polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer (such as polyimide), an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and blends thereof.

[0253] A through-hole OP-60 may be provided in the sixth insulating layer 60, and at least a portion of the intermediate connection electrode CN may be exposed through the through-hole OP-60. The intermediate connection electrode CN may be connected to the connection electrode CNE via its portion exposed from the sixth insulating layer 60, and may be electrically connected to the light-emitting device LD. The intermediate connection electrode CN, together with the connection electrode CNE, may electrically connect the connection transistor TR and the light-emitting device LD. In the display panel DP according to an embodiment of the present disclosure, the sixth insulating layer 60 may be omitted, or may be provided as a plurality of sixth insulating layers 60, but the present disclosure is not limited to this embodiment. If the sixth insulating layer 60 is omitted, the intermediate connection electrode CN may be omitted.

[0254] The intermediate connection electrode CN may include a first layer L1, a second layer L2, and a third layer L3 that may be sequentially stacked in the third direction DR3. The second layer L2 may include a material that may be different from the material of the first layer L1. In addition, the second layer L2 may include a material that may be different from the material of the third layer L3. The second layer L2 may have a thickness that is relatively greater than that of the first layer L1. In addition, the second layer L2 may have a thickness that is relatively greater than that of the third layer L3. The second layer L2 may include a material having high electrical conductivity. In an embodiment, the second layer L2 may include aluminum (Al).

[0255] The light emitting device layer LDL may be disposed on the driving device layer DDL. The light emitting device layer LDL may include a pixel defining layer PDL, a light emitting device LD, and a spacer SPR.

[0256] The pixel defining layer (PDL) may be an organic layer. For example, the pixel defining layer (PDL) may include BCB, HMDSO, PMMA, a general polymer such as PS, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer (such as polyimide), an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and blends thereof.

[0257] In an embodiment, the pixel defining film (PDL) may have a light-absorbing property and may have, for example, a black color. The pixel defining film (PDL) may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal (such as chromium) or an oxide thereof. The pixel defining film (PDL) may correspond to a light-blocking pattern having light-blocking properties.

[0258] An opening OP-PDL (hereinafter, referred to as a light emitting opening OP-PDL) may be defined in the pixel defining film PDL, and at least a portion of the first electrode EL1 to be described below may be exposed through the opening OP-PDL. The light emitting opening OP-PDL may be provided as a plurality of light emitting openings OP-PDL that may be arranged to correspond to the light emitting devices, respectively. All components of the light emitting device LD may be arranged to overlap with the light emitting opening OP-PDL, and the light emitting opening OP-PDL may be an area on which light emitted by the light emitting device LD may be substantially displayed. Therefore, the first light emitting portion EP1 (see Figure 4A ) may substantially correspond to the shape of the light emitting opening OP-PDL in a plan view.

[0259] The connection electrode CNE may be provided on the pixel definition film PDL. The connection electrode CNE may electrically connect the pixel driver PDC and the light emitting device LD. The pixel driver PDC may be electrically connected to the light emitting device LD via the intermediate connection electrode CN and the connection electrode CNE. The connection electrode CNE may correspond to Figure 4A The first connection electrode CNE1 is shown in FIG. The second connection electrode CNE2 (see FIG. Figure 4A ) and the third connection electrode CNE3 (see Figure 4A ) may also have a structure similar to that of the connecting electrode CNE.

[0260] The connection electrode CNE may include a first edge EG1c that may be adjacent to the light emitting opening OP-PDL and a second edge EG2c surrounding the first edge EG1c. The second electrode EL2 of the light emitting device LD may contact the connection electrode CNE in a region adjacent to the second edge EG2c.

[0261] The connection electrode CNE may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), or a combination thereof. However, the material constituting the connection electrode CNE is not limited to the above examples.

[0262] A through hole OP-P spaced apart from the light-emitting opening OP-PDL may be defined in the pixel-defining film PDL. A plurality of through holes OP-P may be provided and arranged to correspond to the light-emitting devices. The size of the through hole OP-P defined in the pixel-defining film PDL may be larger than the size of the through hole OP-60 defined in the sixth insulating layer 60. A connection electrode CNE may be provided in the through hole OP-P and the through hole OP-60 and may be connected to the intermediate connection electrode CN.

[0263] The light emitting device LD may include a first electrode EL1 , an intermediate layer IML, and a second electrode EL2 .

[0264] The first electrode EL1 may be a semi-transmissive, transmissive, or reflective electrode. According to an embodiment of the present disclosure, the first electrode EL1 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), compounds thereof, or combinations thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 may include a stacked structure of ITO / Ag / ITO.

[0265] In an embodiment, the first electrode EL1 may be an anode of the light emitting device LD. The first electrode EL1 may be connected to a first power line VDL (see Figure 2A ), and the first power supply voltage VDD (see Figure 2A ) may be applied to the first electrode EL1. The first electrode EL1 may be applied to the display area DA (see Figure 3A or Figure 3B ) is internally connected to the first power line VDL or is connected to the first power line VDL in the peripheral area NDA. In the latter, the first power line VDL may be provided in the peripheral area NDA (see Figure 3A or Figure 3B ), and the first electrode EL1 may have a shape extending up to the peripheral area NDA.

[0266] exist Figure 5 In the schematic cross-sectional view of , it is shown that the first electrode EL1 overlaps with the light emitting opening OP-PDL and does not overlap with the partition SPR. Figure 4E As shown in , the first electrode EL1 of the light emitting device may have an integral shape and may have a mesh or lattice shape in which an opening may be defined in a partial area thereof. In the case where the same first power supply voltage VDD is applied to the first electrode EL1 of each of the light emitting devices, the shape of the first electrode EL1 may be provided differently, and the present disclosure is not limited to the embodiment.

[0267] The intermediate layer IML may be provided between the first electrode EL1 and the second electrode EL2. The intermediate layer IML may include a light-emitting layer EML and a functional layer FNL. The light-emitting device LD may include the intermediate layer IML having various structures, and the present disclosure is not limited to the embodiments. For example, the functional layer FNL may be provided as a plurality of layers or as two or more layers spaced apart from each other, with the light-emitting layer EML provided between the plurality of layers.

[0268] The light emitting layer EML may include an organic light emitting material. In addition, the light emitting layer EML may include an inorganic light emitting material, or may be provided as a mixed layer of an organic light emitting material and an inorganic light emitting material. In an embodiment, the light emitting layer EML may include an organic light emitting material and an inorganic light emitting material. Figure 3A ) may include a light-emitting material that displays a different color. For example, the light-emitting layer EML included in each of the light-emitting portions EP may provide any one of blue light, red light, and green light. However, the present disclosure is not limited thereto, and all the light-emitting layers EML arranged in the light-emitting portion EP may include a light-emitting material that displays the same color. The light-emitting layer EML may provide blue light or white light.

[0269] The functional layer FNL can be disposed between the first electrode EL1 and the second electrode EL2. Specifically, the functional layer FNL can include a first intermediate functional layer FNLa disposed between the first electrode EL1 and the light-emitting layer EML, and a second intermediate functional layer FNLb disposed between the second electrode EL2 and the light-emitting layer EML. In embodiments of the present disclosure, one of the first intermediate functional layer FNLa and the second intermediate functional layer FNLb can be omitted. In embodiments, the light-emitting layer EML is shown as being inserted into the functional layer FNL. It is understood that the light-emitting layer EML can be disposed between the first intermediate functional layer FNLa and the second intermediate functional layer FNLb.

[0270] The functional layer FNL can control the movement of charge between the first electrode EL1 and the second electrode EL2. For example, the first intermediate functional layer FNLa may include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer FNLb may include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0271] The second electrode EL2 may be disposed on the intermediate layer IML. As described above, the second electrode EL2 may be connected to the connection electrode CNE and electrically connected to the pixel driver PDC. The second electrode EL2 may be electrically connected to the connection transistor TR through the connection electrode CNE.

[0272] The spacer SPR may be provided on the pixel defining layer PDL. In addition, the spacer SPR may be provided on the gap GP between the connection electrode CNE provided on the pixel defining layer PDL and the adjacent connection electrode CNEn adjacent to the connection electrode CNE.

[0273] In an embodiment, the second electrode EL2 and the functional layer FNL may be formed by being deposited in common in the pixel through an open mask. The second electrode EL2 and the functional layer FNL may be divided by a separator SPR. As described above, the separator SPR may have a closed line shape for each light emitting portion, and thus, the second electrode EL2 and the functional layer FNL may have a divided shape for each light emitting portion. The second electrode EL2 and the intermediate layer IML may be electrically independent for each adjacent pixel.

[0274] refer to Figure 5 、 Figure 6A and Figure 6B , the spacer SPR may have a double reverse tapered shape. A tapered angle is formed between the upper surface of the pixel defining film PDL and the first side surface TP1 of the spacer SPR, and a tapered angle is formed between the upper surface of the pixel defining film PDL and the second side surface TP2 of the spacer SPR. The tapered angle may be an obtuse angle. For example, referring to Figure 6B, a tapered angle formed between the upper surface of the pixel defining film PDL and the first side surface TP1 may be smaller than a tapered angle formed between the upper surface of the pixel defining film PDL and the second side surface TP2 .

[0275] In an embodiment of the present disclosure, the connection area BDA between the first and second side surfaces TP1 and TP2 may have a curved shape in cross section. The connection area BDA between the first and second side surfaces TP1 and TP2 having different tapered angles may have a rounded shape with a gradually changing slope.

[0276] In an embodiment of the present disclosure, since the second side surface TP2 has a tapered angle that may be greater than the tapered angle of the first side surface TP1, a space (e.g., a predetermined or selectable space) may be defined between the second side surface TP2 of the separator SPR and the connection electrode CNEn. The second electrode EL2n may have a shape extending toward the space (e.g., a predetermined or selectable space).

[0277] However, Figure 6A The shape of the spacer SPR shown in FIG is shown only as an example, and the tapered angle may be set differently as long as the spacer SPR can electrically disconnect the second electrode EL2 for each pixel. In addition, the spacer SPR may have the same structure as that of the tip portion, but the present disclosure is not limited to the embodiment.

[0278] In an embodiment, the spacer SPR may include an insulating material, and in particular, may include an organic insulating material. According to an embodiment, the spacer SPR may include an inorganic insulating material, may include a multilayer structure of an organic insulating material and an inorganic insulating material, and may include a conductive material. As long as the second electrode EL2 can be electrically disconnected for each pixel, the type of material of the spacer SPR is not particularly limited.

[0279] The dummy layer UP may be provided on the separator SPR. The dummy layer UP may include a first dummy layer UP1 provided on the separator SPR and a second dummy layer UP2 provided on the first dummy layer UP1. The first dummy layer UP1 may be formed by the same process as the intermediate layer IML and include the same material as the intermediate layer IML. The first dummy layer UP1 may include a (1-1)th dummy layer UP1a and a (1-2)th dummy layer UP1b. The (1-1)th dummy layer UP1a may be formed by the same process as the first intermediate functional layer FNLa and may include the same material as the first intermediate functional layer FNLa. The (1-2)th dummy layer UP1b may be formed by the same process as the second intermediate functional layer FNLb and include the same material as the second intermediate functional layer FNLb. The second dummy layer UP2 may be formed by the same process as the second electrode EL2 and include the same material as the second electrode EL2. The first and second dummy layers UP1 and UP2 may be formed simultaneously while the functional layer FNL and the second electrode EL2 may be formed. In an embodiment, the display panel DP may not include the dummy layer UP.

[0280] refer to Figure 5 、 Figure 6A and Figure 6C , the intermediate layer IML may include a first area AR1 and a second area AR2. For example, the first area AR1 may be an area including only layers formed by the open mask among the layers constituting the intermediate layer IML, and the second area AR2 may be an area including all layers formed by the open mask and layers formed by the fine metal mask among the layers constituting the intermediate layer IML.

[0281] For example, the first area AR1 may include a first intermediate functional layer FNLa and a second intermediate functional layer FNLb. The second area AR2 may include the first intermediate functional layer FNLa, the second intermediate functional layer FNLb, and the light-emitting layer EML. Therefore, the first thickness TK1 of the first area AR1 of the intermediate layer IML may be less than the second thickness TK2 of the second area AR2 of the intermediate layer IML. A portion of the boundary between the first area AR1 and the second area AR2 may not overlap with the connection electrode CNE and may be spaced apart from the first edge EG1c of the connection electrode CNE. Therefore, the edge EG of the light-emitting layer EML, which is included only in the second area AR2, may be spaced apart from the first edge EG1c.

[0282] refer to Figure 6A, the first area AR1 of the intermediate layer IML is shown on the right side relative to the separator SPR, and the second area AR2n of the adjacent intermediate layer is shown on the left side. When comparing the left and right sides of the separator SPR, it can be seen that the size of the area where the connection electrode CNE can be exposed at the portion adjacent to the first area AR1 can be larger than the size of the area where the connection electrode CNEn can be exposed at the portion adjacent to the second area AR2n.

[0283] The second electrode EL2 may be in contact with the connection electrode CNE through the connection area CA. The second electrode EL2n may be in contact with the connection electrode CNEn through the connection area CAn. Since the layer formed by the fine metal mask (for example, the light emitting layer EML) may be formed so as not to overlap with a portion of the connection electrode CNE, an exposed area may be stably ensured at the portion of the connection electrode CNE, and the contact reliability between the connection electrode CNE and the second electrode EL2 may be improved. Therefore, spot defects caused by contact defects may be reduced or removed. As a result, the display panel DP and the display device DD including the display panel DP (see Figure 1 ) image quality or manufacturing yield.

[0284] According to an embodiment of the present disclosure, the connection electrode CNE has a structure surrounding the light emitting portion EP1 defined in the light emitting device LD (see FIG. Figure 4A ) shape of at least a portion of the intermediate connection electrode CN. Therefore, the degree of freedom of the position where the connection electrode CNE and the light-emitting device LD can be connected to each other, as well as the degree of freedom of the position where the connection electrode CNE and the pixel driver PDC can be connected to each other, can be improved. In addition, the upper surface CNE-us of the connection electrode CNE can be in contact with the lower surface EL2-bs of the second electrode EL2 of the light-emitting device LD. This can improve the contact reliability between the connection electrode CNE and the second electrode EL2. In addition, the lower surface of the connection electrode CNE and the upper surface of the intermediate connection electrode CN can be in contact with each other, thereby improving the contact reliability. Therefore, the size of the through holes OP-P and OP-60 used to connect the connection electrode CNE and the intermediate connection electrode CN can be reduced or minimized. Therefore, the area or resolution of the light-emitting portion of the display panel DP can be easily increased.

[0285] refer to Figure 5 , the encapsulation layer ECL may be disposed on the light-emitting device layer LDL. The encapsulation layer ECL may cover the light-emitting device LD and the spacer SPR. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2, which may be sequentially stacked. However, the present disclosure is not limited thereto, and the encapsulation layer ECL may also include multiple inorganic layers and multiple organic layers. In addition, the encapsulation layer ECL may be a glass substrate.

[0286] The first inorganic layer IL1 and the second inorganic layer IL2 can protect the light-emitting device LD from moisture and oxygen outside the display panel DP, and the organic layer OL can protect the light-emitting device LD from foreign matter such as particles remaining in the process of forming the first inorganic layer IL1. The first inorganic layer IL1 and the second inorganic layer IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like, or a combination thereof. The organic layer OL may include an acrylic organic layer, and the type of material is not limited to any one.

[0287] The sensing layer ISL may sense external input. In an embodiment, the sensing layer ISL may be formed on the encapsulation layer ECL through a subsequent process. The sensing layer ISL may be disposed (e.g., directly disposed) on the encapsulation layer ECL. Directly disposed may mean that there may be no components between the sensing layer ISL and the encapsulation layer ECL. No separate adhesive member may be disposed between the sensing layer ISL and the encapsulation layer ECL. However, this is merely an example, and in the display panel DP according to an embodiment of the present disclosure, the sensing layer ISL may be formed separately and then coupled to the display panel DP through an adhesive member, but the present disclosure is not limited to the embodiment.

[0288] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The conductive layer may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the insulating layer may include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73. However, this is merely an example, and the number of conductive layers and insulating layers is not limited to the embodiment.

[0289] The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have a single-layer structure or a multi-layer structure in which multiple layers may be stacked in the third direction DR3. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an organic film. The organic film may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a polyurethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0290] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have a single-layer structure or a multi-layer structure in which a plurality of layers may be stacked in the third direction DR3.

[0291] The sensing conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, alloys thereof, or combinations thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium zinc tin oxide (IZTO), or combinations thereof. The transparent conductive layer may include a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires, or graphene.

[0292] The sensing conductive layer having a multi-layer structure may include a metal layer. For example, the metal layer may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). The sensing conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0293] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may constitute a sensor for sensing an external input in the sensing layer ISL. The sensor may be driven using a capacitive method, and may be driven using either a mutual capacitance method or a self-capacitive method. However, this is merely an example, and in addition to the capacitive method, the sensor may also be driven using a resistive film method, an ultrasonic method, or an infrared method, but the present disclosure is not limited to this embodiment.

[0294] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide, or may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have various materials and various shapes as long as the visibility of the image displayed by the display panel DP is not degraded, and the present disclosure is not limited to the embodiments.

[0295] Figure 7 is an enlarged schematic cross-sectional view showing a partial area of ​​a display panel according to an embodiment of the present disclosure. For example, Figure 7 is with Figure 5 An enlarged schematic cross-sectional view of a region corresponding to region AA'.

[0296] refer to Figure 5 and Figure 7The display panel DP may further include a lower encapsulation layer IL-ad. The lower encapsulation layer IL-ad may be disposed between the pixel defining layer PDL and the spacer SPR. In embodiments where the lower encapsulation layer IL-ad is applicable, a portion of the connection electrode CNE may be disposed on the lower encapsulation layer IL-ad. The lower encapsulation layer IL-ad may be an inorganic layer.

[0297] Even if a gap is formed in the first inorganic layer IL1 in a portion adjacent to the side surface of the spacer SPR, the gap can be shielded by the lower encapsulation layer IL-ad. Therefore, even if the gap serves as an exhaust path or moisture permeation path for organic materials that may be included in the insulating layer 50 and / or 60, gas and moisture can be shielded by the lower encapsulation layer IL-ad. Therefore, the protection function of protecting the light-emitting device LD can be improved, and thus, the reliability of the display panel DP can be improved.

[0298] Figure 8 is an enlarged schematic cross-sectional view showing a partial area of ​​a display panel according to an embodiment of the present disclosure. For example, Figure 8 is with Figure 5 An enlarged schematic cross-sectional view of a region corresponding to region AA'.

[0299] refer to Figure 5 and Figure 8 , the first encapsulation layer IL1a can be used instead Figure 5 The first inorganic layer IL1 is shown in FIG. The first encapsulation layer IL1a may include a plurality of sub-encapsulation layers ILs1, ILs2, and ILs3. Therefore, the first encapsulation layer IL1a can relatively smoothly cover the spacer SPR. Therefore, a gap formed adjacent to the side surface of the spacer SPR can be removed from the upper surface of the first encapsulation layer IL1a. Therefore, the protective function of the encapsulation layer for protecting the light-emitting device LD can be improved.

[0300] In an embodiment of the present disclosure, the first encapsulation layer IL1a may include a first sub-encapsulation layer ILs1, a second sub-encapsulation layer ILs2, and a third sub-encapsulation layer ILs3. The first sub-encapsulation layer ILs1 may cover the separator SPR. The second sub-encapsulation layer ILs2 may be provided on the first sub-encapsulation layer ILs1. The third sub-encapsulation layer ILs3 may be provided on the second sub-encapsulation layer ILs2. However, this is merely an example, and some of the sub-encapsulation layers constituting the first encapsulation layer IL1a may be omitted, or more sub-encapsulation layers may be included.

[0301] In an embodiment of the present disclosure, at least some of the first sub-encapsulation layer ILs1, the second sub-encapsulation layer ILs2, and the third sub-encapsulation layer ILs3 may include an organic material. For example, the first sub-encapsulation layer ILs1 and the third sub-encapsulation layer ILs3 may include an inorganic material, and the second sub-encapsulation layer ILs2 may include an organic material. Even in the case where a gap is formed in the first sub-inorganic layer ILs1 in a portion adjacent to the side surface of the partition SPR, the gap may be filled by the second sub-encapsulation layer ILs2. For example, the first sub-encapsulation layer ILs1 and the third sub-encapsulation layer ILs3 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or a combination thereof. The second sub-encapsulation layer ILs2 may include silicon oxycarbide (SiOC x ). However, the present disclosure is not particularly limited thereto.

[0302] Figure 9 is a schematic cross-sectional view of a display panel DP-1 according to an embodiment of the present disclosure. Figure 9 is shown with Figure 4A A schematic cross-sectional view of the portion corresponding to line II'. Figure 9 In the description of Figure 5 The same components as those described in may be denoted by the same reference numerals, and description thereof will be omitted.

[0303] refer to Figure 9 The display panel DP-1 may further include a connection wiring line CN-ad disposed between the sixth insulating layer 60 and the pixel defining layer PDL. The connection wiring line CN-ad may be connected to the intermediate connection electrode CN through a through-hole OP-60, and at least a portion of the intermediate connection electrode CN may be exposed through the through-hole OP-60.

[0304] In an embodiment of the present disclosure, the connection wiring line CN-ad and the first electrode EL1 may be provided on the same layer. For example, the connection wiring line CN-ad and the first electrode EL1 may have the same material and the same layer structure. Furthermore, the connection wiring line CN-ad may be formed using the same process as the first electrode EL1. However, this is merely an example, and the present disclosure is not limited thereto. For example, the connection wiring line CN-ad may include a different material than the first electrode EL1 and may be formed using a different process than the first electrode EL1.

[0305] A through hole OP-Pa may be defined in the pixel defining layer PDL. The through hole OP-Pa and the through hole OP-60 may not overlap each other, but the present disclosure is not particularly limited to this. For example, the through hole OP-Pa and the through hole OP-60 may overlap each other. The connection electrode CNEa may be disposed within the through hole OP-Pa. The connection electrode CNEa may be connected to the portion of the connection wiring line CN-ad exposed by the through hole OP-Pa.

[0306] Figure 10A is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0307] refer to Figure 10A , it can be seen that a region in which a total of four light-emitting sections UT11a, UT12, UT21, and UT22a can be arranged in two rows and two columns. The light-emitting portion in the first row Rk includes the light-emitting portion constituting the first-row, first-column light-emitting section UT11a and the first-row, second-column light-emitting section UT12, and the light-emitting portion in the second row Rk+1 includes the light-emitting portion constituting the second-row, first-column light-emitting section UT21 and the second-row, second-column light-emitting section UT22a.

[0308] In the embodiment of the present disclosure, the shapes of the light emitting parts included in the four light emitting units UT11a, UT12, UT21, and UT22a may be substantially the same. Therefore, the light emitting parts having the same shape may be repeatedly arranged in the first direction DR1 and the second direction DR2.

[0309] Figure 10B is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure. Figure 10B Shown Figure 10A Some components of the display panel, for example, the light emitting parts EP1, EP2, EP31 and EP32, the connection electrodes CNE1, CNE2 and CNE3, and the intermediate layers IML1, IML2 and IML3.

[0310] refer to Figure 10B The intermediate layers IML1, IML2 and IML3 may be separated from each other by separators SPR. The intermediate layers IML1, IML2 and IML3 may include a cathode EL2_1 (see Figure 4B ) and the first electrode EL1 (see Figure 4E ) between the first intermediate layer IML1, provided at the second cathode EL2_2 (see Figure 4B ) and the second intermediate layer IML2 between the first electrode EL1 and the third cathode EL2_3 (see Figure 4B ) and a third intermediate layer IML3 between the first electrode EL1.

[0311] The first intermediate layer IML1 may include a first functional layer FNL1 having a first area and a first light-emitting layer EML1 having a second area that may be smaller than the first area. The second intermediate layer IML2 may include a second functional layer FNL2 having a third area and a second light-emitting layer EML2 having a fourth area that may be smaller than the third area. The third intermediate layer IML3 may include a third functional layer FNL3 having a fifth area and a third light-emitting layer EML3 having a sixth area that may be smaller than the fifth area.

[0312] According to an embodiment of the present disclosure, at least a portion of a first edge EG11 of the first connection electrode CNE1 may not overlap with the first light-emitting layer EML1 and may be spaced apart from the edge EG1 of the first light-emitting layer EML1. At least a portion of a first edge EG21 of the second connection electrode CNE2 may not overlap with the second light-emitting layer EML2 and may be spaced apart from the edge EG2 of the second light-emitting layer EML2. At least a portion of a first edge EG31 of the third connection electrode CNE3 may not overlap with the third light-emitting layer EML3 and may be spaced apart from the edge EG3 of the third light-emitting layer EML3.

[0313] According to an embodiment of the present disclosure, at least a portion of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may not overlap with the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3. The area of ​​the exposed area of ​​the first connection electrode CNE1, the area of ​​the exposed area of ​​the second connection electrode CNE2, and the area of ​​the exposed area of ​​the third connection electrode CNE3 can be stably ensured. Therefore, the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be stably connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively, and thus the contact reliability can be improved. Therefore, the appearance defects caused by contact defects, such as the spot defects found when the light is turned on, can be reduced or eliminated. The display panel DP (see Figure 1 ) and a display device DD including a display panel DP (see Figure 1 ) image quality or manufacturing yield.

[0314] Figure 11A is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0315] refer to Figure 11A , also refer to Figure 4A and Figure 4B , shows a region in which a total of four light emitting portions UT11b, UT12b, UT21b, and UT22b can be arranged in two rows and two columns.

[0316] In the embodiment of the present disclosure, the shape of the light-emitting portion constituting the first row, first column light-emitting unit UT11b can be substantially the same as the shape of the light-emitting portion constituting the second row, second column light-emitting unit UT22b. Furthermore, the shape of the light-emitting portion constituting the first row, second column light-emitting unit UT12b can be substantially the same as the shape of the light-emitting portion constituting the second row, first column light-emitting unit UT21b. The shape of the light-emitting portion constituting the first row, first column light-emitting unit UT11b can be different from the shape of the light-emitting portion constituting the first row, second column light-emitting unit UT12b. For example, some light-emitting portions in the first row Rk and some light-emitting portions in the second row Rk+1 can have symmetrical shapes.

[0317] In an embodiment of the present disclosure, the third light emitting portion EP3a of the second row and first column light emitting portion UT21b and the third light emitting portion EP3 of the first row and first column light emitting portion UT11b may have shapes and arrangements that are line-symmetrical with respect to an axis parallel to the first direction DR1, and the third light emitting portion EP3 of the second row and second column light emitting portion UT22b and the third light emitting portion EP3a of the first row and second column light emitting portion UT12b may have shapes and arrangements that are line-symmetrical with respect to an axis parallel to the first direction DR1. However, this is exemplary and the present disclosure is not limited thereto.

[0318] In an embodiment of the present disclosure, a portion of the separator SPRa may be deformed so that the first to third cathodes EL2_1 , EL2_2 , and EL2_3 may be stably connected to the first to third connection electrodes CNE1 , CNE2 , and CNE3 .

[0319] For example, the portion PR1 of the separator SPRa surrounding the first light emitting portion EP1 of each of the first-row, first-column light emitting portion UT11b and the second-row, second-column light emitting portion UT22b may have a shape that protrudes toward the third connection portion CE3 of each of the first-row, first-column light emitting portion UT11b and the second-row, second-column light emitting portion UT22b. The portion PR1a of the separator SPRa surrounding the first light emitting portion EP1 of the first-row, second-column light emitting portion UT12b may have a shape that protrudes toward the third connection portion CE3 of the first-row, first-column light emitting portion UT11b. The portion PR2 of the separator SPRa surrounding the second light emitting portion EP2 of the first-row, second-column light emitting portion UT12b may have a shape that protrudes toward the third connection portion CE3 of the first-row, second-column light emitting portion UT12b. The portion PR2a of the separator SPRa surrounding the second light emitting portion EP2 of the second-row, second-column light emitting portion UT22b may have a shape that protrudes toward the third connection portion CE3 of the second-row, first-column light emitting portion UT21b.

[0320] The third light-emitting portion EP3 may include two sub-light-emitting portions EP31 and EP32 spaced apart from each other in the second direction DR2. The partition SPRa surrounding the third light-emitting portion EP3 may have a closed line shape. The region of the third light-emitting portion EP3 defined by the partition SPRa surrounding the first row, first column light-emitting portion UT11b may be defined as a main region having a first width WT1 and a protruding region having a second width WT2. The second width WT2 may be smaller than the first width WT1. The protruding region may be provided between the protruding portion PR1 of the partition SPRa surrounding the first row, first column light-emitting portion UT11b and the protruding portion PR1a of the partition SPRa surrounding the first row, second column light-emitting portion UT12b.

[0321] Figure 11B is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure. Figure 11B Shown Figure 11A Some components of the display panel, for example, the light emitting parts EP1, EP2, EP31 and EP32, the connection electrodes CNE1a, CNE2a and CNE3a, and the plurality of intermediate layers IML1a, IML2a and IML3a.

[0322] refer to Figure 11A and Figure 11B The first intermediate layer IML1a, the second intermediate layer IML2a, and the third intermediate layer IML3a may be separated from each other by the separator SPRa. The first intermediate layer IML1a, the second intermediate layer IML2a, and the third intermediate layer IML3a may be arranged on the first electrode EL1 (see Figure 12 ) and the corresponding second electrode EL2 (see Figure 12 )between.

[0323] The first intermediate layer IML1a may include a first functional layer FNL1a having a first area and a first light-emitting layer EML1a having a second area that may be smaller than the first area. The second intermediate layer IML2a may include a second functional layer FNL2a having a third area and a second light-emitting layer EML2a having a fourth area that may be smaller than the third area. The third intermediate layer IML3a may include a third functional layer FNL3a having a fifth area and a third light-emitting layer EML3a having a sixth area that may be smaller than the fifth area.

[0324] The first connection electrode CNE1a may include a first edge EG11 surrounding at least a portion of the first light emitting portion EP1 and a second edge EG12 surrounding the first edge EG11. The second connection electrode CNE2a may include a first edge EG21 surrounding at least a portion of the second light emitting portion EP2 and a second edge EG22 surrounding the first edge EG21. The third connection electrode CNE3a may include a first edge EG31 surrounding at least a portion of the third light emitting portion EP3 and a second edge EG32 surrounding the first edge EG31.

[0325] In an embodiment of the present disclosure, the first connection electrode CNE1a may further include a first protrusion portion CPR1 protruding in a direction away from the first light emitting opening OP-PDL1. The second connection electrode CNE2a may further include a second protrusion portion CPR2 protruding in a direction away from the second light emitting opening OP-PDL2. The third connection electrode CNE3a may further include a third protrusion portion CPR3 protruding in a direction away from the third light emitting opening OP-PDL3.

[0326] According to an embodiment of the present disclosure, the first edge EG11 and the second edge EG12 of the first connection electrode CNE1a may protrude in a direction away from the first light-emitting opening OP-PDL1 to correspond to the shape of the first protrusion CPR1. The first edge EG21 and the second edge EG22 of the second connection electrode CNE2a may protrude in a direction away from the second light-emitting opening OP-PDL2 to correspond to the shape of the second protrusion CPR2. The first protrusion CPR1 may not overlap with the first light-emitting layer EML1a and may be spaced apart from the first light-emitting layer EML1a. The second protrusion CPR2 may not overlap with the second light-emitting layer EML2a and may be spaced apart from the second light-emitting layer EML2a. The third protrusion CPR3 may not overlap with the third light-emitting layer EML3a and may be spaced apart from the third light-emitting layer EML3a.

[0327] The first functional layer FNL1a may overlap the region between the first protrusion CPR1 and the first light-emitting layer EML1a. The second functional layer FNL2a may overlap the region between the second protrusion CPR2 and the second light-emitting layer EML2a. The third functional layer FNL3a may overlap the region between the third protrusion CPR3 and the third light-emitting layer EML3a. Furthermore, the first functional layer FNL1a may further overlap a portion of the first protrusion CPR1. The second functional layer FNL2a may further overlap a portion of the second protrusion CPR2. The third functional layer FNL3a may further overlap a portion of the third light-emitting layer EML3a.

[0328] In an embodiment of the present disclosure, the first light-emitting layer EML1a may overlap with the first light-emitting opening OP-PDL1 and the first through hole OP-P1, and the second light-emitting layer EML2a may overlap with the second light-emitting opening OP-PDL2 and the second through hole OP-P2. The third through hole OP-P3 may be provided between the third protrusion CPR3 and the third light-emitting portion EP3. Therefore, the third light-emitting layer EML3a may overlap with the third light-emitting opening OP-PDL3, but may not overlap with the third through hole OP-P3.

[0329] The first intermediate layer IML1a may include a first area AR11a and a second area AR12a adjacent to the first area AR11a. The second intermediate layer IML2a may include a first area AR21a and a second area AR22a adjacent to the first area AR21a. The third intermediate layer IML3a may include a first area AR31a and a second area AR32a adjacent to the first area AR31a. For example, the first areas AR11a, AR21a, and AR31a may be areas in which some of the multiple layers constituting the first intermediate layer IML1a, the second intermediate layer IML2a, and the third intermediate layer IML3a may be arranged, and the second areas AR12a, AR22a, and AR32a may be areas in which all of the layers constituting the first intermediate layer IML1a, the second intermediate layer IML2a, and the third intermediate layer IML3a may be arranged.

[0330] In an embodiment of the present disclosure, the first area AR11a of the first intermediate layer IML1a may not overlap with the first through-hole OP-P1, and the second area AR12a may overlap with the first through-hole OP-P1. The first area AR21a of the second intermediate layer IML2a may not overlap with the second through-hole OP-P2, and the second area AR22a may overlap with the second through-hole OP-P2. The first area AR31a of the third intermediate layer IML3a may overlap with the third through-hole OP-P3, and the second area AR32a may not overlap with the third through-hole OP-P3. For example, the first area AR11a of the first intermediate layer IML1a or the first area AR21a of the second intermediate layer IML2a may be adjacent to the first area AR31a of the third intermediate layer IML3a in the first direction DR1. Figure 11B It is shown that the first region AR11a of the first intermediate layer IML1a is adjacent to the first region AR31a of the third intermediate layer IML3a in the first direction DR1.

[0331] Figure 12 is a schematic cross-sectional view of a display panel DP-2 according to an embodiment of the present disclosure. Figure 12 is shown with Figure 11A Schematic cross-sectional view of the portion corresponding to line II-II'.

[0332] refer to Figure 12 , also refer to Figure 11A , a protruding region PRA may be further defined in the display panel DP-2. The protruding region PRA may be a region defined by a portion PR2 of the partition member SPRa, the portion PR2 surrounding Figure 11A The second light emitting part EP2 described in.

[0333] The connection electrode CNEb may include a protruding portion CRP to correspond to the protruding area PRA. A portion of the functional layer FNL may be provided in the protruding area PRA, and the light-emitting layer EML may not be provided in the protruding area PRA. The area of ​​the exposed area of ​​the connection electrode CNEb can be stably ensured. Therefore, the second electrode EL2 can be stably connected to the connection electrode CNEb, and therefore, the contact reliability can be improved. Therefore, the appearance defects caused by the contact defects, for example, the spot defects found when the light is turned on, can be reduced or eliminated. The display panel DP-2 and the display device DD including the display panel DP-2 (see Figure 1 ) image quality or manufacturing yield.

[0334] According to the above description, the light-emitting device and the pixel driving circuit can be stably in contact with each other, and thus the contact reliability can be improved. For example, the cathode of the light-emitting device and the connecting electrode electrically connected to the pixel driving circuit can be connected in a relatively wide area rather than at a specific point, and thus the contact reliability can be improved. In addition, at least a portion of the connecting electrode may not overlap with the light-emitting layer. Therefore, the area of ​​the exposed area of ​​the connecting electrode can be stably ensured. Therefore, the appearance defects caused by defective contact, such as spot defects found when the light is turned on, can be reduced or eliminated. Therefore, the image quality and manufacturing yield of the display panel can be improved.

[0335] Furthermore, the lower surface of the connecting electrode and the upper surface of the intermediate connecting electrode can contact each other, thereby improving contact reliability. Consequently, the size of the through hole connecting the connecting electrode and the intermediate connecting electrode can be reduced or minimized. Consequently, the area and resolution of the light-emitting portion of the display panel can be easily increased.

[0336] Although the above description has been made with reference to the embodiments of the present disclosure, it is understood that those skilled in the art or those with ordinary knowledge in the art may make various modifications and changes to the present disclosure without departing from the spirit and technical scope of the present disclosure described in the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of the specification, but should be defined by the appended claims.

Claims

1. A display panel, characterized in that: The display panel includes: a driver device layer, including a pixel driver; a light emitting device disposed on the driving device layer and comprising a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a pixel defining film, disposed on the driving device layer; and a connecting electrode disposed on the pixel defining film and electrically connected to the pixel driver and the second electrode, The intermediate layer includes a functional layer having a first area and a light-emitting layer having a second area smaller than the first area.

2. The display panel according to claim 1, wherein: The pixel defining film defines an opening, and at least a portion of the first electrode is exposed through the opening. The connecting electrode has a ring shape surrounding the opening, or a connection region where the second electrode and the connecting electrode are electrically connected surrounds at least a portion of the opening.

3. The display panel according to claim 1, wherein: A lower surface of the second electrode contacts an upper surface of the connection electrode.

4. The display panel according to claim 1, wherein: The functional layer includes: a first intermediate functional layer, disposed on the first electrode; and The second intermediate functional layer is provided on the light-emitting layer, wherein: The light emitting layer is disposed between the first intermediate functional layer and the second intermediate functional layer.

5. The display panel according to claim 1, wherein: The display panel further includes: a separator, disposed on the connecting electrode, The second electrode and the connecting electrode are electrically connected to each other in a region adjacent to the separator.

6. The display panel according to claim 5, wherein: The display panel further includes: a first dummy layer disposed on the separator, wherein the first dummy layer and the functional layer comprise the same material; and The second dummy layer is disposed on the first dummy layer, and the second dummy layer and the second electrode include the same material.

7. The display panel according to claim 5, wherein: The connecting electrode includes a first edge and a second edge surrounding the first edge, and The second edge overlaps the divider.

8. The display panel according to claim 5, wherein: The light emitting device is provided as a plurality of light emitting devices, the pixel driver is provided as a plurality of pixel drivers, and the connection electrode is provided as a plurality of connection electrodes, The plurality of connection electrodes electrically connect the plurality of light emitting devices and the plurality of pixel drivers, respectively, and A gap between adjacent connection electrodes among the plurality of connection electrodes overlaps with the separator.

9. The display panel according to claim 1, wherein: defining a through hole in the pixel defining film, and The connection electrode is electrically connected to the pixel driver through the through hole, The light-emitting layer does not overlap with the through hole and the functional layer overlaps with the through hole, or the light-emitting layer and the functional layer overlap with the through hole.

10. The display panel according to claim 1, wherein The pixel defining film defines an opening, and at least a portion of the first electrode is exposed through the opening. The connection electrode includes a protruding portion protruding in a direction away from the opening, The protruding portion does not overlap with the light emitting layer, The protruding portion of the connection electrode and the light emitting layer are spaced apart from each other, and The functional layer overlaps a region between the protruding portion and the light emitting layer.

11. A display panel, characterized in that: The display panel includes: a driver device layer, including a pixel driver; a light emitting device disposed on the driving device layer and comprising a first electrode, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer, wherein a light emitting portion is defined as corresponding to a portion of the first electrode; and a connecting electrode electrically connected to the pixel driver and the second electrode, wherein the connecting electrode comprises a first edge surrounding the light emitting portion, and A portion of the first edge does not overlap with the light emitting layer, and the portion of the first edge is spaced apart from an edge of the light emitting layer.

12. The display panel according to claim 11, wherein: The display panel further includes: A pixel defining film is provided on the driving device layer, wherein: An opening and a through hole spaced apart from the opening are defined in the pixel defining film, the opening defining the light emitting portion by exposing the portion of the first electrode, and The connection electrode is disposed on the pixel definition film, and the connection electrode is electrically connected to the pixel driver through the through hole.

13. The display panel according to claim 12, wherein: The connecting electrode further includes a second edge surrounding the first edge, Wherein, the display panel further includes: a spacer disposed on the pixel definition film and overlapping the second edge, The second electrode and the connecting electrode are electrically connected to each other in a region adjacent to the separator.

14. The display panel according to claim 12, wherein: The light emitting layer overlaps with the opening and does not overlap with the through hole, or the light emitting layer overlaps with the opening and the through hole.

15. The display panel according to claim 12, wherein: The portion of the first edge protrudes in a direction away from the opening.

16. The display panel according to claim 11, wherein: The light emitting device further comprises: a first intermediate functional layer, disposed between the first electrode and the light-emitting layer; and A second intermediate functional layer is provided between the light-emitting layer and the second electrode, The area of ​​each of the first intermediate functional layer and the second intermediate functional layer is larger than the area of ​​the light-emitting layer, or the first intermediate functional layer and the second intermediate functional layer overlap with the portion of the first edge.

17. A display panel, characterized in that: The display panel includes: a driver device layer, comprising a plurality of pixel drivers; a plurality of light emitting devices arranged on the driving device layer and electrically connected to the plurality of pixel drivers respectively; a plurality of connection electrodes electrically connected to the plurality of pixel drivers and the plurality of light emitting devices; and A plurality of partitions are provided between the plurality of light emitting devices, wherein: Each of the plurality of light emitting devices includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, and The intermediate layer includes a plurality of layers, some of the plurality of layers are arranged in a first region of the intermediate layer, and all of the plurality of layers are arranged in a second region of the intermediate layer adjacent to the first region.

18. The display panel according to claim 17, wherein: A gap between adjacent connection electrodes among the plurality of connection electrodes overlaps with a corresponding one of the plurality of separators. The display panel further includes: a pixel defining film disposed on the driving device layer, and defining an opening in the pixel defining film that exposes at least a portion of the first electrode of each of the plurality of light-emitting devices, wherein: A portion of each of the plurality of connection electrodes is disposed on the pixel definition film, and The plurality of spacers are disposed on the pixel defining film.

19. The display panel according to claim 18, wherein: The plurality of light emitting devices include a first light emitting device, a second light emitting device spaced apart from the first light emitting device in a first direction, and a third light emitting device spaced apart from the first and second light emitting devices in a second direction intersecting the first direction, A first opening exposing at least a portion of the first electrode of the first light emitting device, a second opening exposing at least a portion of the first electrode of the second light emitting device, and a third opening exposing at least a portion of the first electrode of the third light emitting device are defined in the pixel defining film, and The plurality of connection electrodes include a first connection electrode surrounding the first opening, a second connection electrode surrounding the second opening, and a third connection electrode surrounding the third opening.

20. The display panel according to claim 19, wherein The first region of the first light emitting device and the first region of the second light emitting device are arranged between the first opening and the second opening, and The first region of the first light emitting device and the first region of the second light emitting device are spaced apart from each other in the second direction.

21. The display panel according to claim 19, wherein The plurality of pixel drivers include a first pixel driver electrically connected to the first light emitting device, a second pixel driver electrically connected to the second light emitting device, and a third pixel driver electrically connected to the third light emitting device. A first through hole, a second through hole, and a third through hole are defined in the pixel defining film, and The first connection electrode is electrically connected to the first pixel driver through the first through-hole, the second connection electrode is electrically connected to the second pixel driver through the second through-hole, and the third connection electrode is electrically connected to the third pixel driver through the third through-hole.

22. The display panel according to claim 21, wherein: The first region of the first light emitting device overlaps with the first through hole, The first region of the second light emitting device overlaps with the second through hole, and The first region of the third light emitting device overlaps with the third through hole.

23. The display panel according to claim 21, wherein: The first region of the first light emitting device does not overlap with the first through hole, The first region of the second light emitting device does not overlap with the second through hole, and The first region of the third light emitting device overlaps with the third through hole, The first region of the first light-emitting device or the first region of the second light-emitting device is adjacent to the first region of the third light-emitting device in the second direction.

24. The display panel according to claim 17, wherein: A gap between adjacent connection electrodes among the plurality of connection electrodes overlaps with a corresponding one of the plurality of separators. The plurality of layers of the intermediate layer include: a first intermediate functional layer, disposed on the first electrode; a light-emitting layer, disposed on the first intermediate functional layer; and A second intermediate functional layer is provided on the light-emitting layer, and The first region of the intermediate layer includes the first intermediate functional layer and the second intermediate functional layer, and The second region of the intermediate layer includes the first intermediate functional layer, the light emitting layer, and the second intermediate functional layer.

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