Processor temperature adjusting device

Abstract

The utility model discloses a processor temperature adjusting device, which comprises a temperature acquisition chip, a CPLD (Complex Programmable Logic Device) chip, a BMC (Baseboard Management Controller) chip and a temperature sensor arranged in a processor, the temperature sensor, the temperature acquisition chip and the BMC chip are sequentially and electrically connected, the CPLD chip is respectively and electrically connected with the temperature acquisition chip and the BMC chip, and the BMC chip is electrically connected with the processor. According to the processor temperature adjusting device, the temperature of the processor is adjusted through the BMC chip, damage caused by too high temperature is prevented, meanwhile, when the BMC device is damaged, the CPLD chip directly powers off the processor, shutdown is achieved, and then the problems that in the prior art, BMC key hardware warning information is not processed in time, and the BMC device cannot be powered off in time are solved. In the scene, the situation that the maximum junction temperature of the processor is exceeded may occur, and physical damage is caused.

Description

TECHNICAL FIELD

[0001] The utility model belongs to computer technical field, and specifically relates to a processor temperature adjusting device. BACKGROUND

[0002] The CPU is mainly made of silicon material, and the melting point of silicon is 1402 DEG C. Although silicon can work at a higher temperature, in order to ensure the safety and stability of hardware, the temperature is usually limited at a lower level.

[0003] The CPU has a maximum junction temperature limit, and the chip may be physically damaged when running at a junction temperature exceeding the limit. In the design process of the whole machine product, the heat dissipation component is generally used to ensure that the whole machine does not appear over-temperature in the product application environment. If the heat dissipation component of the whole machine fails, such as fan failure, the BMC key hardware alarm information is not processed in time, and in this scene, the maximum junction temperature of the CPU may be exceeded, so the high-temperature fusing mechanism is proposed to protect the physical damage caused by over-temperature of the CPU. UTILITY MODEL CONTENTS

[0004] The utility model aims at solving the problems in the background art and proposes a processor temperature adjusting device.

[0005] To achieve the above-mentioned purpose, the technical scheme adopted by the utility model is:

[0006] The utility model proposes a processor temperature adjusting device, which comprises a temperature acquisition chip, a CPLD chip and a BMC chip, and a temperature sensor arranged in the processor.

[0007] The temperature sensor, the temperature acquisition chip and the BMC chip are electrically connected in sequence, the CPLD chip is electrically connected with the temperature acquisition chip and the BMC chip respectively, and the BMC chip is electrically connected with the processor.

[0008] Preferably, the temperature acquisition chip is provided with a first pin and a second pin, and the temperature acquisition chip is electrically connected with the temperature sensor in the processor through the first pin and is electrically connected with the CPLD chip through the second pin.

[0009] Preferably, the temperature acquisition chip and the BMC chip are connected through a first bus.

[0010] Preferably, the BMC chip and the processor are connected through a second bus.

[0011] Preferably, the first pin is a Temp_P / N pin.

[0012] Preferably, the second pin is an Alert pin.

[0013] Preferably, the first bus is an I2C bus.

[0014] Preferably, the second bus is an IPMB bus.

[0015] Compared with the prior art, the processor temperature regulating device has the following beneficial effects:

[0016] The processor temperature regulating device adjusts the temperature of the processor through the BMC chip to prevent damage caused by excessively high temperature, and when the BMC device is damaged, the CPLD chip directly powers off the processor to realize shutdown, thereby solving the problem that the BMC key hardware alarm information is not processed in time in the prior art, which may cause the maximum junction temperature of the processor to be exceeded and physical damage. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A module block diagram of the processor temperature regulating device. DETAILED DESCRIPTION

[0018] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and do not limit the present application.

[0019] In one embodiment, as shown in Figure 1 A processor temperature regulating device is provided, comprising a temperature acquisition chip, a CPLD chip and a BMC chip, and a temperature sensor placed in the processor, wherein:

[0020] The temperature sensor, the temperature acquisition chip and the BMC chip are electrically connected in sequence, the CPLD chip is electrically connected with the temperature acquisition chip and the BMC chip respectively, and the BMC chip is electrically connected with the processor.

[0021] It should be noted that the processor temperature adjustment device is placed within the computer chassis to regulate the temperature of the processor (i.e., CPU) to prevent damage caused by excessive temperatures. The model of each chip can be selected based on actual needs and is not limited. For example, in this embodiment, the model of the temperature acquisition chip is the domestic Shensi Ling CT7428, the model of the processor is the domestic Feiteng S5000C, the model of the CPLD chip is the domestic Unisplendour Tongchuang, and the model of the BMC chip is the domestic Loongson 2K0500. The temperature sensor is integrated within the processor and displays the temperature of the processor. The temperature acquisition chip acquires the temperature of the temperature sensor (i.e., the temperature of the processor). The BMC chip obtains the temperature acquired by the temperature acquisition chip and, in turn, acquires the temperature of the processor. The BMC chip regulates the temperature of the processor to prevent damage caused by excessive temperatures. The CPLD chip is also electrically connected to the processor to power on or off the processor, thereby turning the processor on or off.

[0022] In one embodiment, the temperature acquisition chip is provided with a first pin and a second pin, and the temperature acquisition chip is electrically connected to the temperature sensor in the processor through the first pin, and the temperature acquisition chip is electrically connected to the CPLD chip through the second pin;

[0023] Among them, the first pin is the Temp_P / N pin, and the second pin is the Alert pin (specifically the Alert[0:1] pin).

[0024] In one embodiment, the temperature acquisition chip and the BMC chip are connected via a first bus; wherein the first bus is an I2C bus.

[0025] In one embodiment, the BMC chip and the processor are connected via a second bus, wherein the second bus is an IPMB bus.

[0026] It should be noted that the number of temperature acquisition chips and temperature sensors corresponds to the number of processors. In this embodiment, the number of processors is two as an example. Figure 1 In the example, CPU1 and CPU2 are used to represent them respectively. Then the number of temperature sensors is also two, which are built into the two processors respectively. The number of temperature acquisition chips is also two. Figure 1The temperature sensors are respectively represented by Temp sensor1 and Temp sensor2, and the first pin is connected to the temperature sensor in the two processors one by one, and is also connected to the CPLD chip through the second pin. The temperature sensor displays the temperature of the processor. The temperature acquisition chip collects the temperature of the temperature sensor in the processor. The BMC chip obtains the temperature collected by the temperature acquisition chip through the I2C bus, and then obtains the temperature of the processor. When the temperature of the processor is greater than the first threshold value (which is the maximum junction temperature of the processor), the BMC chip adjusts the rotating speed of the fan in the case to cool the processor or reduces the performance of the processor (the BMC first adjusts the rotating speed of the fan. When the rotating speed of the fan is adjusted to the maximum, it is detected that the temperature of the processor does not decrease, and then the BMC reduces the performance of the processor through the second bus (IPMB bus)), thereby reducing the power consumption of the processor. The operation can be performed in a polling manner until the junction temperature of the processor is lower than the first threshold value. When the temperature of the processor is greater than the second threshold value (which is greater than the first threshold value and is the maximum temperature that the processor can withstand without causing physical damage), the processor may not work normally and be in a hanging state. The BMC chip sends a shutdown command to the CPLD chip, and the CPLD chip performs a power-down operation to realize the shutdown of the processor. The fan is built-in in the case and is electrically connected with the BMC chip, and is used for cooling. Figure 1 The second bus between the BMC chip and the two processors is respectively represented by CPU1_IPMB and CPU2_IPMB.

[0027] Meanwhile, the temperature acquisition chip configures the level state of the second pin Alert[0:1] according to the collected temperature of the processor and outputs it to the CPLD chip. The CPLD chip detects the level change of the second pin in real time. For example, a high level indicates that the temperature of the processor is greater than the second threshold value, and a low level indicates that the temperature of the processor is less than the second threshold value. When the CPLD chip detects that the level of one of the second pins becomes high, it sends an alarm information to the BMC chip (which is represented by Temp_Over signal). Figure 1 When the BMC chip receives the Temp_Over signal, it sends a shutdown command to the CPLD chip, and the CPLD chip performs a power-down operation to realize the shutdown of the processor. When the BMC chip fails to process the alarm information, the CPLD chip can also directly perform a power-down operation to realize the shutdown of the processor.

[0028] The processor temperature adjusting device adjusts the temperature of the processor through the BMC chip to prevent damage caused by high temperature. When the BMC device is damaged, the CPLD chip directly powers down the processor to realize shutdown, thereby solving the problem that the alarm information of the BMC key hardware in the prior art is not processed in time, which may cause the maximum junction temperature of the processor to be exceeded and cause physical damage.

[0029] The above embodiments only express several implementation manners of the application, and the description is more specific and detailed, but it cannot be understood as the limitation of the scope of the utility model patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the application, several modifications and improvements can be made, which belong to the protection scope of the application. Therefore, the protection scope of the patent of the application should be subject to the appended claims.

Claims

1. A processor temperature regulating device, characterized in that: The processor temperature adjustment device includes a temperature acquisition chip, a CPLD chip, a BMC chip, and a temperature sensor placed in the processor, wherein: The temperature sensor, the temperature acquisition chip and the BMC chip are electrically connected in sequence, the CPLD chip is electrically connected to the temperature acquisition chip and the BMC chip respectively, and the BMC chip is electrically connected to the processor.

2. The processor temperature regulating device according to claim 1, wherein: The temperature acquisition chip is provided with a first pin and a second pin, and the temperature acquisition chip is electrically connected to the temperature sensor in the processor through the first pin, and the temperature acquisition chip is electrically connected to the CPLD chip through the second pin.

3. The processor temperature regulating device according to claim 1, wherein: The temperature acquisition chip and the BMC chip are connected via a first bus.

4. The processor temperature regulating device according to claim 1, wherein: The BMC chip and the processor are connected via a second bus.

5. The processor temperature regulating device according to claim 2, wherein: The first pin is a Temp_P / N pin.

6. The processor temperature regulating device according to claim 2, wherein: The second pin is an Alert pin.

7. The processor temperature regulating device according to claim 3, wherein: The first bus is an I2C bus.

8. The processor temperature regulating device according to claim 4, wherein: The second bus is an IPMB bus.

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