Integrated circuit package

Abstract

Various embodiments of the utility model relate to an integrated circuit package. The integrated circuit package comprises a first integrated circuit device. The interconnect structure is disposed over the first integrated circuit device in a cross-sectional side view. The interconnect structure includes a plurality of interconnect components. The holes are disposed in the interconnect structure in a cross-sectional side view. The second integrated circuit device is at least partially disposed within the cavity in a cross-sectional side view. The second integrated circuit device is electrically coupled to the first integrated circuit device at least through a subset of the interconnect components of the interconnect structure. The non-metallic material partially fills the hole. In a cross-sectional side view and in a top view, the second integrated circuit device is at least partially surrounded by a non-metallic material.

Description

TECHNICAL FIELD

[0001] An integrated circuit package is provided. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. IC design and material technology has progressed to the point where ICs can now be created with feature sizes below 100 nanometers. Designing and manufacturing ICs with such small features is an extremely challenging task. In designing ICs that can include ever increasing numbers of devices and components, there comes a point where refinement of IC design is no longer possible. To achieve this, a new design is needed that allows for ICs to be created with significantly more features.

[0003] As semiconductor devices continue to shrink in size, challenges in manufacturing can arise. For example, a redistribution layer (RDL) structure can be formed as part of an IC package for routing electrical signals. An IC device can be formed on top of the RDL structure, with the IC device electrically coupled to the IC package. An underfill material is typically formed around the IC device. However, as semiconductor devices continue to shrink in size, the distance between the underfill material and other nearby components on the IC package (e.g., under bump metallization (UBM) components) can also become smaller. This can cause the underfill material to spread onto these nearby components, which can adversely affect the performance or intended operation of the IC package.

[0004] Therefore, while existing semiconductor manufacturing methods are generally adequate for their intended purposes, these methods have not been entirely satisfactory in every respect. SUMMARY

[0005] An integrated circuit package is provided. The integrated circuit package includes a first integrated circuit device. The integrated circuit package also includes an interconnect structure disposed on the first integrated circuit device in a cross-sectional side view, wherein the interconnect structure includes a plurality of interconnect components. The integrated circuit package also includes a cavity disposed in the interconnect structure in the cross-sectional side view. The integrated circuit package also includes a second integrated circuit device at least partially disposed within the cavity in the cross-sectional side view, wherein the second integrated circuit device is electrically coupled to the first integrated circuit device at least through a subset of the interconnect components of the interconnect structure. The integrated circuit package also includes a non-metallic material that partially fills the cavity, wherein the second integrated circuit device is at least partially surrounded by the non-metallic material in the cross-sectional side view and in a top view.

[0006] Another aspect of the present application provides an integrated circuit package. The integrated circuit package includes a system-on-a-chip device. The integrated circuit package also includes a redistribution layer structure disposed over the system-on-a-chip device, wherein the redistribution layer structure includes an isolation material and a plurality of conductive components embedded in the isolation material. The integrated circuit package also includes an integrated circuit device at least partially embedded in the redistribution layer structure, wherein the integrated circuit device is electrically coupled to a first one of the conductive components of the redistribution layer structure. The integrated circuit package also includes an under bump metallization structure disposed over the redistribution layer structure, wherein the under bump metallization structure is electrically coupled to a second one of the conductive components of the redistribution layer structure.

[0007] Another aspect of the present application provides a method of manufacturing an integrated circuit package. The method includes forming a redistribution layer structure over a first integrated circuit device, wherein the redistribution layer structure includes a plurality of conductive components. The method also includes forming a cavity in the redistribution layer structure, wherein the cavity exposes at least a first one of the plurality of conductive components. The method also includes placing a second integrated circuit device at least partially in the cavity such that the second integrated circuit device is electrically coupled to the first conductive component. The method also includes at least partially filling the cavity with a material layer, wherein the material layer surrounds a portion of the second integrated circuit device.

[0008] So that the foregoing features and advantages of the present application can be understood in more detail, a more particular description will be rendered by reference to specific embodiments thereof, which are illustrated in the appended drawings and will be described herein below. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figures 1-25 are cross-sectional side views of an integrated circuit (IC) package constructed in accordance with various aspects of the present disclosure at various stages of manufacture.

[0010] Figures 26A-26B , Figures 27A-27B and Figures 28A-28B are top views of an integrated circuit (IC) package constructed in accordance with various aspects of the present disclosure.

[0011] Figure 29 is a block diagram of a semiconductor manufacturing system.

[0012] Figure 30 is a flow diagram of a method of manufacturing an IC package in accordance with various aspects of the present disclosure. DETAILED DESCRIPTION

[0013] It is to be understood that the present technology provides many different embodiments or examples, and that the embodiments can be implemented in various combinations and / or sub-combinations. It is further noted that, depending on the express ablities of the processor being employed, the exemplary methods can be implemented in "real-time" or in "non-real-time". Embodiments of the present technology will be described herein with reference to the accompanying drawings, in which:

[0014] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. For example, when a device is inverted, as illustrated in the figures, a component described as "below" or "beneath" another component or "lower" than another component can be oriented "above" the other component or "upper" than the other component. Accordingly, the exemplary spatially relative descriptors used herein interpreted

[0015] Furthermore, "about", "approximately", and the like, when used with a numerical value or range of values, are intended to encompass values that are within a reasonable range of the recited value or values, such as within ±10% of the recited value or other values as would be understood by those skilled in the art. For example, the language "about 5 nm" encompasses a range of sizes from 4.5 nm to 5.5 nm.

[0016] Integrated circuit (IC) chips include a plurality of different types of microelectronic components, such as transistors, resistors, inductors, capacitors, etc. In some cases, an IC package can include a system on IC (or SoIC) device that includes a plurality of such microelectronic components. The IC package can also include a redistribution layer (RDL) structure formed over the IC device. The RDL structure can include a plurality of metallization layers (e.g., copper-based metallization layers) that can be used to facilitate electrical routing (and / or heat dissipation) of the IC package. For example, another type of IC device can be formed over the RDL structure. In some embodiments, the IC device formed over the RDL structure can be an integrated passive device (IPD), which is an IC that includes passive components such as capacitors, inductors, or resistors. The IPD can or can not include active devices such as transistors. In other embodiments, the IC device formed over the RDL structure can include an IC that includes active devices (e.g., with transistors). Regardless of the type of IC device formed over the RDL structure, the RDL structure can provide electrical connections between the SoIC device (disposed below the RDL structure) and the IC device formed over the RDL structure. Solder bumps can also be formed over the RDL structure to provide electrical connections to the SoIC device through the RDL structure.

[0017] An underfill material can be applied around the IC device formed over the RDL structure. The underfill material can include an adhesive material to enhance attachment between the IC device and the RDL structure. The underfill material also helps to protect the IC device from contamination sources and / or moisture. However, as IC device sizes continue to shrink, the distance between the IC device and other nearby components (e.g., solder bumps) formed over the RDL structure can also shrink. As a result, the underfill material intended to surround the IC device (but not the nearby components, such as solder bumps) can inadvertently spread to the nearby components. Capillary effects can exacerbate the spread of the underfill material to the nearby components, such as solder bumps. Inadvertent over-spread of the underfill material can adversely affect the overall functionality of the IC package, and thus is undesirable.

[0018] To address the problem of over-diffusion of underfill, the present disclosure utilizes a novel manufacturing process flow to create a cavity in an RDL structure formed over a SoIC as part of an IC package. An IC device is then formed at least partially in the cavity in the RDL structure, and then an underfill material is applied around the IC device in the cavity. The cavity acts as a reservoir to contain the underfill material therein, such that the underfill material does not leak out of the cavity. Thus, according to the present disclosure, the underfill material does not inadvertently diffuse to nearby components. As a result, the overall performance of the IC package of the present disclosure is improved.

[0019] Reference will now be made to the drawings Figures 1-25 to discuss a process flow for implementing various aspects of the present disclosure, Figures 1-25 is a schematic partial cross-sectional side view of an IC package 100 constructed in accordance with various aspects of the present disclosure in one embodiment.

[0020] Reference will now be made to the drawings Figure 1 The IC package 100 includes an IC device 110. In some embodiments, the IC device 110 includes a System on Integrated Circuit (SoIC) chip. In some embodiments, the SoIC chip can include different IC dies. For example, the SoIC chip can include an electronic memory (e.g., Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM)) die, and a logic device die electrically and / or physically coupled to the electronic memory die. The logic device die can include logic circuitry configured to operate and / or control circuit operations of the electronic memory die.

[0021] As Figure 1As shown, the IC device 110 includes an IC base 120. In some embodiments, the IC base 120 includes a semiconductor base, such as a silicon base. Other types of bases can also be employed in other embodiments. The IC base 120 can include various IC component devices, such as field effect transistors (FETs), memory cells, image sensors, passive devices, other devices, or combinations thereof. For example, the IC base 120 can include a planar active region having various IC devices such as planar field effect transistors (FETs). In some other embodiments, the IC base 120 can include a fin (e.g., vertically protruding) active region having various IC devices formed thereon. It should be appreciated that, in some embodiments, the fin active region can also be used to form gate-all-around (GAA) devices. Regardless of the type of transistors employed, it should be appreciated that these transistors can form building blocks of the circuitry of the electronic memory die and / or logic device die of the SoIC chip. For simplicity, the details of the transistor layout / arrangement are not specifically illustrated or described herein.

[0022] The IC device 110 can also include a plurality of metal layers 140 formed on the side 160 of the IC device 110. In this regard, for ease of reference, the IC device 110 (or the IC package 100 itself) can have a side 160 and a side 161 opposite the side 160. The side 160 can also be referred to as a top side, and the side 161 can also be referred to as a bottom side. In some embodiments, the transistors (e.g., planar transistors, FinFETs, or GAA devices) of the IC device 110 can be formed at or near the side 160 of the IC base 120. The metal layers 140 can include metal lines and vias or contacts to provide electrical routing for the circuitry of the IC device 110. The metal lines are distributed in multiple levels of metal layers, such as a first metal layer (e.g., Ml layer), a second metal layer (e.g., M2 layer), and so on. For simplicity, the details of the metal layers 140 are not described herein.

[0023] Still referring to Figure 1 The IC package 100 also includes an interconnect structure 150 (separate from the metal layers 140) formed on the metal layers 140. In some embodiments, the interconnect structure 150 can include a redistribution layer (RDL) structure configured to route and / or, in some cases, dissipate electrical signals generated by the IC device 110. For example, as will be discussed in greater detail below, the interconnect structure 150 can include a plurality of interconnect layers that include electrically and / or thermally conductive components that can be used to route and / or dissipate electrical signals. In some embodiments, the conductive components of the interconnect structure 150 are copper-based conductive components. Thus, the RDL structure of the interconnect structure 150 can be referred to as a copper RDL structure. In other embodiments, the conductive components of the interconnect structure 150 can be nickel-based or some other type of metal material.

[0024] The interconnect structure 150 can include a plurality of RDL layers. In Figure 1 At a manufacturing stage, an RDL0 layer and an RDL1 layer are formed as initial portions of the interconnect structure 150. The RDL0 layer is the bottommost layer of the interconnect structure 150, and the RDL1 layer is the layer immediately above the RDL0 layer. Each RDL layer can include a conductive material, as discussed above, which in various embodiments can be copper, nickel, or other types of metallic materials. The conductive material is surrounded by an isolation material 170, which helps to electrically isolate the conductive material of the RDL layers from other conductive components (e.g., nearby RDL components) that are not intended to be in electrical contact with the RDL layers. In other words, the isolation material 170 helps to prevent unintended and undesirable electrical shorts.

[0025] The isolation material 170 is a non-metallic material that is capable of providing electrical isolation for various conductive components (e.g., RDL layers) of the interconnect structure 150. In some embodiments, the isolation material 170 includes a polymeric material. In other embodiments, the isolation material 170 includes a dielectric material, such as silicon oxide. In any case, it should be understood that, in accordance with various embodiments of the present disclosure, a via can be formed in the interconnect structure 150 in a manner that exposes any one of the RDL layers. In embodiments related to Figures 1-13 In some other embodiments, the via can expose the RDL0, or even in yet other embodiments, the via can expose an RDL2 layer (formed later).

[0026] Still referring to Figure 1 The IC package 100 also includes a mold encapsulation material 180 that surrounds at least a portion of the IC device 110 and the interconnect structure 150. In Figure 1 In a cross-sectional side view, the mold encapsulation material 180 is shown as being on opposite side surfaces of the IC substrate 120, the metal layer 140, and the isolation material 170 of the interconnect structure 150. The mold encapsulation material 180 can provide protection for the portions of the IC package 100 that are surrounded by the mold encapsulation material 180.

[0027] Reference is now made to Figure 2A coating and patterning process 190 is performed on the IC package 100. As a first step of the coating and patterning process 190, a coating process is performed to coat additional portions of the isolation material 170 over and around the RDL1 layers of the interconnect structure 150. In some embodiments, the coating process can include one or more deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. In some embodiments, the deposited isolation material 170 includes a polymer or silicon oxide. As a second step of the coating and patterning process 190, a photolithographic patterning process is performed on the deposited isolation material 170. For example, the photolithographic patterning process can include one or more photoresist spin coating, pre-exposure baking, exposure, post-exposure baking, and / or developing processes. The photolithographic patterning process forms a plurality of holes in the interconnect structure 150. For example, a hole 200 is formed to expose at least a portion of the first RDL1 layer (e.g., the one on the right), and a hole 201 is formed to expose at least a portion of the second RDL1 layer (e.g., the one on the left). Figure 2 The one on the right). Figure 2 The one on the left).

[0028] Referring now to Figure 3 A photoresist coating process 210 is performed on the IC package 100 to form a patterned photoresist layer 220. In some embodiments, the photoresist coating process 210 includes a photoresist spin coating process. One or more photoresist exposure, baking, and developing processes can also be performed to define the patterned photoresist layer 220. The patterned photoresist layer 220 fills the hole 200, but still exposes the hole 201. At this stage of fabrication, the hole 201 not only includes the portion of the hole that extends vertically through the isolation material 170, but the hole 201 can also include the portion of the hole that extends vertically through a portion of the photoresist layer 220 to expose a portion of the isolation material 170.

[0029] Referring now to Figure 4 A deposition process 230 is performed on the IC package 100 to form an RDL2 layer of the interconnect structure 150. In some embodiments, the deposition process 230 can include one or more CVD, PVD, or ALD processes. The deposition process 230 deposits a conductive material, such as copper or nickel, in the hole 201 to form the RDL2 layer in the hole 201. The RDL2 layer is electrically connected to the underlying RDL1 layer. Since the hole 200 is covered by the photoresist layer 220, no RDL2 layer is formed in the hole 200. It should be appreciated that in some embodiments, a planarization process, such as a chemical mechanical polishing (CMP) process, can be performed after the deposition of the conductive material to remove excess portions of the conductive material outside the hole 201.

[0030] Referring now to Figure 5A photoresist removal process 240 is performed on the IC package 100 to remove the photoresist layer 220. In some embodiments, the photoresist removal process 240 can include a photoresist stripping process or a photoresist ashing process. As a result of performing the photoresist removal process 240, the RDL2 layer is exposed, and portions of the RDL1 layer that were located under the via 200 are also exposed.

[0031] Referring now to Figure 6 A coating and patterning process 250 is performed on the IC package 100. As a first step of the coating and patterning process 250, a coating process is performed to form additional portions of the isolation material 170 over and around the RDL2 layer of the interconnect structure 150. Portions of the isolation material 170 can also be coated over the RDL1 layer under the via 200. In some embodiments, the coating process can include one or more deposition processes, such as CVD, PVD, ALD, or a combination thereof. In some embodiments, the deposited isolation material 170 includes a polymer or silicon oxide. As a second step of the coating and patterning process 250, a lithographic patterning process is performed on the deposited isolation material 170. For example, the lithographic patterning process can include one or more photoresist spin coating, pre-exposure baking, exposure, post-exposure baking, and / or developing processes. The lithographic patterning process forms a via 260 in the isolation material 170, where the via 260 at least partially exposes the RDL2 layer. As a result of the lithographic patterning process, the via 200 (exposing the RDL1 layer) is also substantially maintained, although its depth is increased by the deposition of the additional isolation material 170.

[0032] Referring now to Figure 7 A photoresist coating process 280 is performed on the IC package 100 to form a patterned photoresist layer 290. In some embodiments, the photoresist coating process 280 includes a photoresist spin coating process. One or more photoresist exposure, baking, and developing processes can also be performed to define the patterned photoresist layer 290. The patterned photoresist layer 220 fills the via 200 but exposes the via 260. At this stage of fabrication, the via 260 not only includes a portion of the via that extends vertically through the isolation material 170, but the via 260 can also include a portion of the via that extends vertically through a portion of the photoresist layer 290 to expose a portion of the isolation material 170.

[0033] Referring now to Figure 8A deposition process 300 is performed on the IC package 100 to form an RDL3 layer of the interconnect structure 150. In some embodiments, the deposition process 300 can include one or more CVD, PVD, or ALD processes. The deposition process 300 deposits a conductive material, such as copper or nickel, in the cavities 260 to form the RDL3 layer in the cavities 260. The RDL3 layer is electrically connected to the underlying RDL2 layer. Since the cavities 200 are covered by the photoresist layer 290, no RDL3 layer is formed in the cavities 200. It should be appreciated that in some embodiments, a planarization process, such as a CMP process, can be performed after the deposition of the conductive material to remove excess portions of the conductive material outside the cavities 260.

[0034] Referring now to Figure 9 A photoresist removal process 310 is performed on the IC package 100 to remove the photoresist layer 290. In some embodiments, the photoresist removal process 310 can include a photoresist stripping process or a photoresist ashing process. As a result of performing the photoresist removal process 310, the RDL3 layer is exposed, and portions of the RDL1 layer located under the cavities 200 are also exposed.

[0035] The above manufacturing processes can be repeated for multiple cycles to complete the formation of the interconnect structure 150. For example, each cycle can include the formation and patterning of the isolation material, the application of a patterned photoresist layer to cover the cavities 200, the formation of an RDL layer, and the subsequent removal of the patterned photoresist layer. For simplicity, the present disclosure illustrates the formation of three RDL layers: RDL1, RDL2, and RDL3, where RDL1 is the intended landing layer for the IC devices (e.g., IPDs) that have not yet been formed over the side surface 160 and in the cavities 200. However, it should be appreciated that the interconnect structure 150 can include any number of RDL layers (e.g., four, five, six, or more), and any of the RDL layers can be used as the bonding layer for the IC devices to be formed over the side surface 160.

[0036] Referring now to Figure 10, a UBM formation process 320 is performed on the IC package 100 to form a UBM structure. In this regard, the UBM formation process 320 may include one or more of the manufacturing processes for forming the RDL layer. For example, the UBM formation process 320 may include a coating process for coating an additional portion of the isolation material 170 around the RDL 3, a coating process for a patterned photoresist layer covering the cavity 200, the formation of the UBM structure (e.g., by defining the UBM structure using a patterned photoresist layer), and subsequent removal of the patterned photoresist layer. In this way, the UBM structure can be considered as another RDL layer of the interconnect structure. However, in some embodiments, the UBM structure can be configured to have a different material composition and / or a different thickness than the remaining RDL layers of the interconnect structure 150 because the purpose of the UBM structure is to serve as a landing pad for the solder bump.

[0037] Now refer to Figure 11 , a solder bump and IC device forming process 340 is performed on the IC package 100 to form solder bumps 350 and IC devices 360. Figure 11 As shown, solder bumps 350 are formed on the UBM. In some embodiments, solder bumps 350 include a metal alloy material that is meltable at high temperatures. For example, the metal alloy material can be made of tin and / or lead, and the metal alloy material can be melted by a hot iron when the hot iron reaches a temperature of approximately 600 degrees Fahrenheit or higher. Due to its melting properties, solder bumps 350 can serve as electrical conduits between IC device 110 and other external devices. For example, the external device can be configured to be in direct physical contact with solder bumps 350 and heat can be applied to melt solder bumps 350. This allows the external device to establish a good electrical connection with the UBM, thereby allowing the external device to electrically communicate with the circuitry of IC device 110 at least partially through the RDL layer of interconnect structure 150.

[0038] According to various aspects of the present disclosure, IC device 360 ​​is at least partially disposed within cavity 200. For example, the bottom surface of IC device 360 ​​is vertically lower than the top surface of the uppermost isolation material 170, even though the top surface of IC device 360 ​​is vertically higher than the top surface of the uppermost isolation material 170. In other words, the bottom surface of IC device 360 ​​is located closer to IC device 110 than the top surface of the uppermost isolation material 170, but the top surface of IC device 360 ​​is located farther from IC device 110 than the top surface of the uppermost isolation material 170. Stated another way, the top surface of the uppermost isolation material 170 has a vertical height between the vertical height of the bottom surface of IC device 360 ​​and the vertical height of the top surface of IC device 360.

[0039] In some embodiments, the IC device 360 ​​includes an integrated passive device (IPD), which is an IC that includes passive components such as capacitors, inductors, or resistors. For example, the IPD may include a three-dimensional capacitor structure, such as a deep trench capacitor. In some embodiments, the IPD may or may not include active devices, such as transistors. It should be understood that the IC device 360 ​​is not limited to an IPD. In some embodiments, the IC device 360 ​​may include an IC that includes active devices such as transistors. Regardless of the type of device as which the IC device 360 ​​is implemented, the IC device 360 ​​is electrically coupled to the RDL1 layer through a plurality of interconnect components 370, which may be in the form of bonding pads or solder bumps. In this way, the IC device 360 ​​is at least partially electrically coupled to the circuit of the IC device 110 through the RDL1 layer and the RDL0 layer.

[0040] The implementation of the IC device 360 ​​at least partially within the cavity 200 is one of the unique physical characteristics of the IC package 100 of the present disclosure. Conventional IC packages lack such a cavity 200, so any IC device implemented on top of the RDL structure must be implemented on the topmost RDL layer. As discussed above, this may result in the underfill material (described below with reference to Figure 13 The formation of the RDL structure (formed in the steps discussed above) can lead to excessive diffusion, which is undesirable. Furthermore, conventional implementations of IC device 360 ​​(e.g., not within a cavity) may require a relatively long distance between the IC device bonded to the RDL structure and the SoIC beneath it. Such a long distance may increase parasitic effects, such as parasitic inductance and / or parasitic resistance.

[0041] Conversely, the fact that IC device 360 ​​is at least partially located within cavity 200 effectively reduces the distance between IC device 360 ​​and IC device 110 (e.g., a SoIC device) (e.g., by more than 20 microns in some embodiments) because electrical signals transmitted between IC device 360 ​​and IC device 110 can bypass the RDL layer above RDL layer RDL1. In other words, electrical signals propagate through RDL layers RDL1 and RDL0, but not through RDL layers RDL2 and RDL3. Consequently, parasitic effects can be reduced. For example, the shorter distance can result in a reduction in equivalent series inductance (ESL) or equivalent series resistance (ESR). Consequently, the overall device performance of IC package 100 can be improved.

[0042] Now refer to Figure 12, performing an underfill material dispensing process 380 to partially fill the cavity 200 with an underfill material 400. In some embodiments, the underfill material 400 is dispensed via a nozzle 410. In some embodiments, the nozzle 410 can dispense the underfill material 400 using a jet dispensing process. In some embodiments, the underfill material 400 can include a non-metallic colloidal material that can provide electrical insulation and physical protection. For example, the underfill material 400 can have a relatively low viscosity, a relatively high glass transition temperature, a relatively low coefficient of thermal expansion, and relatively good adhesion. The underfill material 400 can also include inorganic particles that can be relatively easily dispersed in the space filled by the underfill material 400, in this case, the space is the lower portion of the cavity 200. In some embodiments, the underfill material 400 includes an epoxy resin.

[0043] like Figure 12 As shown, underfill material 400 fills the space between IC device 360 ​​and RDL1 layer, including the space around interconnect component 370. Due to the above-described properties of underfill material 400, underfill material 400 can adequately maintain the bond between IC device 360 ​​and RDL1 layer, and shield the portion of IC device 360 ​​encapsulated therein from other sources of contamination (e.g., dust or moisture) and from mechanical forces that may damage IC device 360.

[0044] Now refer to Figure 13The underfill material dispensing process 380 can continue such that more of the cavities 200 are filled with the underfill material 400. How much of the cavity 200 is to be filled with the underfill material 400 can be precisely configured. For example, the distance 430 between the uppermost surface of the interconnect structure 150 (e.g., the exposed upper surface of the isolation material 170) and the upper surface of the RDL1 layer can be known by design. The size (e.g., volume) of the cavity 200 can also be configured by the fabrication processes discussed above. The rate at which the nozzle 410 dispenses the underfill material 400 is also known, and can be configured. From the above factors, the length of the dispensing time can be calculated to control the amount of underfill material 400 that fills the cavity 200 such that the underfill material 400 does not overfill the cavity 200. In other words, the underfill material dispensing process 380 is configured to ensure that the depth 440 of the underfill material 400 (e.g., corresponding to the distance between the upper surface of the underfill material 400 in the cavity 200 and the upper surface of the RDL1 layer) is less than the distance 430. In other words, the upper surface of the underfill material 400 is lower in the vertical direction than the uppermost surface of the interconnect structure 150. Such a configuration reduces the likelihood that the underfill material 400 will overflow the cavity 200 and spread to nearby components, such as the solder bump 350.

[0045] As discussed above, the formation of the cavity 200 and the implementation of the IC device 360 in the cavity 200 provides various benefits. One benefit is that the closer distance between the IC device 360 and the IC device 110 translates to reduced parasitic inductance and / or reduced parasitic resistance. Another benefit is that the underfill material 400 can be retained within the cavity 200, thereby reducing the likelihood that the underfill material will over-spread to nearby components, such as the solder bump 350. The reduced likelihood of over-spread of the underfill material 400 means that the distance 450 between the IC device 360 and the solder bump 350 (in some embodiments between about 10 microns and about 100 microns) can also be reduced.

[0046] In more detail, conventional IC packages can have to designate a "keep-out zone" around an IC device like IC device 360. Components around such an IC device should stay away from the keep-out zone in order to minimize the risk of underfill material spreading to nearby components. However, such a keep-out zone places an undue burden on IC design and fabrication, especially since IC device space is very valuable, and the keep-out zone can translate into wasted space. In contrast, IC device 360 can not need a keep-out zone around it at all since underfill material 400 is retained within cavities 200. Even if a keep-out zone is designated around IC device 360 as a precaution, the size of the keep-out zone can be significantly reduced compared to conventional IC packages. In other words, solder bumps 350 and IC device 360 can now be implemented closer to each other without increasing the risk of underfill material 400 spreading onto solder bumps 350.

[0047] Note that, Figure 13 Embodiments of the present disclosure also do not require a dam structure to prevent potential over-spreading of underfill material 400. However, a dam structure (e.g., a columnar structure that protrudes vertically upward) can still be implemented between solder bumps 350 and IC device 360 to block any underfill material 400 that spills outside of cavities 200. Since any inadvertently spilled underfill material 400 has to climb over such a dam structure before reaching solder bumps 350, the presence of the dam structure can further prevent solder bumps 350 (or other nearby components of IC device 360) from coming into contact with underfill material 400.

[0048] Figures 1-13 Corresponding to a first embodiment of the present disclosure, cavities 200 in interconnect structure 150 are filled with underfill material 400 that has a different material composition than isolation material 170. Figures 14-17 Corresponding to a second embodiment of the present disclosure (to be discussed below), cavities 200 in interconnect structure 150 are filled with isolation material 170. For consistency and clarity, similar components appearing in the first and second embodiments will be labeled the same.

[0049] Referring now to Figure 14 , IC package 100 has gone through the fabrication process discussed above with reference to Figures 1-9 That is, RDL1, RDL2, and RDL3 layers of interconnect structure 150 have been formed on side 160 of IC package 100. Cavities 200 have also been formed in interconnect structure 150, with cavities 200 exposing one of the RDL1 layers. Patterned photoresist layer 290 (see Figure 8) have also been removed by the photoresist removal process 310. Thus, the RDL3 layer and the RDL1 layer are both exposed at this fabrication stage.

[0050] Referring now to Figure 15 , an IC device coupling process 500 is performed to couple the IC device 360 to the IC package 100. The IC device 360 is electrically coupled to the RDL1 layer by a plurality of interconnect components 370. Again, the IC device 360 is implemented at least partially within the aperture 200 such that a bottom surface of the IC device 360 is lower in a vertical direction than an upper surface of the uppermost isolation material 170. However, an upper surface of the IC device 360 is still higher in the vertical direction than the upper surface of the uppermost isolation material 170. As discussed above, the IC device 360 can include an IPD in some embodiments, or the IC device 360 can include an active device such as a transistor in other embodiments.

[0051] Referring now to Figure 16 , an isolation material and UBM formation process 520 is performed to fill the aperture 200 with an isolation material 170 and to form a UBM structure over the RDL3 layer. In more detail, one or more deposition processes such as a CVD process, a PVD process, or an ALD process can be performed to deposit the isolation material 170 in the aperture 200. The isolation material 170 can completely fill the aperture and enclose portions of the IC device 360 including the interconnect components 370. In other words, portions of the IC device 360 are embedded within the isolation material 170. In some embodiments, the isolation material 170 includes a polymer material. In other embodiments, the isolation material 170 includes a silicon oxide material. The isolation material 170 can also embed the RDL3 layer therein. The UBM structure is also formed over the isolation material 170. The UBM structure is electrically coupled to the RDL3 layer of the interconnect structure 150.

[0052] Referring now to Figure 17 , a solder bump formation process 540 is performed to form a solder bump 350 over the UBM structure. As discussed above with reference to the first embodiment, the solder bump 350 can include a metal alloy material such as a tin-based and / or lead-based metal alloy. The solder bump 350 serves as an electrical access point for circuitry within the IC device 110.

[0053] Although the cavity 200 is filled by the isolation material 170 in the second embodiment, rather than being filled by the underfill material 400 in the first embodiment, the second embodiment can still substantially achieve the same benefits discussed above with reference to the first embodiment. For example, since the IC device 360 is at least partially located within the cavity 200, the IC device 360 is closer to the IC device 110. Such a reduction in distance can effectively reduce parasitic effects, such as parasitic inductance and / or parasitic resistance, thereby improving device performance. Additionally, since the underfill material 400 is not used in the second embodiment, there is no risk of the underfill material 400 overflowing and spreading to nearby components, such as the solder bumps 350. Eliminating the underfill material 400 does not interfere with or otherwise alter the normal operation of the IC package 100, since the isolation material 170 can still effectively maintain the attachment of the IC device 360 to the RDL1 layer, and protect the components and / or interconnects 370 of the IC device 360 from contamination particles or mechanical forces.

[0054] Figures 18-22 A third embodiment corresponding to the present disclosure will be discussed below, in which the cavity 200 in the interconnect structure 150 is filled by a combination of the underfill material 400 and the isolation material 170. For consistency and clarity, similar components appearing in the first embodiment, the second embodiment, and the third embodiment will be labeled the same.

[0055] Referring now to Figure 18 , the IC package 100 has undergone a manufacturing process discussed above with reference to Figures 1-9 . That is, the RDL1 layer, the RDL2 layer, and the RDL3 layer of the interconnect structure 150 have been formed over the side surface 160 of the IC package 100. The cavity 200 has also been formed in the interconnect structure 150, in which the cavity 200 exposes one of the RDL1 layers. The patterned photoresist layer 290 (see Figure 8 ) has also been removed by the photoresist removal process 310. Thus, the RDL3 layer and the RDL1 layer are both exposed at this manufacturing stage.

[0056] Referring now to Figure 19 , the IC device coupling process 500 (see Figure 15) to couple IC device 360 ​​to IC package 100. For example, IC device 360 ​​can be bonded to RDL1 layer via a plurality of interconnect components 370. Again, IC device 360 ​​is implemented at least partially within cavity 200 such that the bottom surface of IC device 360 ​​is vertically lower than the upper surface of the uppermost isolation material 170. However, the upper surface of IC device 360 ​​is still vertically higher than the upper surface of the uppermost isolation material 170. As discussed above, IC device 360 ​​may comprise an IPD in some embodiments, or may comprise an active device, such as a transistor, in other embodiments.

[0057] Now refer to Figure 20 , performing an underfill forming process 600 to partially fill the cavity 200 with the underfill material 400. In some embodiments, the underfill material 400 may be dispensed through a nozzle 410 (see Figure 12 ) is dispensed, for example, by a jet dispensing process. As discussed above, the colloidal nature of underfill material 400 facilitates attachment of IC device 360 ​​(specifically, interconnect assembly 370) to the underlying RDL1 layer. Underfill material 400 also protects portions of IC device 360 ​​and interconnect assembly 370 from sources of contamination (e.g., dust or moisture) and from mechanical forces that could damage IC device 360.

[0058] Now refer to Figure 21 , an isolation material and UBM formation process 620 is performed to fill the cavity 200 with the isolation material 170 and form a UBM structure above the RDL3 layer. In more detail, one or more deposition processes, such as a CVD process, a PVD process, or an ALD process, may be performed to deposit the isolation material 170 on the bottom filler material 400 in the cavity 200. As discussed above, in various embodiments, the isolation material 170 may include a polymer material or a silicon oxide material. The isolation material 170 and the bottom filler material 400 may together fill the cavity 200 and embed a portion of the IC device 360 ​​therein. The isolation material 170 may also embed the RDL3 layer therein. The UBM structure is also formed above the isolation material 170. The UBM structure is electrically coupled to the RDL3 layer of the interconnect structure 150.

[0059] Now refer to Figure 22 , a solder bump formation process 640 is performed to form solder bumps 350 on the UBM structure. As discussed above with reference to the first embodiment or the second embodiment, solder bumps 350 may include a metal alloy material, such as a tin-based and / or lead-based metal alloy. Solder bumps 350 serve as electrical access points for circuits within IC device 110.

[0060] Based on the above discussion, it can be seen that in the third embodiment, the cavity 200 is filled with a combination of underfill material 400 and isolation material 170, rather than being filled with underfill material 400 alone (e.g., as in the first embodiment) or isolation material 170 alone (e.g., as in the second embodiment). However, the third embodiment still achieves substantially the same benefits discussed above with reference to the first or second embodiments. For example, because IC device 360 ​​is at least partially located within cavity 200, IC device 360 ​​can still be positioned closer to IC device 110. This reduced distance can effectively reduce parasitic effects, such as parasitic inductance and / or parasitic resistance, thereby improving device performance. Furthermore, because underfill material 400 is covered by isolation material 170, it is less likely to overflow from cavity 200 and infringe upon adjacent IC components, such as solder bumps 350. The colloid-like properties of underfill material 400 allow it to maintain the adhesion of IC device 360 ​​to the RDL1 layer. The combination of underfill material 400 and isolation material 170 can also effectively protect components of IC device 360 ​​and / or interconnect components 370 from contaminating particles or mechanical forces that may damage IC device 360 ​​.

[0061] Based on the above discussion, it can be seen that each of the first embodiment, the second embodiment, or the third embodiment of the present disclosure can form an IC package 100 that at least partially embeds the IC device 360 ​​in a cavity 200 formed on the side 160 of the interconnect structure 150. This embodiment allows the bottom filler material 400 to be retained in the cavity 200, or even eliminated entirely. In this way, the likelihood of the bottom filler material 400 overflowing the cavity and diffusing to nearby components (e.g., solder bumps 350) is greatly reduced. However, the embodiments discussed above can be modified to include a dam structure to further reduce the likelihood of excessive diffusion of the bottom filler material 400. These modifications to the above first embodiment, second embodiment, and third embodiment are respectively illustrated in FIG. Figures 23-25 .

[0062] For example, the IC packages 100 manufactured according to the first embodiment, the second embodiment, and the third embodiment of the present disclosure are respectively Figure 23 、 Figure 24 and Figure 25 Specifically, the dam structure 700 is implemented on the side 160 of the interconnect structure 150, for example, on the upper surface of the uppermost isolation material 170. In the top view, the dam structure 700 can surround the IC device 360 ​​360 degrees. However, in Figures 23-25In cross-sectional side views, dam structures 700 can appear as two vertical protruding pillars located on opposite sides of IC device 360. The material composition of dam structures 700 can be configured elastically. In Figures 23-25 In embodiments, dam structures 700 have the same material composition as UBM structures. For example, dam structures 700 can be formed together with UBM structures through the same manufacturing process used to form UBM structures. The presence of dam structures 700 can further prevent potential over- spreading of underfill material 400 (or over-spreading of isolation material 170, if any, were to occur). As such, components near IC device 360 are less likely to come into contact with underfill material 400. Thus, the implementation of dam structures 700 can further reduce potential defects and further improve device performance.

[0063] To further illustrate various aspects of the disclosure, top views of embodiments of the disclosure are illustrated in Figures 26A-26B , Figures 27A-27B and Figures 28A-28B . Specifically, Figure 26A a top view of IC package 100 manufactured according to a first embodiment of the disclosure is illustrated, in which dam structures 700 are not implemented, while Figure 26B a top view of IC package 100 manufactured according to a variation of the first embodiment of the disclosure is illustrated, in which dam structures 700 are implemented. Figure 27A a top view of IC package 100 manufactured according to a second embodiment of the disclosure is illustrated, in which dam structures 700 are not implemented, while Figure 27B a top view of IC package 100 manufactured according to a variation of the second embodiment of the disclosure is illustrated, in which dam structures 700 are implemented. Figure 28A a top view of IC package 100 manufactured according to a third embodiment of the disclosure is illustrated, in which dam structures 700 are not implemented, while Figure 28B a top view of IC package 100 manufactured according to a variation of the third embodiment of the disclosure is illustrated, in which dam structures 700 are implemented.

[0064] Referring now to Figure 26A and Figure 26B , underfill material 400 circumferentially surrounds IC device 360 by 360 degrees. In Figures 26A-26B embodiments, the profile of underfill material 400 can be configured as a rectangle, but can be configured as other geometric shapes in different embodiments. A plurality of solder bumps 350 are implemented near IC device 360, for example, in respective rows on each side of IC device 360. In Figure 26B a variation of the first embodiment shown, dam structures 700 circumferentially surround IC device 360 and underfill material 400 by 360 degrees. In Figure 26BIn the embodiment of FIG. 7, the dam structure 700 can also be configured to be rectangular in profile, but can be configured to other geometric shapes in different embodiments.

[0065] Referring now to FIG. 8, a cross-sectional side view of the IC package 100 of FIG. 1 is shown. Figure 27A and Figure 27B The underfill material 400 is not implemented, but the portion of the isolation material 170 that fills the void 200 is circumferentially around the IC device 360 at 360 degrees. In the embodiment of FIG. 8, the dam structure 700 is implemented around the IC device 360 and the isolation material 170 at 360 degrees. Figures 27A-27B In the embodiment of FIG. 8, the dam structure 700 can also be configured to be rectangular in profile, but can be configured to other geometric shapes in different embodiments. A plurality of solder bumps 350 are implemented around the IC device 360, for example, in respective rows on each side of the IC device 360. Figure 27B In the variant of the second embodiment shown in FIG. 9, the dam structure 700 is implemented around the IC device 360 and the isolation material 170 at 360 degrees. Figure 27B In the embodiment of FIG. 9, the dam structure 700 can also be configured to be rectangular in profile, but can be configured to other geometric shapes in different embodiments.

[0066] Referring now to FIG. 10, a cross-sectional side view of the IC package 100 of FIG. 1 is shown. Figure 28A and 28B The top-down view of the third embodiment (and variants thereof) looks substantially the same as the top-down view of the second embodiment (and variants thereof) shown in FIGS. 5 and 6, respectively. This is because, although the third embodiment does implement the underfill material 400, in cross-sectional side view, the underfill material 400 is implemented below the isolation material 170 (see FIG. 10). Thus, the isolation material 170 can be seen in the top-down view, but the underfill material 400 cannot be seen. Figure 27A and Figure 27B The top-down view of the third embodiment (and variants thereof) looks substantially the same as the top-down view of the second embodiment (and variants thereof) shown in FIGS. 5 and 6, respectively. This is because, although the third embodiment does implement the underfill material 400, in cross-sectional side view, the underfill material 400 is implemented below the isolation material 170 (see FIG. 10). Thus, the isolation material 170 can be seen in the top-down view, but the underfill material 400 cannot be seen. Figure 25

[0067] Figure 29 An integrated circuit manufacturing system 900 that can be used to manufacture the IC package 100 (or components thereof, such as the IC device 110 or the IC device 360) according to embodiments of the present disclosure is shown. The manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916,..., N connected by a communications network 918. The network 918 can be a single network or can be various different networks, such as an intranet and the Internet, and can include wired and wireless communication channels.

[0068] ​In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring a product of interest; entity 906 represents an engineer, such as a process engineer controlling processes and associated recipes, or an equipment engineer monitoring or adjusting conditions and settings of a process tool; entity 908 represents a metrology tool used for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool for performing a photolithography process to define gate spacers for SRAM devices; entity 912 represents a virtual metrology module associated with process tool 910; entity 914 represents an advanced process control module associated with process tool 910 and another process tool; and entity 916 represents a sampling module associated with process tool 910.

[0069] Each entity can interact with the other entities and can provide integrated circuit manufacturing capabilities, process control capabilities, and / or computing capabilities to the other entities and / or receive integrated circuit manufacturing capabilities, process control capabilities, and / or computing capabilities from the other entities. Each entity can also include one or more computer systems for performing calculations and performing automation. For example, the advanced process control module of entity 914 can include a plurality of computer hardware having software instructions encoded therein. The computer hardware can include a hard drive, a flash drive, a compact disc read-only memory (CD-ROM), a random access memory (RAM), a display device (e.g., a monitor), and input / output devices (e.g., a mouse and keyboard). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0070] The integrated circuit manufacturing system 900 enables interaction between entities to achieve integrated circuit (IC) manufacturing and advanced process control for IC manufacturing. In one embodiment, advanced process control includes adjusting process conditions, settings, and / or recipes of a processing tool applied to associated wafers based on metrology results.

[0071] In another embodiment, metrology results are measured from a subset of processed wafers based on an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and selected points of a subset of processed wafers based on an optimal sampling field / optimal sampling point determined based on various characteristics of process quality and / or product quality.

[0072] One of the capabilities provided by the IC manufacturing system 900 can be to enable collaboration and information access in areas such as design, engineering and processing, metrology, and advanced process control. Another capability provided by the IC manufacturing system 900 can be to integrate systems between facilities, such as between metrology tools and processing tools. Such integration enables facilities to coordinate their activities. For example, integrating metrology tools and processing tools can enable manufacturing information to be more effectively incorporated into manufacturing processes or APC modules, and can enable wafer data measured from online or in-line metrology tools to be integrated in related processing tools.

[0073] Figure 30 is a flowchart illustrating a method 1000 according to an embodiment of the disclosure. The method 1000 includes a step 1010 to form a redistribution layer (RDL) structure over a first integrated circuit (IC) device. The RDL structure includes a plurality of conductive components.

[0074] The method 1000 includes a step 1020 to form a hole in the RDL structure. The hole exposes at least a first conductive component of the plurality of conductive components.

[0075] The method 1000 includes a step 1030 to place a second IC device at least partially in the hole such that the second IC device is electrically coupled to the first conductive component.

[0076] The method 1000 includes a step 1040 to at least partially fill the hole with a material layer, where the material layer surrounds a portion of the second IC device.

[0077] In some embodiments, the step 1020 of forming the hole includes forming the hole in a first layer of the RDL structure, forming a patterned photoresist layer over the RDL structure, where the patterned photoresist layer fills the hole but exposes a second conductive component of the plurality of conductive components, forming an additional layer of the RDL structure over the second conductive component, and removing the patterned photoresist layer, thereby exposing the first conductive component in the hole.

[0078] In some embodiments, the first IC device and the second IC device are different types of IC devices.

[0079] In some embodiments, the RDL structure is formed to include an isolation material that separates the plurality of conductive components from one another. In some embodiments, at least partially filling the hole includes dispensing an underfill material into the hole through a nozzle, where the underfill material has a different material composition than the isolation material.

[0080] In some embodiments, the RDL structure is formed to include an isolation material separating the plurality of conductive components from one another. In some embodiments, at least partially filling the cavity includes depositing an additional portion of the isolation material into the cavity such that the cavity is completely filled with the isolation material.

[0081] In some embodiments, the RDL structure is formed to include an isolation material separating the plurality of conductive components from one another. In some embodiments, at least partially filling the cavity includes dispensing a bottom-filler material into the cavity through a nozzle. A material composition of the bottom-filler material is different from the isolation material. At least partially filling the cavity further includes applying an additional portion of the isolation material over the bottom-filler material. The additional portion of the isolation material completely fills the cavity.

[0082] It should be appreciated that additional processes can be performed before, during, or after steps 1010-1040 of method 1000. For example, method 1000 can include a step of forming an under bump metallization (UBM) structure over the RDL structure, where the UBM structure is electrically coupled to the second conductive component of the plurality of conductive components. A solder bump is formed over the UBM structure. As another example, method 1000 can include a step of forming a dam structure over the RDL structure, where, in a top view, the dam structure circumferentially surrounds the second IC device. For the sake of simplicity, other additional steps are not discussed in detail herein.

[0083] In summary, the present disclosure relates to forming a cavity in an interconnect structure (e.g., a RDL structure) of an IC package, and implementing an IC device at least partially inside the cavity. The cavity is then filled with an underfill material or an isolation material or a combination of both. By doing so, the present disclosure provides advantages over conventional IC packages. However, it should be understood that other embodiments can provide additional advantages, and not all advantages necessarily need to be recited in the present disclosure, and not all embodiments need to provide a particular advantage. One of the advantages is to reduce over- spreading of the underfill material. In this regard, conventional IC packages can result in the underfill material being formed on the upper surface of the RDL structure, and the underfill material can over-spread to other nearby components, such as solder bumps. Capillary effect can exacerbate the problem of over-spreading. If the underfill material is in direct contact with the nearby components, it can adversely interfere with the intended operation of the IC package. Another advantage is to reduce parasitic effects. As discussed above, since the IC device is implemented at least partially inside the cavity, this translates to a closer distance between the IC device and the SoIC device of the IC package. If the cavity is not implemented, the IC device has to be located on the upper surface of the RDL structure, which is further away from the SoIC device. The reduced distance between the IC device and the SoIC device can result in lower parasitic inductance and / or lower parasitic resistance, which will improve the overall performance of the IC package. Other advantages include compatibility with existing manufacturing and / or packaging processes, so the present disclosure does not require additional processing, and thus is easy and inexpensive to implement.

[0084] One aspect of the present disclosure provides an IC package. The IC package includes a first integrated circuit (IC) device. An interconnect structure is disposed over the first IC device in a cross-sectional side view. The interconnect structure includes a plurality of interconnect components. A cavity is disposed in the interconnect structure in the cross-sectional side view. A second IC device is disposed at least partially within the cavity in the cross-sectional side view. The second IC device is electrically coupled to the first IC device at least through a subset of the interconnect components of the interconnect structure. A non-metallic material partially fills the cavity. The second IC device is at least partially surrounded by the non-metallic material in the cross-sectional side view and in a top view.

[0085] In some embodiments, the interconnect structure includes a plurality of redistribution layers overlying one another in the cross-sectional side view; the plurality of redistribution layers each include a different subset of the interconnect components; and the via extends through a plurality of the redistribution layers in the cross-sectional side view. In some embodiments, the first integrated circuit device includes a system-on-a-chip (SoIC) device; and the second integrated circuit device includes a chip that includes a plurality of passive components but does not include a transistor. In some embodiments, the first integrated circuit device includes a system-on-a-chip (SoIC) device; and the second integrated circuit device includes a chip that includes a transistor. In some embodiments, in the cross-sectional side view, an uppermost surface of the interconnect structure is higher than an uppermost surface of the non-metallic material in the vertical direction. In some embodiments, the integrated circuit package further includes: an under bump metallization structure disposed over the interconnect structure in the cross-sectional side view, wherein no dam structure is disposed between the under bump metallization structure and the second integrated circuit device in the top-down view; and a solder bump disposed over the under bump metallization structure in the cross-sectional side view. In some embodiments, the interconnect structure includes an isolation material in which the interconnect components are embedded; and the non-metallic material that partially fills the via includes an underfill material that has a different material composition than the isolation material. In some embodiments, the interconnect structure includes an isolation material in which the interconnect components are embedded; and the non-metallic material that partially fills the via has the same material composition as the isolation material. In some embodiments, the interconnect structure includes an isolation material in which the interconnect components are embedded; and the non-metallic material that partially fills the via includes the isolation material and an underfill material that has a different material composition than the isolation material.

[0086] Another aspect of the present disclosure provides an IC package. The IC package includes a system-on-a-chip (SoIC) device. A redistribution layer (RDL) structure is disposed over the SoIC device. The RDL structure includes an isolation material and a plurality of conductive components embedded in the isolation material. An integrated circuit (IC) device is at least partially embedded within the RDL structure. The IC device is electrically coupled to a first one of the conductive components of the RDL structure. An under bump metallization (UBM) structure is disposed over the RDL structure. The UBM structure is electrically coupled to a second one of the conductive components of the RDL structure.

[0087] In some embodiments, the redistribution layer structure includes an isolation material and an underfill material that has a different material composition than the isolation material; and the integrated circuit device is at least partially embedded in the underfill material. In some embodiments, the integrated circuit device includes a passive device.

[0088] Yet another aspect of the present disclosure provides a method. A redistribution layer (RDL) structure is formed over a first integrated circuit (IC) device. The RDL structure includes a plurality of conductive components. An aperture is formed in the RDL structure. The aperture exposes at least a first conductive component of the plurality of conductive components. A second IC device is placed at least partially in the aperture such that the second IC device is electrically coupled to the first conductive component. The aperture is at least partially filled with a material layer. The material layer surrounds a portion of the second IC device.

[0089] In some embodiments, the method further includes forming an under bump metallization structure over the redistribution layer structure, wherein the under bump metallization structure is electrically coupled to a second conductive component of the plurality of conductive components; and forming a solder bump over the under bump metallization structure. In some embodiments, the method further includes forming a dam structure over the redistribution layer structure, wherein, in a top view, the dam structure circumferentially surrounds the second integrated circuit device. In some embodiments, forming the aperture includes forming the aperture in a first layer of the redistribution layer structure; forming a patterned photoresist layer over the redistribution layer structure, wherein the patterned photoresist layer fills the aperture but exposes the second conductive component of the plurality of conductive components; forming an additional layer of the redistribution layer structure over the second conductive component; and removing the patterned photoresist layer, thereby exposing the first conductive component in the aperture. In some embodiments, the first integrated circuit device and the second integrated circuit device are different types of integrated circuit devices. In some embodiments, the redistribution layer structure is formed to include an isolation material that separates the plurality of conductive components from one another; and at least partially filling the aperture includes dispensing a underfill material into the aperture through a nozzle, wherein the underfill material has a different material composition than the isolation material. In some embodiments, the redistribution layer structure is formed to include an isolation material that separates the plurality of conductive components from one another; and at least partially filling the aperture includes depositing an additional portion of the isolation material into the aperture such that the aperture is completely filled with the isolation material. In some embodiments, the redistribution layer structure is formed to include an isolation material that separates the plurality of conductive components from one another; and at least partially filling the aperture includes dispensing a underfill material into the aperture through a nozzle, wherein the underfill material has a different material composition than the isolation material; and subsequently applying an additional portion of the isolation material over the underfill material, wherein the additional portion of the isolation material completely fills the aperture.

[0090] Finally, it should be noted that: the above embodiments are used to illustrate the technical solutions of the present application, but not limited to them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An integrated circuit package, characterized in that: include: a first integrated circuit device; an interconnect structure disposed over the first integrated circuit device in a cross-sectional side view, wherein the interconnect structure includes a plurality of interconnect components; a cavity disposed in the interconnect structure in the cross-sectional side view; a second integrated circuit device disposed at least partially within the cavity in the cross-sectional side view, wherein the second integrated circuit device is electrically coupled to the first integrated circuit device via at least a subset of the interconnect components of the interconnect structure; as well as A non-metallic material partially fills the cavity, wherein the second integrated circuit device is at least partially surrounded by the non-metallic material in the cross-sectional side view and in the top view.

2. The integrated circuit package according to claim 1, wherein: The interconnect structure includes a plurality of redistribution layers stacked one upon another in the cross-sectional side view; each of the plurality of redistribution layers comprises a different subset of the interconnect components; and The hole extends through a plurality of the plurality of redistribution layers in the cross-sectional side view.

3. The integrated circuit package according to claim 1, wherein: In the cross-sectional side view, an uppermost surface of the interconnect structure is higher in a vertical direction than an uppermost surface of the non-metallic material.

4. The integrated circuit package according to claim 1, wherein: Also includes: an underbump metallization structure disposed above the interconnect structure in the cross-sectional side view, wherein no dam structure is disposed between the underbump metallization structure and the second integrated circuit device in the top view; as well as A solder bump is disposed over the underbump metallization in the cross-sectional side view.

5. The integrated circuit package according to claim 1, wherein: The interconnect structure includes an isolation material, the interconnect component being embedded in the isolation material; and The non-metallic material partially filling the cavity includes an underfill material having a material composition different from that of the isolation material.

6. The integrated circuit package according to claim 1, wherein: The interconnect structure includes an isolation material, the interconnect component being embedded in the isolation material; and The non-metallic material partially filling the pores has the same material composition as the isolation material.

7. The integrated circuit package according to claim 1, wherein: The first integrated circuit device comprises an integrated system-on-chip device; and The second integrated circuit device includes a chip including transistors.

8. An integrated circuit package, characterized in that: include: integrating system-on-chip devices; a redistribution layer structure disposed on the integrated system-on-chip device, wherein the redistribution layer structure comprises an isolation material and a plurality of conductive components embedded in the isolation material; a cavity disposed in the redistribution layer structure in a cross-sectional side view; an integrated circuit device at least partially disposed within the cavity in the cross-sectional side view, wherein the integrated circuit device is electrically coupled to a first of the conductive elements of the redistribution layer structure; as well as An under bump metallization (UBM) structure is disposed above the RDL structure, wherein the UBM structure is electrically coupled to a second one of the conductive components of the RDL structure.

9. The integrated circuit package according to claim 8, wherein: The redistribution layer structure further includes an underfill material, the underfill material partially filling the hole, the material composition of the underfill material being different from that of the isolation material; and The integrated circuit device is at least partially embedded in the underfill material.

10. The integrated circuit package according to claim 8, wherein: The integrated circuit device includes integrated passive devices.

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