ESD circuit and chip
By introducing a bias signal providing unit and a secondary discharge module into the ESD circuit, the problem of insufficient transistor conduction uniformity in traditional ESD protection circuits is solved, achieving more effective electrostatic energy discharge and chip protection.
Patent Information
- Application Number
- CN202422908867.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-11-27
AI Technical Summary
In traditional ESD protection circuits, transistor conduction uniformity is insufficient, affecting circuit performance.
An ESD circuit design including a primary discharge module and a secondary discharge module is adopted. A preset bias signal is provided to the discharge MOS tube through a bias signal providing unit to make it turn on evenly. The Wilson current mirror and the nanoampere current branch are used to mirror the current. Combined with the pinch-off characteristics of the JFET tube, the electrostatic energy is further discharged.
The discharge capacity of the discharge MOS tube is improved, ensuring uniform opening, and enhancing the protection capability of chip-related structures, especially providing additional protection in the case of ESD current overload.
Smart Images
Figure CN223451823U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of circuit, in particular to an ESD circuit and a chip. BACKGROUND
[0002] ESD (electrostatic discharge) protection is widely used in various fields requiring stable operation of electronic devices, especially in the electronic and electrical, IT and communication, and automotive industries. In the electronic industry, static electricity is one of the main causes of damage to electronic devices, so static protection measures are particularly important. ESD protection devices are widely used in various types of circuits, systems and devices, especially in high-integration electronic devices. For example, in automotive electronic systems, due to the increase in chip integration and the decrease in size, the sensitivity to ESD increases, so special attention needs to be paid to ESD protection. However, under many processes, the traditional ESD protection circuit has the problem of insufficient uniformity of at least part of the transistor conduction, thereby affecting the performance of the circuit. CONTENT OF THE INVENTION
[0003] In view of this, the present application provides an ESD circuit and a chip to solve the problem of insufficient uniformity of at least part of the transistor conduction in the traditional ESD protection circuit.
[0004] The ESD circuit provided by the present application comprises a first discharge module and a second discharge module; the first discharge module comprises a discharge MOS tube, a bias signal providing unit and a first resistor corresponding to each discharge MOS tube;
[0005] The drain of the discharge MOS tube is linked to a chip pin, the gate is grounded through the corresponding first resistor, the source is grounded, and the substrate is connected to the signal providing end of the bias signal providing unit; the first end of the second discharge module is connected to the chip pin, and the second end is connected to the internal circuit of the chip;
[0006] The first discharge module is used to discharge the static energy at the chip pin by turning on the discharge MOS tube;
[0007] The second discharge module is used to further discharge the static energy at the chip pin and clamp the voltage at the second end to below a preset voltage;
[0008] The bias signal providing unit is used to provide a preset bias signal for the discharge MOS tube, so that the discharge MOS tube is in a weak conduction state when the static energy passes through the discharge MOS tube.
[0009] Optionally, the bias signal providing unit comprises a Wilson current mirror and a nano-ampere current branch; the nano-ampere current branch is configured to provide a nano-ampere current; an input end of the Wilson current mirror is connected to an output end of the nano-ampere current branch, and an output end thereof is connected to a substrate level of the discharge MOS tube as a signal providing end of the bias signal providing unit, and is configured to mirror process the nano-ampere current and provide the mirror-processed current to the substrate level of the discharge MOS tube as the preset bias signal.
[0010] Optionally, the Wilson current mirror comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube; a source of the first MOS tube is connected to the chip pin, a drain thereof is connected to an output end of the Wilson current mirror, and a gate thereof is connected to a gate of the second MOS tube, a gate of the third MOS tube, a drain of the fourth MOS tube and a drain of the third MOS tube respectively; a source of the second MOS tube and a source of the third MOS tube are connected to the chip pin respectively; a source of the fourth MOS tube is grounded, and a gate thereof is connected to a gate of the fifth MOS tube, a drain of the fifth MOS tube and the drain of the third MOS tube respectively; and a source of the fifth MOS tube is connected to an output end of the nano-ampere current branch.
[0011] Optionally, the first MOS tube, the second MOS tube and the third MOS tube are PMOS tubes; and the fourth MOS tube and the fifth MOS tube are NMOS tubes.
[0012] Optionally, the nano-ampere current branch comprises a second resistor; a first end of the second resistor is connected to an output end of the nano-ampere current branch, and a second end thereof is grounded.
[0013] Optionally, the second resistor has a resistance of 100MΩ.
[0014] Optionally, the second discharge module comprises a third resistor and a jfet tube; a first end of the third resistor is connected to the chip pin, and a second end thereof is connected to a source of the jfet tube; a gate of the jfet tube is connected to a drain of the jfet tube and an internal circuit of the chip respectively.
[0015] Optionally, the third resistor has a resistance in a range of 1kΩ-10kΩ.
[0016] The application further provides a chip comprising any one of the ESD circuits.
[0017] In the above ESD circuit and chip, the bias signal providing unit can provide preset bias signals for the discharge MOS tubes, so that each discharge MOS tube is in a weak conduction state when the static electricity energy is discharged through each discharge MOS tube. In this way, when the ESD current passes through the discharge MOS tube, the discharge MOS tube can be evenly opened to improve the discharge capacity of each discharge MOS tube. In addition, the secondary discharge module can further discharge the static electricity energy at the chip pin when the energy discharge of the primary discharge module is not complete, so as to protect the chip related structure again and improve the protection capacity of the chip related structure. The above ESD circuit can improve the static electricity discharge capacity from multiple aspects, thereby improving the protection capacity of the chip related structure. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0019] Figure 1 is an ESD circuit structure schematic diagram of an embodiment of the present application;
[0020] Figure 2 is a discharge MOS tube schematic diagram of an embodiment of the present application;
[0021] Figure 3 is an ESD circuit structure schematic diagram of another embodiment of the present application;
[0022] Figure 4 is an ESD circuit structure schematic diagram of another embodiment of the present application. DETAILED DESCRIPTION
[0023] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application. In the case of no conflict, each of the following embodiments and technical features can be combined with each other.
[0024] The first aspect of the present application provides an ESD circuit, which is arranged in a chip that needs to be protected from static electricity discharge. Referring to Figure 1As shown, the ESD circuit includes a first discharge module 100 and a second discharge module 200; the first discharge module 100 includes at least one discharge MOS tube N1, a bias signal providing unit 111, and a first resistor R1 corresponding to each discharge MOS tube N1.
[0025] The drain of each discharge MOS tube N1 is linked to a chip pin PAD, the gate is grounded through the corresponding first resistor R1, the source is grounded, and the substrate is connected to the signal providing end of the bias signal providing unit 111. The first end of the second discharge module 200 is connected to the chip pin PAD, and the second end is connected to the internal circuit of the chip.
[0026] Optionally, the discharge MOS tube N1 can be a P-substrate NMOS tube, and the transistor structure thereof can refer to Figure 2 As shown, the discharge MOS tube N1 can include one discharge MOS tube or multiple discharge MOS tubes, and the connection characteristics of each discharge MOS tube are consistent; for example, referring to Figure 3 As shown, the discharge MOS tube N1 includes one discharge MOS tube ESD1, the drain of the discharge MOS tube ESD1 is linked to the chip pin PAD, the gate is grounded through the first resistor R1, the source is grounded, and the substrate is connected to the signal providing end of the bias signal providing unit 111; for another example, referring to Figure 4 As shown, the discharge MOS tube N1 includes n discharge MOS tubes, namely ESD1 to ESDn, the drain of each discharge MOS tube ESD1 is linked to the chip pin PAD, the gate is grounded through the corresponding first resistor R1, the source is grounded, and the substrate is connected to the signal providing end of the bias signal providing unit 111.
[0027] The first discharge module 100 is used to discharge the static energy at the chip pin PAD by turning on each discharge MOS tube N1.
[0028] The second discharge module 200 is used to further discharge the static energy at the chip pin PAD, so as to protect the chip-related structure again in the case that the energy discharge of the first discharge module 100 is not complete, and to enhance the protection capability of the chip-related structure. Optionally, the second discharge module 200 can also clamp the voltage at the second end to below a preset voltage, that is, clamp the voltage input to the internal circuit of the chip to below a preset voltage, so as to enhance the protection function of the internal circuit of the chip. Optionally, the preset voltage can be set to 5V or the like.
[0029] The bias signal providing unit 110 is configured to provide a preset bias signal for each discharge MOS tube N1, so that each discharge MOS tube N1 is in a weak conduction state when the electrostatic energy passes through each discharge MOS tube N1. In this way, when the ESD current passes through the discharge MOS tube N1, the discharge MOS tube N1 can be uniformly turned on, thereby improving the discharge capability of each discharge MOS tube N1.
[0030] Optionally, the preset bias signal includes a bias voltage. The bias signal providing unit 110 can provide a small bias voltage, and the value of the bias voltage is in the range of 0.6V-1V, for example, the preset bias signal can be 0.6V, 0.7V or 1V, etc. A preset bias signal is provided to the substrate of each discharge MOS tube N1, that is, a preset bias signal is provided to the parasitic diode of each discharge MOS tube N1, so that each discharge MOS tube N1 is in a weak conduction state, and thus when the ESD current passes through each discharge MOS tube N1, each discharge MOS tube N1 can be uniformly turned on, and the electrostatic energy discharge capability is improved.
[0031] The above ESD circuit, the bias signal providing unit 110 is configured to provide a preset bias signal for each discharge MOS tube N1, so that each discharge MOS tube N1 is in a weak conduction state when the electrostatic energy passes through each discharge MOS tube N1. In this way, when the ESD current passes through the discharge MOS tube N1, the discharge MOS tube N1 can be uniformly turned on, thereby improving the discharge capability of each discharge MOS tube N1; in addition, the secondary discharge module 200 can further discharge the electrostatic energy at the chip pin when the energy discharge of the primary discharge module 100 is not complete, thereby protecting the chip-related structure again and improving the protection capability of the chip-related structure. The above ESD circuit can improve the electrostatic discharge capability from multiple aspects, thereby improving the protection capability of the chip-related structure.
[0032] In some embodiments, referring to Figure 3 The bias signal providing unit 110 includes a Wilson current mirror 111 and a nano-ampere current branch 112.
[0033] The nano-ampere current branch 112 is configured to provide a nano-ampere current.
[0034] The input end of the Wilson current mirror 111 is connected to the output end of the nano-ampere current branch 112, the output end is connected to the substrate of each discharge MOS tube N1 as the signal providing end of the bias signal providing unit 111, and is configured to mirror process the nano-ampere current and provide the mirror-processed current to the substrate of each discharge MOS tube N1 as the preset bias signal, so that each discharge MOS tube N1 is in a weak conduction state when the ESD current passes through the discharge MOS tube N1.
[0035] The embodiment adopts the Wilson current mirror 111 to mirror process the nano-ampere level current, which can improve the linearity and reliability in the mirror process, so as to provide a more stable and reliable small current signal or small voltage signal to the substrate level of the discharge MOS tube N1.
[0036] In some examples, the Wilson current mirror 111 includes a first MOS tube P1, a second MOS tube P2, a third MOS tube P3, a fourth MOS tube N2 and a fifth MOS tube N3. Specifically, the first MOS tube P1, the second MOS tube P2 and the third MOS tube P3 are PMOS tubes; the fourth MOS tube N2 and the fifth MOS tube N3 are NMOS tubes.
[0037] The source of the first MOS tube P1 is connected to the chip pin PAD, the drain is used as the output end of the Wilson current mirror 111, and the gate is connected to the gate of the second MOS tube P2, the gate of the third MOS tube P3, the drain of the fourth MOS tube N2 and the drain of the third MOS tube P3 respectively. The source of the second MOS tube P2 and the source of the third MOS tube P3 are connected to the chip pin PAD respectively. The source of the fourth MOS tube N2 is grounded, and the gate is connected to the gate of the fifth MOS tube N3, the drain of the fifth MOS tube N3 and the drain of the third MOS tube P3 respectively. The source of the fifth MOS tube N3 is connected to the output end of the nano-ampere level current branch 112.
[0038] Specifically, the nano-ampere level current branch 112 includes a second resistor R2; the first end of the second resistor R2 is used as the output end of the nano-ampere level current branch 112, and the second end is grounded.
[0039] Optionally, the resistance value of the second resistor R2 is 100MΩ, so that the current passing through the second resistor R2 is a nano-ampere level current.
[0040] The second resistor R2 is set to 100MΩ in the example, thereby providing a nano-ampere level current branch, and the Wilson current mirror 111 provides a small bias voltage (such as 0.7V) to the parasitic diode of the discharge MOS tube N1, so that the discharge MOS tube N1 is in a weak conduction state.
[0041] In some embodiments, as shown in Figure 1 , Figure 3 and Figure 4 , the secondary discharge module 200 includes a third resistor R3 and a jfet (junction field effect transistor) tube Jfet (also referred to as jfet mos tube).
[0042] The first end of the third resistor R3 is connected to the chip pin as the first end of the secondary discharge module 200, and the second end of the third resistor R3 is connected to the source of the jfet tube Jfet as the second end of the secondary discharge module 200. The gate of the jfet tube Jfet is connected to the drain of the jfet tube Jfet and the internal circuit of the chip, respectively.
[0043] Optionally, the resistance value of the third resistor R3 ranges from 1kΩ to 10kΩ.
[0044] In this embodiment, the secondary discharge module 200 can use the pinch-off characteristic of the jfet tube Jfet to pinch off the voltage near the internal circuit of the chip to below 5V, thereby protecting the internal circuit of the chip from being affected and further improving the protection capability of the secondary discharge module 200.
[0045] In the above ESD circuit, the bias signal providing unit 110 is configured to provide a preset bias signal for each discharge MOS tube N1, so that each discharge MOS tube N1 is in a weak conduction state when the static energy is discharged through each discharge MOS tube N1. In this way, when the ESD current flows through the discharge MOS tube N1, the discharge MOS tube N1 can be uniformly turned on to improve the discharge capability of each discharge MOS tube N1. In addition, the secondary discharge module 200 can further discharge the static energy at the chip pin when the energy discharge of the primary discharge module 100 is not complete, thereby protecting the chip-related structure again and improving the protection capability of the chip-related structure. In addition, the secondary discharge module 200 can use the pinch-off characteristic of the jfet tube Jfet to pinch off the voltage near the internal circuit of the chip to below 5V, thereby protecting the internal circuit of the chip from being affected and further improving the protection capability of the secondary discharge module 200. The above ESD circuit can improve the protection capability of the chip-related structure from multiple aspects.
[0046] The second aspect of the present application provides a chip, which includes at least one ESD circuit described in any of the above embodiments. Specifically, the ESD circuit can be arranged at the pin of the chip that needs to be protected from static discharge. Each pin that needs to be protected from static discharge can correspond to an ESD circuit.
[0047] The above chip includes the ESD circuit described in any of the above embodiments, and has all the beneficial effects of the ESD circuit described in any of the above embodiments, which will not be repeated here.
[0048] Although the present application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based on the foregoing description and accompanying drawings. The application includes all such modifications and alterations and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the above described components, the terms (e.g., "means for") used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the exemplary implementation illustrated by the present application. In this manner, and other ways, the application is intended to cover any and all equivalents.
[0049] That is, the above-described embodiments are merely exemplary implementations of the present application, and do not limit the patent scope of the present application, and equivalent structures or equivalent processes made by using the contents of the present application specification and drawings, such as the mutual combination of technical features between embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.
[0050] In addition, in the description of the present application, it should be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, for structural elements with the same or similar properties, the present application can use the same or different reference numerals for identification. Furthermore, the terms "first", "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features referred to. Therefore, the features with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.
[0051] In this application, the use of the singular includes the plural unless specifically stated otherwise. In this application, the use of "or" means "and / or" unless stated otherwise. In this application, the use of "an" includes "one or more". In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at least a third" unless context clearly states otherwise. In this application, the use of "another" means "at least a second" or "at
Claims
1. An ESD circuit, characterized in that: The ESD circuit includes a primary discharge module and a secondary discharge module; the primary discharge module includes a discharge MOS tube, a bias signal providing unit and a first resistor corresponding to each discharge MOS tube; The drain of the discharge MOS tube is connected to the chip pin, the gate is grounded through the corresponding first resistor, the source is grounded, and the substrate is connected to the signal providing end of the bias signal providing unit; The first end of the secondary discharge module is connected to the chip pin, and the second end is connected to the internal circuit of the chip; The first-level discharge module is used to discharge the electrostatic energy at the chip pin by connecting the discharge MOS tube; The secondary discharge module is used to further discharge the electrostatic energy at the chip pin and clamp the voltage of the second end to below a preset voltage; The bias signal providing unit is used to provide a preset bias signal for the discharge MOS transistor, so that when the electrostatic energy passes through the discharge MOS transistor, the discharge MOS transistor is in a weak conduction state.
2. The ESD circuit according to claim 1, wherein: The bias signal providing unit includes a Wilson current mirror and a nanoampere current branch; The nanoampere-level current branch is used to provide nanoampere-level current; The input end of the Wilson current mirror is connected to the output end of the nanoampere current branch, and the output end serves as the signal providing end of the bias signal providing unit, and is connected to the substrate level of the discharge MOS tube, for performing mirror processing on the nanoampere current and providing the mirrored current as the preset bias signal to the substrate level of the discharge MOS tube.
3. The ESD circuit according to claim 2, wherein: The Wilson current mirror includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor; The source of the first MOS transistor is connected to the chip pin, the drain serves as the output end of the Wilson current mirror, and the gate is respectively connected to the gate of the second MOS transistor, the gate of the third MOS transistor, the drain of the fourth MOS transistor, and the drain of the third MOS transistor; The source of the second MOS tube and the source of the third MOS tube are respectively connected to the chip pins; the source of the fourth MOS tube is grounded, and the gate is respectively connected to the gate of the fifth MOS tube, the drain of the fifth MOS tube and the drain of the third MOS tube; the source of the fifth MOS tube is connected to the output end of the nanoampere current branch.
4. The ESD circuit according to claim 3, wherein: The first MOS transistor, the second MOS transistor, and the third MOS transistor are PMOS transistors; the fourth MOS transistor and the fifth MOS transistor are NMOS transistors.
5. The ESD circuit according to claim 2, wherein: The nanoampere level current branch includes a second resistor; The first end of the second resistor serves as the output end of the nanoampere current branch, and the second end is grounded.
6. The ESD circuit according to claim 5, wherein: The resistance of the second resistor is 100 MΩ.
7. The ESD circuit according to claim 1, wherein: The secondary discharge module includes a third resistor and a jfet tube; The first end of the third resistor is connected to the chip pin, and the second end is connected to the source of the jfet tube; the gate of the jfet tube is respectively connected to the drain of the jfet tube and the internal circuit of the chip.
8. The ESD circuit according to claim 7, wherein: The resistance value of the third resistor ranges from 1 kΩ to 10 kΩ.
9. A chip, characterized in that: The chip includes at least one ESD circuit according to any one of claims 1 to 8.