Buffer circuit for bidirectional level conversion

Abstract

The utility model discloses a buffer circuit for bidirectional level conversion. The buffer circuit comprises a first accelerator module circuit, a second accelerator module circuit, a switch control module circuit, an LVST circuit and an M2 transistor, the input end of the first accelerator module circuit, the input end of the switch control module circuit and the input end of the LVST circuit input EN enable signals; the output end of the LVST circuit is electrically connected with the second accelerator module circuit; the grid electrode, the source electrode and the drain electrode of the M2 transistor are electrically connected with the output end of the switch control module circuit, the output end of the first accelerator module circuit and the output end of the second accelerator module circuit respectively; the first accelerator module circuit and the second accelerator module circuit respectively detect potential changes of two ports of the source electrode and the drain electrode of the M2 transistor, and pull up or pull down the potential of the ports to realize level conversion during level conversion; and a bidirectional level conversion technology is adopted, so that compatibility of the Flash chip to different SPI protocols and different voltage domains are met.

Description

TECHNICAL FIELD

[0001] The utility model discloses integrated circuit design field, especially relate to a bidirectional level conversion buffer circuit. BACKGROUND

[0002] The new Flash chip on the market supports SPI protocol, QSPI and DSPI protocol, wherein QSPI and DSPI have two and four bidirectional transmission ports respectively, so the traditional unidirectional buffer cannot meet the existing demand. In addition, the traditional buffer has no means to suppress power supply noise, and when the external voltage fluctuates, it will cause signal transmission error, and further cause the Flash chip to work abnormally. The common Flash buffer circuit implementation method mainly adopts two-stage inverter architecture to realize enhanced driving circuit capability, level conversion and other functions. But this design scheme can only be used for traditional serial peripheral interface device SPI, and cannot meet the needs of two-bit serial peripheral interface device DSPI and four-bit serial peripheral interface device QSPI. SUMMARY

[0003] The utility model discloses a bidirectional level conversion buffer circuit, adopts bidirectional level conversion technology, and meets the compatibility of different SPI protocols and the voltage domain difference of Flash chip.

[0004] Technical scheme: in order to realize the above-mentioned purpose, a bidirectional level conversion buffer circuit of the utility model, including first accelerator module circuit, second accelerator module circuit, switch control module circuit, LVST circuit and M2 transistor, the input of first accelerator module circuit, the input of switch control module circuit and the input of LVST circuit input EN enable signal, the output of LVST circuit is electrically connected with second accelerator module circuit, the grid, source and drain of M2 transistor are electrically connected with the output of switch control module circuit, the output of first accelerator module circuit and the output of second accelerator module circuit respectively, the source and drain of M2 transistor are two ports of buffer circuit respectively, and the first accelerator module circuit and second accelerator module circuit detect two port potential changes respectively, and when level conversion, the potential of port is pulled up or pulled down to realize the conversion of level.

[0005] Further, the source of the M2 transistor is electrically connected to the VCCA power supply through the R3 constant pull-up resistor, and the drain of the M2 transistor is electrically connected to the VCCB power supply through the R4 constant pull-up resistor.

[0006] Further, the LVST circuit comprises MP1 transistor, MP2 transistor, MN1 transistor and MN2 transistor; the drain of the MP1 transistor is electrically connected with the drain of the MN1 transistor and the gate of the MP2 transistor, the drain of the MP2 transistor is electrically connected with the drain of the MN2 transistor and the gate of the MP1 transistor; the gate of the MN1 transistor is the input end of the LVST level conversion circuit, and the drain of the MP2 transistor is the output end of the LVST circuit.

[0007] Further, the gate of the MN1 transistor inputs an IN signal, and the gate of the MN2 transistor inputs an INN signal obtained by taking inversion of the IN signal.

[0008] Further, the first accelerator module circuit and the second accelerator module circuit each comprise an inverter, MP3 transistor and MN3 transistor; the input end of the inverter inputs an EN enabling signal, the output end of the inverter is electrically connected with one input end of an NAND gate circuit and one input end of an NOR gate circuit through an R5 resistor, and the other input end of the NAND gate circuit and the other input end of the NOR gate circuit each input the EN enabling signal; the output end of the NAND gate circuit is electrically connected with the gate of the MP3 transistor, and the output end of the NOR gate circuit is electrically connected with the gate of the MN3 transistor; the drain of the MP3 transistor is electrically connected with the drain of the MN3 transistor, and serves as an output end.

[0009] Further, the output end of the inverter is electrically connected with one end of a plate of a C1 capacitor through the R5 resistor, and the other end of the plate of the C1 capacitor is grounded, so that the R5 resistor and the C1 capacitor form an RC network to delay the signal inputted by the input end of the inverter.

[0010] Further, the source of the MP3 transistor in the first accelerator module circuit is electrically connected with a VCCA power supply, and the source of the MP3 transistor in the second accelerator module circuit is electrically connected with a VCCB power supply.

[0011] Beneficial effects: the bidirectional level conversion buffer circuit can meet the compatibility of different SPI protocols and the problem of different voltage domains of the Flash chip, effectively suppresses the interference of power supply noise on the internal chip, and realizes the compatibility problem and voltage conversion problem between different SPIs. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 It is a buffer circuit diagram for port detection and level conversion;

[0013] Figure 2 It is an LVST level conversion circuit diagram;

[0014] Figure 3To accelerate the module circuit. DETAILED DESCRIPTION

[0015] The utility model will be further explained in connection with the drawings.

[0016] As Figure 1 shown, in order to meet the needs of two serial peripheral interface device DSPI and four serial peripheral interface device QSPI, design a bidirectional level conversion buffer circuit, including first accelerator module circuit 1, second accelerator module circuit 2, switch control module circuit 3, LVST circuit 4 and M2 transistor 5;The input end of first accelerator module circuit 1, the input end of switch control module circuit 3 and the input end of LVST circuit 4 input EN enable signal;The output end of LVST circuit 4 is electrically connected with second accelerator module circuit 2;The gate, source and drain of M2 transistor 5 are electrically connected with the output end of switch control module circuit 3, the output end of first accelerator module circuit 1 and the output end of second accelerator module circuit 2 respectively;The source and drain of M2 transistor 5 are two ports of buffer circuit respectively, and the first accelerator module circuit 1 and the second accelerator module circuit 2 detect the potential change of two ports respectively, and when level conversion, the potential of port is pulled up or pulled down to realize the conversion of level.The first accelerator module 1 and the second accelerator module 2 are disposable self-accelerating module circuits;The LVST circuit is a level conversion circuit.The two ports of the port detection and level conversion buffer circuit are I / O ports, and any one port of the two ports is electrically connected with the Flash chip.

[0017] The source of M2 transistor 5 is electrically connected with VCCA power supply through R3 constant pull-up resistance, and the drain of M2 transistor 5 is electrically connected with VCCB power supply through R4 constant pull-up resistance.

[0018] As Figure 2 shown, the LVST circuit 4 includes MP1 transistor 21, MP2 transistor 22, MN1 transistor 23 and MN2 transistor 24;The drain of MP1 transistor 21 is electrically connected with the drain of MN1 transistor 23 and the gate of MP2 transistor 22, and the drain of MP2 transistor 22 is electrically connected with the drain of MN2 transistor 24 and the gate of MP1 transistor 21;The gate of MN1 transistor 23 is the input end of LVST level conversion circuit, and the drain of MP2 transistor 22 is the output end of LVST circuit 4.MN1 transistor and MN2 transistor are level conversion input pair tubes, MP1 transistor and MP2 transistor are load tubes, and they are cross-connected to constitute positive feedback, thereby ensuring the normal work of the circuit.

[0019] The gate of the MN1 transistor 23 inputs the IN signal, and the gate of the MN2 transistor 24 inputs the INN signal obtained by inverting the IN signal. At this time, the input IN signal is the EN signal, and the INN signal is the inverted EN signal.

[0020] As shown in Figure 3 The first accelerator module circuit 1 and the second accelerator module circuit 2 each include an inverter 11, an MP3 transistor 12, and an MN3 transistor 13. The input end of the inverter 11 inputs the EN signal, and the output end of the inverter 11 is electrically connected to one input end of an NAND gate circuit 14 and one input end of an NOR gate circuit 15 through an R5 resistor. The other input end of the NAND gate circuit 14 and the other input end of the NOR gate circuit 15 each input the EN signal. The output end of the NAND gate circuit 14 is electrically connected to the gate of the MP3 transistor 12, and the output end of the NOR gate circuit 15 is electrically connected to the gate of the MN3 transistor 13. The drain of the MP3 transistor 12 is electrically connected to the drain of the MN3 transistor 13, and serves as an output end.

[0021] The output end of the inverter 11 is electrically connected to one end plate of a C1 capacitor through an R5 resistor, and the other end plate of the C1 capacitor is grounded. The R5 resistor and the C1 capacitor constitute an RC network to delay the signal input to the input end of the inverter 11. After the input IN signal is inverted by the inverter and delayed by the RC network, an IN1 signal is generated, and the IN1 signal and the original IN signal are combined by the NAND gate circuit. The signal output by the NAND gate circuit controls the MP3 transistor and the MN3 transistor to be temporarily turned on or turned off, and outputs a high potential or a low potential, so as to realize the pull-up or pull-down operation of the M2 transistor.

[0022] The source of the MP3 transistor in the first accelerator module circuit 1 is electrically connected to a VCCA power supply, and inputs a VCCA voltage signal to the first accelerator module circuit 1. The source of the MP3 transistor in the second accelerator module circuit 2 is electrically connected to a VCCB power supply, and inputs a VCCB voltage signal to the second accelerator module circuit 2. The VCCA voltage signal output by the VCCA power supply and the VCCA voltage signal output by the VCCB power supply have different potentials, so that an LVST circuit is added to the input end of the second accelerator module circuit 2 to convert the input EN signal into a VCCB voltage signal input to the second accelerator module circuit 2, thereby preventing the circuit from leaking electricity. The input end of the first accelerator module circuit 1 directly inputs the EN signal.

[0023] The first acceleration module circuit or the second acceleration module circuit respectively detects the potential change of the two ports, can automatically detect the source of the input signal, thereby determining the transmission direction and realizing the level conversion; when the potential of any one port of the two port I / O ports changes, the level conversion is needed at this time; the EN enable signal is input into the first acceleration module circuit or indirectly into the second acceleration module circuit to control the output of high potential or low potential, and the level conversion is performed. When the level conversion is performed, a high potential or a low potential is output through the first acceleration module circuit or the second acceleration module circuit, thereby controlling the pull-up or pull-down NMOS tube on the other end, and thereby completing the level conversion operation of the two ends.

[0024] The above is only the description of the preferred embodiment of the present application, and those skilled in the art can make some modifications and optimizations according to the above disclosure without departing from the above basic principles. These improvements and optimizations should be considered as the protection scope of the present application.

Claims

1. A bidirectional level conversion buffer circuit, characterized in that: The invention comprises a first accelerator module circuit (1), a second accelerator module circuit (2), a switch control module circuit (3), an LVST circuit (4) and an M2 transistor (5); an EN enable signal is input to the input end of the first accelerator module circuit (1), the input end of the switch control module circuit (3) and the input end of the LVST circuit (4); the output end of the LVST circuit (4) is electrically connected to the second accelerator module circuit (2); the gate, source and drain of the M2 transistor (5) are respectively electrically connected to the output end of the switch control module circuit (3), the output end of the first accelerator module circuit (1) and the output end of the second accelerator module circuit (2); the source and drain of the M2 transistor (5) are respectively two ports of a buffer circuit; the first accelerator module circuit (1) and the second accelerator module circuit (2) respectively detect potential changes of the two ports, and when the level is converted, the potential of the port is pulled up or pulled down to realize the level conversion.

2. The bidirectional level conversion buffer circuit according to claim 1, wherein: The source of the M2 transistor (5) is electrically connected to the VCCA power supply via the R3 pull-up resistor, and the drain of the M2 transistor (5) is electrically connected to the VCCB power supply via the R4 pull-up resistor.

3. The bidirectional level conversion buffer circuit according to claim 1, wherein: The LVST circuit (4) comprises an MP1 transistor (21), an MP2 transistor (22), an MN1 transistor (23) and an MN2 transistor (24); the drain of the MP1 transistor (21) is electrically connected to the drain of the MN1 transistor (23) and the gate of the MP2 transistor (22); the drain of the MP2 transistor (22) is electrically connected to the drain of the MN2 transistor (24) and the gate of the MP1 transistor (21); the gate of the MN1 transistor (23) is the input end of the LVST level conversion circuit, and the drain of the MP2 transistor (22) is the output end of the LVST circuit (4).

4. The bidirectional level conversion buffer circuit according to claim 3, wherein: The gate of the MN1 transistor (23) inputs the IN signal, and the gate of the MN2 transistor (24) inputs the INN signal obtained by inverting the IN signal.

5. The bidirectional level conversion buffer circuit according to claim 1, wherein: The first accelerator module circuit (1) and the second accelerator module circuit (2) both include an inverter (11), an MP3 transistor (12) and an MN3 transistor (13); an EN enable signal is input to the input end of the inverter (11); an output end of the inverter (11) is electrically connected to an input end of a NAND gate circuit (14) and an input end of a NOR gate circuit (15) through an R5 resistor; the other input end of the NAND gate circuit (14) and the other input end of the NOR gate circuit (15) both input the EN enable signal; the output end of the NAND gate circuit (14) is electrically connected to the gate of the MP3 transistor (12); the output end of the NOR gate circuit (15) is electrically connected to the gate of the MN3 transistor (13); the drain of the MP3 transistor (12) is electrically connected to the drain of the MN3 transistor (13) and serves as an output end.

6. The bidirectional level conversion buffer circuit according to claim 5, wherein: The output end of the inverter (11) is electrically connected to one end plate of the C1 capacitor through the R5 resistor, and the other end plate of the C1 capacitor is grounded. The R5 resistor and the C1 capacitor form an RC network to delay the signal input to the input end of the inverter (11).

7. The bidirectional level conversion buffer circuit according to claim 5, wherein: The source of the MP3 transistor in the first accelerator module circuit (1) is electrically connected to the VCCA power supply, and the source of the MP3 transistor in the second accelerator module circuit (2) is electrically connected to the VCCB power supply.

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