Packaging structure based on ultrathin chip of 2nm and below

Abstract

The utility model discloses a packaging structure based on an ultrathin chip of 2nm and below, which can be used as an electrical connection channel through the arrangement of a vertical metal column, can increase the sectional area of current transmission, and meets the packaging requirement of large current. Therefore, the heat dissipation efficiency is improved. By arranging the adapter plate on the substrate and inversely connecting the first chip with the thickness of 2nm and below, smaller packaging height and size are realized. The first chip is connected to the adapter plate in an inverted manner, so that the back surface of the first chip faces upwards and can be matched with the transverse metal block and the conductive material layer to form a conductive network to realize wafer back power supply, a power supply path can be shortened, resistance can be reduced, IR voltage drop is remarkably reduced, and power supply efficiency is improved. The substrate is provided with the integrally-formed vertical metal columns in the feeding process, the welding and connecting steps in the assembling process are reduced, and therefore the production efficiency is improved, and the vertical metal columns are suitable for manufacturers with high requirements for the production efficiency.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor packaging, and particularly relates to a packaging structure based on 2nm and below ultra-thin chips. BACKGROUND

[0002] With the rapid development of semiconductor technology, chip manufacturing processes are constantly advancing to finer scales, especially in the 2nm and below process era, the integration and performance of chips have been unprecedentedly improved. However, this technological progress has also brought many challenges, especially in the field of chip packaging. The traditional packaging technology has been difficult to meet the stringent requirements of these high-end chips for power supply efficiency, thermal management and physical size control.

[0003] For 2nm and below process chips, their power density increases significantly, combined with the explosive growth of the number of transistors inside the chip, making resistance control of the power supply line critical. High resistance not only leads to energy waste, but also may cause voltage drop, affecting the stability and performance of the chip. At the same time, high power consumption also means more heat, how to effectively dissipate heat and prevent performance degradation or damage caused by overheating of the chip has become a problem to be solved.

[0004] Therefore, it is particularly important to develop a packaging structure that can realize low resistance, large current power supply and has high heat dissipation capacity. SUMMARY

[0005] The utility model overcomes the above technical insufficiency and provides a packaging structure based on 2nm and below ultra-thin chips.

[0006] To achieve the above purpose, the utility model adopts the following technical scheme:

[0007] A packaging structure based on 2nm and below ultra-thin chips, comprising a substrate 1, the substrate 1 is connected with an adapter plate 2 on its upper surface, a first chip 3 with a thickness of 2nm and below is flip-chip mounted on the upper surface of the adapter plate 2, the back surface of the first chip 3 is provided with a plurality of first metal contacts 31, and the substrate 1 is correspondingly formed with a plurality of vertically extending vertical metal columns 11 according to the number of the first metal contacts 31; the vertical metal column 11 is an integral molding structure, the bottom of which is embedded into the top of the substrate 1 and vertically extends upward to the same height as the back surface of the first chip 3; each first metal contact 31 is provided with a first conductive material layer 41 on its surface, and each vertical metal column 11 is provided with a second conductive material layer 42 on its upper surface; the first conductive material layer 41 and the second conductive material layer 42 are conductively connected through a transverse metal block 5.

[0008] Preferably, the vertical metal column 11 is a metal column made of high-conductivity metal, and the transverse metal block 5 is a metal block made of high-conductivity metal.

[0009] Preferably, the substrate 1 is provided with a chip mounting area 110 and a back side power supply area 120 arranged on both sides of the chip mounting area 110, the substrate 1 is provided with a plurality of first solder balls 6 on the upper surface of the chip mounting area 110, the vertical metal columns 11 are arranged on the back side power supply area 120, the adapter plate 2 is provided with a plurality of first solder joints 21 corresponding to the first solder balls 6 on the lower surface of the adapter plate 2; each back side power supply area 120 is provided with a plurality of vertical metal columns 11

[0010] Preferably, the first solder joints 21 are arranged on the lower surface of the adapter plate 2, and the vertical metal columns 11 are arranged on the back side power supply area 120.

[0011] Preferably, the first chip 3 is provided with a plurality of second metal contacts 32 on the front surface, and the adapter plate 2 is provided with second solder joints 22 embedded into the top and connected with the second metal contacts 32 on the upper surface of the adapter plate 2.

[0012] Preferably, a filling glue layer 7 is arranged in the gap between the lower surface of the adapter plate 2 and the upper surface of the substrate 1 to fill the gap.

[0013] Preferably, the upper surface of the substrate 1 is provided with a plastic sealing layer 8 for encapsulating all components into one body.

[0014] Preferably, the first conductive material layer 41 and the second conductive material layer 42 are tin paste layers or conductive glue layers.

[0015] Preferably, the substrate 1 is an FCBGA packaging substrate.

[0016] Compared with the prior art, the utility model has the advantages of:

[0017] 1. The packaging structure can meet the requirements of low resistance, large current and strong heat dissipation capacity of 2nm and below chips. The vertical metal column is formed on the substrate, and the first metal contact on the back of the chip is connected by the first conductive material layer, the second conductive material layer and the horizontal metal block, which significantly reduces the resistance of the power supply circuit, reduces the energy loss in the signal transmission process, improves the power supply efficiency, and ensures the stable operation of the chip under high power consumption. The vertical metal column can be used as an electrical connection channel and a heat conduction path, so that the heat generated during the operation of the chip can be more effectively conducted to the substrate, which is beneficial to improve the heat dissipation efficiency. The adapter plate is arranged on the substrate, and the first chip with a thickness of 2nm or below is inverted on the basis, realizing the high integration between the chip and the substrate, and realizing smaller packaging height and smaller physical size. The first chip is connected to the adapter plate in an inverted manner, so that the back of the first chip faces up, and the back of the chip can be powered by the above-mentioned conductive network, which can shorten the power supply path and reduce the resistance, thereby significantly reducing the IR drop and improving the power supply efficiency. On the other hand, the front of the chip powered by the back can appropriately reduce the circuit density, which helps to improve the heat dissipation condition and improve the reliability and stability of the chip. Since the thickness of the first chip is small, the adapter plate can also play a certain heightening role, so that the first metal contact connected to the back of the first chip through the vertical metal column and the horizontal metal block. The substrate has an integrally formed vertical metal column according to the requirements of the packaged chip when it is delivered, and does not need to be stacked to the same height as the first chip by mounting, reducing the welding and connection steps in the assembly process, thereby improving the production efficiency, and being suitable for production manufacturers with high requirements for production efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a cross-sectional structure schematic diagram of the present application.

[0019] Figure 2 is a structure schematic diagram of the substrate of the present application.

[0020] Figure 3 is a top view structure schematic diagram of the present application without a plastic sealing layer and a horizontal metal block.

[0021] Figure 4 is a top view structure schematic diagram of the present application without a plastic sealing layer. DETAILED DESCRIPTION

[0022] The features of the present application and other related features are further described in detail by the following examples, so as to be understood by the technical personnel in the same industry:

[0023] As Figure 1 and Figure 4As shown, a packaging structure based on 2nm and below ultra-thin chip includes a substrate 1, a conversion board 2 connected to the upper surface of the substrate 1, a first chip 3 with a thickness of 2nm and below flip-chip mounted on the upper surface of the conversion board 2, and a plurality of first metal contacts 31 provided on the back surface of the first chip 3. The substrate 1 is provided with a plurality of vertically extending vertical metal columns 11 corresponding to the number of first metal contacts 31. The vertical metal columns 11 are integrally formed, with the bottom embedded into the top of the substrate 1 and vertically extending upward to the same height as the back surface of the first chip 3. Each first metal contact 31 is provided with a first conductive material layer 41 on the surface, and each vertical metal column 11 is provided with a second conductive material layer 42 on the upper surface. The first conductive material layer 41 and the second conductive material layer 42 are conductively connected through a transverse metal block 5. In specific implementation, the substrate 1 is provided with integrally formed vertical metal columns 11 according to the requirements of the first chip to be packaged when delivered. The transverse metal block is attached in the form of SMT.

[0024] As described above, the present application provides a packaging structure that can meet the requirements of low resistance, large current and strong heat dissipation of 2nm and below chips. By forming integrally formed vertical metal columns 11 on the substrate 1 and connecting the first metal contacts 31 on the back surface of the chip through the first conductive material layer, the second conductive material layer and the transverse metal block 5, the resistance of the power supply circuit is significantly reduced, thereby reducing the energy loss in the signal transmission process, improving the power supply efficiency and ensuring the stable operation of the chip under high power consumption. Moreover, the vertical metal columns 11 can serve as both an electrical connection channel and a heat conduction path, so as to more effectively conduct the heat generated by the chip during operation to the substrate 1, thereby improving the heat dissipation efficiency. By providing the conversion board 2 on the substrate 1 and flip-chipping the first chip 3 with a thickness of 2nm and below on the basis of the conversion board 2, the high integration between the chip and the substrate is achieved, and smaller packaging height and smaller physical size can be realized. The first chip 3 is connected to the conversion board in a flip-chip manner, with the back surface of the first chip 3 facing upward, so as to realize back surface power supply in cooperation with the above-mentioned conductive network. On the one hand, the power supply path can be shortened and the resistance can be reduced, thereby significantly reducing the IR drop and improving the power supply efficiency. On the other hand, the front surface of the chip for back surface power supply can appropriately reduce the circuit density, which helps to improve the heat dissipation condition and improve the reliability and stability of the chip. Since the first chip 3 has a small thickness, the conversion board can also serve as a certain heightening function, so as to facilitate the subsequent connection of the first metal contacts 31 on the back surface of the first chip 3 through the vertical metal columns and the transverse metal block. In addition, the substrate 1 is provided with integrally formed vertical metal columns 11 according to the requirements of the chip to be packaged when delivered, without the need for stacking to the same height as the first chip through mounting, thereby reducing the welding and connection steps in the assembly process, improving the production efficiency and being suitable for production manufacturers with high requirements for production efficiency.

[0025] Further, the first chip 3 is provided with a first metal contact 31 on the back surface, so that all the electrodes are not concentrated on the front surface, and a larger metal contact can be provided on the back surface, so that a larger transverse metal block can be provided and connected, and the larger transverse metal block is connected in a manner to meet the needs of low resistance and large current. Each vertical metal column 11 is provided at the same height as the back surface of the first chip 3, so that the vertical metal column 11 and the back surface of the first chip can be directly connected by a common transverse extension square metal block, without the need for complex design, while ensuring heat transfer and electrical conductivity, and saving costs. Moreover, the equal height design makes the transverse metal block closely fit the back surface of the first chip, reducing the path length that the current needs to bypass during transmission, and can reduce energy loss and electromagnetic interference during signal transmission, and improve electrical performance.

[0026] As a specific embodiment, the vertical metal column 11 is a metal column made of a high-conductivity metal, and the transverse metal block 5 is a metal block made of a high-conductivity metal. In specific implementation, the high-conductivity metal is copper, aluminum or an alloy thereof, etc., and is preferably copper metal. In this way, the vertical metal column 11 and the transverse metal block 5 of the present application have excellent electrical conductivity, which can significantly reduce resistance and improve current transmission efficiency. In addition, the manufacturing process of copper columns or other metal columns is a large number of mature processes on the market, which is simple to manufacture and cost controllable.

[0027] As shown in Figure 3 In specific implementation, the substrate 1 is provided with a chip mounting area 110 and a back surface power supply area 120 provided on both sides of the chip mounting area 110. The substrate 1 is provided with a plurality of first solder balls 6 on the upper surface of the chip mounting area 110, and the vertical metal column 11 is formed on the back surface power supply area 120. The adapter plate 2 is provided with a plurality of first solder points 21 corresponding to the first solder balls 6 on the lower surface. Each side back surface power supply area 120 is provided with a plurality of vertical metal columns 11.

[0028] As described above, the substrate divides the chip mounting area 110 and the back supply area 120, which can reasonably layout the packaging structure and facilitate subsequent packaging. By protruding a plurality of first solder balls 7 on the upper surface of the chip mounting area 110, the first solder balls 7 are directly connected with the first solder joints 21 on the adapter plate 2, which simplifies the packaging process and improves the integration and efficiency of packaging. The back supply area 120 is arranged on both sides of the chip mounting area 110, and the vertical metal block 5 is connected by the second conductive material layer 42, which effectively utilizes the space of the substrate and optimizes the power supply path, making the power supply more stable and reliable, and reducing the voltage drop and signal interference that may be caused by long distance power supply lines. The direct connection between the first solder ball 7 and the first solder joint 21 provides a short and direct current path, which helps to reduce inductance and resistance, thereby reducing energy loss and electromagnetic interference in the signal transmission process. Moreover, the contact area between the solder ball and the solder joint is relatively large, which helps to conduct and dissipate heat. The arrangement of a plurality of vertical metal columns 11 can more effectively disperse current and reduce the problem of heat concentration caused by excessive current at a single point, which helps to reduce the temperature of the substrate 1 and the chip, and improve the stability and life of the system.

[0029] As shown in Figure 1 or Figure 2 or Figure 4 In specific implementation, the first solder joint 21 is protruded on the lower surface of the adapter plate 2, and the vertical metal column 11 is protruded on the back supply area 120. In this way, the first solder joint 21 is protruded on the lower surface of the adapter plate 2, which makes more efficient use of the space on the substrate 1, and helps to improve the integration and density of packaging. Moreover, the protruded first solder joint 21 facilitates the transfer of heat generated by the first chip to the substrate 1, improving the heat dissipation efficiency.

[0030] As shown in Figure 1 In specific implementation, the first chip 3 is provided with a plurality of second metal contacts 32 on the front surface, and the adapter plate 2 is provided with a second solder joint 22 embedded into the top and connected with the second metal contact 32 on the upper surface. In this way, the second solder joint 22 is embedded into the top of the adapter plate 2 and tightly connected with the second metal contact 32, which helps to reduce the contact resistance and improve the stability and reliability of the electrical connection. At the same time, since the second solder joint 22 is embedded in the adapter plate, on the one hand, it reduces the influence of the external environment on the electrical connection, and on the other hand, it does not increase the height of the upper surface of the adapter plate 2, which is conducive to improving the integration of the packaging structure of the present application.

[0031] As shown in Figure 1As shown, the gap between the lower surface of the adapter plate 2 and the upper surface of the substrate 1 is filled with a filling adhesive layer 7. In this way, the filling adhesive layer 7 can firmly bond the adapter plate 2 and the substrate 1 after curing, thereby enhancing the connection strength between them. On the other hand, the filling adhesive layer 7 can have good thermal conductivity to facilitate the transfer of heat generated by the chip to the substrate 1, thereby further improving the heat dissipation efficiency. Moreover, the filling adhesive layer 7 can fill the small gap between the adapter plate 2 and the substrate 1, thereby reducing the thermal resistance and improving the thermal conductivity efficiency.

[0032] As shown in the drawings, Figure 1 The upper surface of the substrate 1 is provided with a plastic encapsulation layer 8 for encapsulating all components into one body. In this way, all components can be encapsulated into one body to facilitate insulation protection and moisture-proofing of the internal components. In specific implementation, the plastic encapsulation layer 8 is usually made of epoxy resin material.

[0033] As a preferred embodiment, the first conductive material layer 41 and the second conductive material layer 42 are tin paste layers or conductive adhesive layers. In this way, the tin paste layers or conductive adhesive layers are selected as the first conductive material layer 41, the second conductive material layer 42 and the third conductive material layer 43 to meet the requirements of conductivity and heat dissipation. Moreover, the tin paste layers and the conductive adhesive layers are commonly used conductive materials in the packaging process, thereby reducing the complexity and cost of the packaging process.

[0034] As a preferred embodiment, the substrate is an FCBGA packaging substrate. In this way, the adoption of the FCBGA packaging substrate can realize flip-chip technology, i.e., the chip is inverted and attached to the substrate, thereby realizing the power supply of the back of the chip for 2nm and below chips in the subsequent process, without the need for using wires to connect the chip and the substrate, thereby achieving higher integration and higher density packaging.

[0035] As mentioned above, the present application protects a packaging structure based on 2nm and below ultra-thin chips, and all technical solutions identical or similar to the present application shall be deemed to fall within the protection scope of the present application.

Claims

1. A packaging structure based on 2 nm and below ultra-thin chip comprising a substrate (1), characterized in that The substrate (1) is connected with an adapter plate (2) on its upper surface, a first chip (3) with a thickness of 2nm or less is flip-chip mounted on the upper surface of the adapter plate (2), a plurality of first metal contacts (31) are arranged on the back surface of the first chip (3), and a plurality of vertical metal columns (11) are formed on the substrate (1) according to the number of the first metal contacts (31); the vertical metal column (11) is an integral molding structure, the bottom of which is embedded into the top of the substrate (1) and vertically extends upward to the same height as the back surface of the first chip (3); a first conductive material layer (41) is arranged on the surface of each first metal contact (31), and a second conductive material layer (42) is arranged on the upper surface of each vertical metal column (11); the first conductive material layer (41) and the second conductive material layer (42) are conductively connected through a transverse metal block (5).

2. The package structure of claim 1, wherein The vertical metal column (11) is a metal column made of a highly conductive metal, and the transverse metal block (5) is a metal block made of a highly conductive metal.

3. The package structure of claim 1, wherein The substrate (1) is provided with a chip mounting area (110) and a back surface power supply area (120) arranged on both sides of the chip mounting area (110), a plurality of first solder balls (6) are protrudingly arranged on the upper surface of the chip mounting area (110), the vertical metal columns (11) are formed on the back surface power supply area (120), and a plurality of first solder joints (21) corresponding to the first solder balls (6) are arranged on the lower surface of the adapter plate (2); each side back surface power supply area (120) is provided with a plurality of vertical metal columns (11).

4. The package structure of claim 3, wherein, The first solder joint (21) is protrudingly arranged on the lower surface of the adapter plate (2), and the vertical metal column (11) is protrudingly arranged on the back surface power supply area (120).

5. The package structure of claim 3, wherein The front surface of the first chip (3) is provided with a plurality of second metal contacts (32), and the upper surface of the adapter plate (2) is provided with second solder joints (22) embedded into the top and connected with the second metal contacts (32).

6. The package structure of any one of claims 1-5, wherein A filling glue layer (7) is arranged in the gap between the lower surface of the adapter plate (2) and the upper surface of the substrate (1) to fill the gap.

7. The package structure of claim 1, wherein The upper surface of the substrate (1) is provided with a plastic sealing layer (8) for encapsulating all components into one body.

8. The package structure of claim 1, wherein The first conductive material layer (41) and the second conductive material layer (42) are tin paste layers or conductive glue layers.

9. The package structure of claim 1, wherein The substrate (1) is an FCBGA packaging substrate. The substrate (1) is an FCBGA packaging substrate.

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