Overcurrent protection circuit and electrical equipment

Abstract

The utility model discloses an over-current protection circuit and electrical equipment, which can be used in the field of over-current protection, and the over-current protection circuit comprises a detection resistor, a threshold setting circuit, an over-current comparison circuit, an upper tube over-current detection circuit and a pre-driving circuit, the current output end of the full-bridge driving circuit is connected with the first end of the detection resistor; the first end of the detection resistor is connected with the first input end of the overcurrent comparison circuit; the threshold setting circuit is connected with the second input end of the overcurrent comparison circuit; the input end of the upper tube overcurrent detection circuit is connected with the grid electrode of an upper bridge arm switching device in the full-bridge driving circuit and the output end of the full-bridge driving circuit; the output end of the over-current comparison circuit and the output end of the upper tube over-current detection circuit are connected with the input end of the pre-driving circuit; the output end of the pre-driving circuit is connected with the grid electrode of the switching device in the full-bridge driving circuit. Therefore, the over-current protection circuit performs over-current detection on the upper bridge arm and the lower bridge arm of the full-bridge driving circuit, and over-current protection reliability is high.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of overcurrent protection, particularly to an overcurrent protection circuit and electrical equipment. BACKGROUND

[0002] In the field of motor driving, a full-bridge driving circuit is usually used to drive a motor. However, during the operation of the motor, if the motor current is too large, i.e., overcurrent occurs, the coil set and power devices inside the motor may be burned out, causing property loss.

[0003] The full-bridge driving circuit usually consists of four switching devices, which are divided into an upper bridge arm and a lower bridge arm. Currently, the current flowing through the switching device of the lower bridge arm of the full-bridge driving circuit is detected to determine whether overcurrent occurs, and then the switching device is turned off to achieve overcurrent protection of the motor. However, detecting the overcurrent state of the switching device of the lower bridge arm cannot cover all possible fault points in the full-bridge driving circuit, and the reliability is low. Even if overcurrent protection is performed by such a method, there is still a high failure rate, and the maintenance frequency and repair cost of the equipment are high.

[0004] Therefore, how to improve the reliability of the overcurrent protection circuit of the full-bridge driving circuit has become a problem to be solved. SUMMARY

[0005] Based on the above problems, the utility model provides an overcurrent protection circuit and electrical equipment, which provides an overcurrent protection circuit with high reliability for a full-bridge driving circuit.

[0006] The utility model embodiment discloses the following technical scheme:

[0007] In a first aspect, the utility model provides an overcurrent protection circuit applied to a full-bridge driving circuit, which comprises a detection resistor, a threshold setting circuit, an overcurrent comparison circuit, an upper tube overcurrent detection circuit, and a pre-driving circuit.

[0008] The current output end of the full-bridge driving circuit is connected to the first end of the detection resistor.

[0009] The first end of the detection resistor is connected to the first input end of the overcurrent comparison circuit, and the second end of the detection resistor is grounded.

[0010] The threshold setting circuit is connected to the second input end of the overcurrent comparison circuit.

[0011] The input end of the upper tube overcurrent detection circuit is connected to the gate of the switching device of the upper bridge arm in the full-bridge driving circuit and the output end of the full-bridge driving circuit.

[0012] An output terminal of the overcurrent comparison circuit and an output terminal of the upper tube overcurrent detection circuit are connected to an input terminal of the pre-driver circuit.

[0013] An output terminal of the pre-driver circuit is connected to a gate of a switching device in the full-bridge driving circuit, for controlling the switching device in the full-bridge driving circuit to make the full-bridge driving circuit turn off in a case that a first signal or a second signal representing an overcurrent state is acquired, wherein the first signal and the second signal are high-level or low-level signals with consistent level states.

[0014] Optionally, the threshold setting circuit comprises a first resistor and a second resistor.

[0015] A first end of the first resistor is connected to a reference voltage, a second end of the first resistor is connected to a first end of the second resistor, and a second end of the second resistor is grounded.

[0016] The second end of the first resistor is connected to a second input terminal of the overcurrent comparison circuit.

[0017] Optionally, the upper tube overcurrent detection circuit comprises a first detection circuit and a second detection circuit with the same structure.

[0018] The upper bridge arm switching device in the full-bridge driving circuit comprises a first MOS tube and a second MOS tube.

[0019] A gate of the first MOS tube is connected to a gate of a first mirror switch tube in the first detection circuit, and a drain of the first MOS tube is connected to a drain of the first mirror switch tube; the first mirror switch tube is a mirror tube of the first MOS tube.

[0020] A gate of the second MOS tube is connected to a gate of a second mirror switch tube in the second detection circuit, and a drain of the second MOS tube is connected to a drain of the second mirror switch tube; the second mirror switch tube is a mirror tube of the second MOS tube.

[0021] Optionally, the first detection circuit comprises a first mirror switch tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a voltage stabilizing diode, and a buffer.

[0022] A first end of the third resistor and a first end of the fourth resistor are connected to a high-voltage power supply, a second end of the third resistor is connected to a source of the fifth MOS tube, and a second end of the fourth resistor is connected to a source of the sixth MOS tube and a source of the first mirror switch tube.

[0023] The gate of the fifth MOS tube is connected with the gate of the sixth MOS tube and the drain of the fifth MOS tube; the drain of the fifth MOS tube is connected with the anode of the voltage stabilizing diode and the first end of the fifth resistor; the cathode of the voltage stabilizing diode is connected with high-voltage power supply;

[0024] The drain of the sixth MOS tube is connected with the anode of the voltage stabilizing diode, the first end of the seventh resistor, the gate of the ninth MOS tube and the first end of the sixth resistor; the cathode of the voltage stabilizing diode is connected with high-voltage power supply; the second end of the seventh resistor is connected with the source of the ninth MOS tube, and the second end of the seventh resistor and the source of the ninth MOS tube are connected with high-voltage power supply;

[0025] The second end of the fifth resistor is connected with the source of the fourteenth MOS tube; the second end of the sixth resistor is connected with the source of the fifteenth MOS tube; the gate of the fourteenth MOS tube and the gate of the fifteenth MOS tube are connected with a first bias voltage;

[0026] The drain of the fourteenth MOS tube is connected with the source of the seventh MOS tube; the drain of the fifteenth MOS tube is connected with the source of the eighth MOS tube; the gate of the seventh MOS tube and the gate of the eighth MOS tube are connected with a second bias voltage;

[0027] The drain of the ninth MOS tube is connected with the first end of the eighth resistor; the second end of the eighth resistor is connected with the source of the tenth MOS tube; the drain of the tenth MOS tube is connected with the source of the eleventh MOS tube and the gate of the twelfth MOS tube; the gate of the tenth MOS tube is connected with high-level TIE_H; the gate of the eleventh MOS tube is connected with the second bias voltage;

[0028] The source of the twelfth MOS tube is connected with the drain of the thirteenth MOS tube and the input end of the buffer; the output end of the buffer is the output end of the upper tube overcurrent detection circuit;

[0029] The gate of the thirteenth MOS tube is connected with a third bias voltage, and the source of the thirteenth MOS tube is connected with low-voltage power supply;

[0030] The drain of the seventh MOS tube, the drain of the eighth MOS tube, the drain of the eleventh MOS tube and the drain of the twelfth MOS tube are grounded.

[0031] Optionally, the fifth MOS transistor, the sixth MOS transistor, the ninth MOS transistor and the thirteenth MOS transistor are P-type MOS transistors; and the seventh MOS transistor, the eighth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the fourteenth MOS transistor and the fifteenth MOS transistor are N-type MOS transistors.

[0032] Optionally, the first detection circuit further comprises an overcurrent signal NAND gate.

[0033] The input end of the overcurrent signal NAND gate is connected to the output end of the buffer; and the output end of the overcurrent signal NAND gate is the output end of the upper tube overcurrent detection circuit.

[0034] Optionally, the overcurrent comparison circuit comprises an overcurrent signal NAND gate and a comparator.

[0035] The first input end of the comparator is the first input end of the overcurrent comparison circuit; the second input end of the comparator is the second input end of the overcurrent comparison circuit; the output end of the comparator is connected to the input end of the overcurrent signal NAND gate; and the output end of the overcurrent signal NAND gate is the output end of the overcurrent comparison circuit.

[0036] Optionally, the circuit further comprises a delay circuit; the output end of the overcurrent comparison circuit and the output end of the upper tube overcurrent detection circuit are connected to the input end of the pre-driver circuit, comprising:

[0037] The output end of the overcurrent comparison circuit is connected to the first input end of the delay circuit; and the output end of the upper tube overcurrent detection circuit is connected to the second input end of the delay circuit.

[0038] The output end of the delay circuit is connected to the input end of the pre-driver circuit.

[0039] Optionally, the delay circuit comprises an OR gate, an AND gate, a first NAND gate, a second NAND gate, a third NAND gate, a timer group and an SR latch.

[0040] The timer group comprises a plurality of timers; and the plurality of timers are connected in a manner that the Q end of a previous timer is connected to the D end of a subsequent timer.

[0041] The input end of the OR gate is the input end of the delay circuit.

[0042] The input end of the AND gate is connected to the output end of the OR gate and a reset signal; and the output end of the AND gate is connected to the input end of the first NAND gate.

[0043] The output end of the first NAND gate is connected to the input end of the timer group.

[0044] The output end of the timer group is connected to the S end of the SR latch;

[0045] The R end of the SR latch is connected to the output end of the second NOT gate, and the input end of the second NOT gate is connected to the reset signal;

[0046] The Q end of the SR latch is connected to the input end of the third NOT gate, and the output end of the third NOT gate is the output end of the delay circuit.

[0047] In a second aspect, the utility model provides an electrical equipment, the equipment includes full bridge drive circuit and the overcurrent protection circuit of any embodiment in the first aspect.

[0048] Compared with the prior art, the utility model has the following beneficial effects:

[0049] The utility model provides a kind of overcurrent protection circuit, and the circuit includes: detection resistance, threshold setting circuit, overcurrent comparison circuit, upper tube overcurrent detection circuit and pre-driver circuit;The current output end of full bridge drive circuit is connected the first end of detection resistance;The first end of detection resistance is connected the first input end of overcurrent comparison circuit;The second end of detection resistance is grounded;Threshold setting circuit connects the second input end of overcurrent comparison circuit;The input end of upper tube overcurrent detection circuit is connected the gate of upper bridge arm switching device in full bridge drive circuit and the output end of full bridge drive circuit;The output end of overcurrent comparison circuit and the output end of upper tube overcurrent detection circuit are connected the input end of pre-driver circuit;The output end of pre-driver circuit is connected the gate of switching device in full bridge drive circuit, for obtaining the first signal or second signal under the condition of characterizing overcurrent state, control switching device in the full bridge drive circuit, make the full bridge drive circuit cut off;Wherein, the first signal and second signal are high level or low level signal of level state consistency.Overcurrent protection circuit is detected to upper bridge arm and lower bridge arm of full bridge drive circuit by this, covers all possible fault points in full bridge drive circuit, when overcurrent phenomenon appears in any switching tube in full bridge drive circuit, full bridge drive circuit is cut off, to enter current decay stage, and the reliability of overcurrent protection is higher. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical scheme in the utility model embodiment or prior art, the following will briefly introduce the drawings needed to be used in embodiment or prior art description, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can be obtained according to these drawings without paying creative labor.

[0051] Figure 1 A kind of overcurrent protection circuit schematic diagram provided for the utility model embodiment.

[0052] Figure 2 A current flow direction schematic view in a full-bridge driving circuit provided for the embodiment of the utility model;

[0053] Figure 3 A first detection circuit schematic view provided for the embodiment of the utility model;

[0054] Figure 4 Another overcurrent protection circuit schematic view provided for the embodiment of the utility model;

[0055] Figure 5 A delay circuit schematic view provided for the embodiment of the utility model;

[0056] Figure 6 A delay circuit signal timing diagram under the condition of no overcurrent event provided for the embodiment of the utility model;

[0057] Figure 7 A delay circuit signal timing diagram under the condition of overcurrent event provided for the embodiment of the utility model;

[0058] Figure 8 A delay circuit signal timing diagram under the condition of reset overcurrent event provided for the embodiment of the utility model. DETAILED DESCRIPTION

[0059] As described above, in the process of normal operation of the motor, the motor current is less than the rated current, and the motor current is proportional to the torque; and in the case that the motor current exceeds the rated current, the motor internal core magnetic saturation may be caused, and the inductance winding is equivalent to a wire, at this time, the power supply is short-circuited, and the current flowing through the winding sharply increases. In the working state of such overcurrent for a long time, the inductance winding and the chip in the motor may be burned, causing property loss, and even endangering the life safety of the user.

[0060] Therefore, detecting the working state of the motor to limit the maximum value of the current is the key to guarantee the safety of the electrical equipment. At present, for the motor driven by the full-bridge driving circuit, the overcurrent condition of the motor is usually judged by detecting the current flowing through the lower bridge arm switch device of the full-bridge driving circuit, so as to turn off the switch device when the overcurrent condition occurs, and realize the overcurrent protection of the motor. However, only detecting the overcurrent state of the lower bridge arm switch cannot cover all possible fault points in the full-bridge driving circuit, and the reliability is low.

[0061] Therefore, the utility model provides an overcurrent protection circuit, which comprises a detection resistor, a threshold setting circuit, an overcurrent comparison circuit, an upper tube overcurrent detection circuit and a pre-driving circuit, the upper bridge arm and the lower bridge arm of the full-bridge driving circuit are detected, and the reliability of overcurrent protection is high.

[0062] The terms "first", "second", "third", and "fourth" and the like in the description and in the claims of the utility model and the drawings are used to distinguish different objects, rather than to limit a specific order.

[0063] In the embodiments of the utility model, the words such as "as an example" or "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "as an example" or "for example" in the embodiments of the utility model should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. In fact, the words such as "as an example" or "for example" are intended to present the relevant concept in a specific way.

[0064] The terms used in part of the embodiments of the utility model are only used to explain the specific embodiments of the utility model, and are not intended to limit the utility model.

[0065] In order to enable the personnel in the technical field to better understand the utility model scheme, the technical scheme in the embodiments of the utility model will be clearly and completely described below in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all. Based on the embodiments in the utility model, all other embodiments obtained by the ordinary skilled in the art without creative labor belong to the scope of protection of the utility model.

[0066] Referring to Figure 1 The figure is a kind of overcurrent protection circuit schematic diagram provided by the embodiments of the utility model, and the overcurrent protection circuit is applied to full-bridge drive circuit 110, including: detection resistance 120, threshold setting circuit 130, overcurrent comparison circuit 140, upper tube overcurrent detection circuit 150 and pre-driver circuit 160.

[0067] The current output end of full-bridge drive circuit 110 is connected with the first end of detection resistance 120.

[0068] Specifically, full-bridge drive circuit 110 includes two upper bridge arm switching devices and two lower bridge arm switching devices, and in the embodiments of the utility model, the upper bridge arm switching device is first MOS tube M1 and second MOS tube M2, and the lower bridge arm switching device is third MOS tube M3 and fourth MOS tube M4. Wherein, the source of M1 and M2 is connected with high-voltage power supply VBB;The drain of M3 and M4 is connected, as the current output end of full-bridge drive circuit 110;The drain of M1 is connected with the source of M4 and first output end OUT1;The drain of M2 is connected with the source of M3 and second output end OUT2. Load, such as motor, is connected between OUT1 and OUT2.

[0069] Referring to Figure 2The figure is a current flow direction schematic diagram of a full-bridge driving circuit provided by an embodiment of the utility model. Among them, D1 is the parasitic diode of M1, D2 is the parasitic diode of M2, D3 is the parasitic diode of M3, and D4 is the parasitic diode of M4.

[0070] When the motor needs to be driven forward, M1 and M3 can be controlled to be turned on by the pre-driving circuit 160, M2 and M4 are turned off, the current flow direction is from M1 to the motor and then to M3, and finally flows to the detection resistor 120; when the motor needs to be driven in reverse, M2 and M4 can be controlled to be turned on by the pre-driving circuit 160, M1 and M3 are turned off, the current flow direction is from M2 to the motor and then to M4, and finally flows to the detection resistor 120; when the motor needs to pass no current, M3 and M4 can be controlled to be turned on by the pre-driving circuit 160, M1 and M2 are turned off; or when the motor needs to pass no current, M1, M2, M3 and M4 can be controlled to be turned off by the pre-driving circuit 160.

[0071] Optionally, in another embodiment provided by the utility model, the switching device in the full-bridge driving circuit 110 can also be an IGBT device.

[0072] The first end of the detection resistor 120 is connected to the first input end of the overcurrent comparison circuit 140; the second end of the detection resistor 120 is grounded; and the threshold setting circuit 130 is connected to the second input end of the overcurrent comparison circuit 140. Among them, the overcurrent comparison circuit 140 can be a comparator, and the first input end of the overcurrent comparison circuit 140 can be a negative input end or a positive input end of the comparator; correspondingly, the second input end can be a positive input end or a negative input end of the comparator.

[0073] As an example, the threshold setting circuit 130 includes a first resistor R1 and a second resistor R2, wherein the first end of R1 is connected to a reference voltage V REF , the second end of R1 is connected to the first end of R2; the second end of R2 is grounded; and the second end of R1 is connected to the second input end of the overcurrent comparison circuit 140.

[0074] Optionally, the first resistor R1 can be an access circuit part of an adjustable resistor such as a slide rheostat that changes the resistance value by changing the access length, and the second resistor R2 can be a part of the adjustable resistor that is not connected to the circuit. Therefore, by using an adjustable resistor as the threshold setting circuit 130, the resistance values of the first resistor R1 and the second resistor R2 can be adjusted based on actual needs, so that the overcurrent threshold can be flexibly set.

[0075] Specifically, in one embodiment, the overcurrent comparison circuit 140 is a comparator, the first input end of the overcurrent comparison circuit 140 is a negative input end of the comparator, and the second input end of the overcurrent comparison circuit 140 is a positive input end of the comparator; the current ISENSE The voltage signal across the detection resistor R SENSE 120, R SENSE The voltage V SENSE = I SENSE *R SENSE is input to the negative input terminal of the comparator; the voltage V INP = V REF *R1 / (R1+R2) is input to the positive input terminal of the comparator; if V SENSE is greater than V INP , the overcurrent comparison circuit 140 outputs a low level, indicating that the overcurrent phenomenon occurs at the detection resistor end; if V SENSE is less than V INP , the overcurrent comparison circuit 140 outputs a high level, indicating that the overcurrent phenomenon does not occur at the detection resistor end.

[0076] In one embodiment, the overcurrent comparison circuit 140 is a comparator, the first input terminal of the overcurrent comparison circuit 140 is the positive input terminal of the comparator, and the second input terminal of the overcurrent comparison circuit 140 is the negative input terminal of the comparator; the current I SENSE flows through the detection resistor R SENSE 120, R SENSE The voltage V SENSE = I SENSE *R SENSE is input to the positive input terminal of the comparator; the voltage V INP = V REF *R1 / (R1+R2) is input to the negative input terminal of the comparator; if V SENSE is greater than V INP , the overcurrent comparison circuit 140 outputs a high level, indicating that the overcurrent phenomenon occurs at the detection resistor end; if V SENSE is less than V INP , the overcurrent comparison circuit 140 outputs a low level, indicating that the overcurrent phenomenon does not occur at the detection resistor end.

[0077] The input terminal of the upper overcurrent detection circuit 150 is connected to the gate GH1 and GH2 of the upper bridge arm switching device in the full-bridge drive circuit 110 and the output terminal OUT1 and OUT2 of the full-bridge drive circuit 110.

[0078] As an example, the upper overcurrent detection circuit 150 can include a first detection circuit and a second detection circuit which are structurally identical, wherein the gate GH1 of M1 is connected to the gate of a first mirror switch tube in the first detection circuit, and the drain OUT1 of M1 is connected to the drain of the first mirror switch tube; the gate GH2 of M2 is connected to the gate of a second mirror switch tube in the second detection circuit, and the drain OUT2 of M2 is connected to the drain of the second mirror switch tube. Wherein the first mirror switch tube is a mirror tube of the first MOS tube, and the second mirror switch tube is a mirror tube of the second MOS tube.

[0079] Referring to Figure 3 , the figure is the first detection circuit schematic diagram provided by the embodiment of the utility model, first detection circuit includes: first mirror switch tube M1_Mirror, fifth MOS tube M5, sixth MOS tube M6, seventh MOS tube M7, eighth MOS tube M8, ninth MOS tube M9, tenth MOS tube M10, eleventh MOS tube M11, twelfth MOS tube M12, thirteenth MOS tube M13, fourteenth MOS tube M14, fifteenth MOS tube M15, third resistance R3, fourth resistance R4, fifth resistance R5, sixth resistance R6, seventh resistance R7, eighth resistance R8, voltage stabilizing diode ZENER, buffer BUF.

[0080] The first end of R3 and the first end of R4 are connected with high voltage power supply;The second end of R3 is connected with the source electrode of M5;The second end of R4 is connected with the source electrode of M6 and the source electrode of M1_Mirror;The gate electrode of M5 is connected with the gate electrode of M6 and the drain electrode of M5;The drain electrode of M5 is connected with the anode of ZENER and the first end of R5;The cathode of ZENER is connected with high voltage power supply VBB;The drain electrode of M6 is connected with the anode of ZENER, the first end of R7, the gate electrode of M9 and the first end of R6;The cathode of ZENER is connected with high voltage power supply VBB;The second end of R7 is connected with the source electrode of M9, and the second end of R7 and the source electrode of M9 are connected with high voltage power supply VBB;The second end of R5 is connected with the source electrode of M14;The second end of R6 is connected with the source electrode of M15;The gate electrode of M14 and the gate electrode of M15 are connected with first bias voltage BIASN1;The drain electrode of M14 is connected with the source electrode of M7;The drain electrode of M15 is connected with the source electrode of M8;The gate electrode of M7 and the gate electrode of M8 are connected with second bias voltage BIASN2;The drain electrode of M9 is connected with the first end of R8;The second end of R8 is connected with the source electrode of M10;The drain electrode of M10 is connected with the source electrode of M11 and the gate electrode of M12;The gate electrode of M10 is connected with high level TIE_H;The gate electrode of M11 is connected with second bias voltage BIASN2;The source electrode of M12 is connected with the drain electrode of M13 and the input end of BUF;The output end of BUF is the output end of upper tube overcurrent detection circuit;The gate electrode of M13 is connected with third bias voltage BIASN3, and the source electrode of M13 is connected with low voltage power supply VDD;The drain electrode of M7, the drain electrode of M8, the drain electrode of M11 and the drain electrode of M12 are grounded.

[0081] As an example, the high-voltage power supply VBB can be 50V; the low-voltage power supply VDD can be 3.3V or 5.0V, etc. The gate of M10 is connected to the high-level TIE_H, and TIE_H can default to the VDD voltage; M5, M6, M9, M10, M14 and M15 are all high-voltage tubes; BIASN1, BIASN2 and BIASN3 are bias voltages; the clamping diode of ZENER is reversed to protect the gate-source voltage of M5 and M9 from being less than 6V, preventing excessive gate-source voltage from causing damage to the MOS tube or performance degradation.

[0082] Exemplarily, M5, M6, M9 and M13 are P-type MOS transistors, and M7, M8, M10, M11, M12, M14 and M15 are N-type MOS transistors.

[0083] The size ratio (W / L) of M1_Mirror and M1 is recorded as K:1, and the saturation region equation of the MOS tube is: Where, I is the drain current; μ n is the conductive carrier mobility; C ox is the gate oxide capacitance; W / L is the width-to-depth ratio; V GS is the gate-source voltage; V THN is the threshold voltage of the N-type MOS tube.

[0084] Since M1_Mirror and M1's V THN and V GS Equal, so the current flowing through M1_Mirror I4=K*I M1 , the voltage drop of current I4 on R4 is K*I M1 *R4. The current flowing through R3 is recorded as I1, when (I1+K*I M1 )*R4 is greater than I1*R3, indicating that the upper tube has an overcurrent phenomenon, the source voltage of M6 rises, causing M6 to enter the linear region, and the drain voltage Vp voltage will increase. When it rises to VBB-Vp which is less than the threshold voltage Vth_M9 of M9, M9 will be cut off, and the gate voltage V N is pulled to the reference point GND and cut off, the source voltage of M12 V N1 Pull up to VDD-V ov_M13 , where V ov_M13 The overdrive voltage of M13 is outputted high by buffer BUF, indicating an overcurrent event on the upper tube. Optionally, the upper tube overcurrent threshold can be set by configuring the K value and the ratio of R3 to R4.

[0085] As an example, in the case that the overcurrent comparison circuit 140 is a comparator, the first input end of the overcurrent comparison circuit 140 is the negative phase input end of the comparator, and the second input end of the overcurrent comparison circuit 140 is the positive input end of the comparator, the first detection circuit can further include a first signal NOT gate; the input end of the first signal NOT gate is connected to the output end of the buffer BUF; and the output end of the first signal NOT gate is the output end of the upper tube overcurrent detection circuit 150. At this time, the overcurrent comparison circuit 140 outputs a low level, indicating that the overcurrent phenomenon occurs at the detection resistance end; the first detection circuit outputs a low level, indicating that the overcurrent event occurs at the upper tube M1; and the second detection circuit with the same structure as the first detection circuit outputs a low level, indicating that the overcurrent event occurs at the upper tube M2.

[0086] The output end of the overcurrent comparison circuit 140 and the output end of the upper tube overcurrent detection circuit 150 are connected to the input end of the pre-driver circuit 160.

[0087] The output end of the pre-driver circuit 160 is connected to the gate GH1, GH2, GH3 and GH4 of the switching device in the full-bridge driving circuit 110, so as to control the switching device in the full-bridge driving circuit 110 to make the full-bridge driving circuit 110 be turned off in the case that the first signal or the second signal representing the overcurrent state is obtained, so as to achieve the effect of protecting the full-bridge driving circuit and the motor. The first signal can be a high level or a low level, and the second signal can also be a high level or a low level, and the first signal and the second signal are level signals with the same level state. The first signal is the signal output from the output end of the upper tube overcurrent detection circuit 150, and the second signal is the signal output from the output end of the overcurrent comparison circuit 140.

[0088] Therefore, the overcurrent protection circuit provided in the embodiment of the present application performs overcurrent detection on the upper bridge arm and the lower bridge arm of the full-bridge driving circuit, covers all possible fault points in the full-bridge driving circuit, and turns off the full-bridge driving circuit when overcurrent phenomenon occurs in any switching tube in the full-bridge driving circuit, so as to enter the current decay stage, and the reliability of overcurrent protection is higher.

[0089] Referring to Figure 4 The figure is another overcurrent protection circuit schematic diagram provided by the embodiment of the present application, which is applied to the full-bridge driving circuit 110 and includes a detection resistance 120, a threshold setting circuit 130, an overcurrent comparison circuit 140, an upper tube overcurrent detection circuit 150, a pre-driver circuit 160 and a delay circuit 170.

[0090] The overcurrent comparison circuit 140 comprises a comparator 141 and a second signal NOT gate 142. The first input end of the comparator 141 is the first input end of the overcurrent comparison circuit 140; the second input end of the comparator 141 is the second input end of the overcurrent comparison circuit 140; the output end of the comparator 141 is connected to the input end of the second signal NOT gate 142; and the output end of the second signal NOT gate 142 is the output end of the overcurrent comparison circuit 140.

[0091] As an example, the output end of the overcurrent comparison circuit 140 is connected to the first input end of the delay circuit 170; the output end of the upper tube overcurrent detection circuit 150 is connected to the second input end of the delay circuit 170; and the output end of the delay circuit 170 is connected to the input end of the pre-driver circuit 160.

[0092] The delay time length of the delay circuit 170 can be set, for example, the delay time length of 2 microseconds can be set, and in the case that the first signal or the second signal lasts for more than 2 microseconds, the delay circuit 170 confirms that the overcurrent event occurs, and controls the pre-driver circuit 160 to turn off the full-bridge drive circuit 110.

[0093] As an example, in the case that the overcurrent comparison circuit 140 comprises the comparator 141 and the second signal NOT gate 142, if the first input end of the overcurrent comparison circuit 140 is the negative phase input end of the comparator 141, and the second input end of the overcurrent comparison circuit 140 is the positive phase input end of the comparator 141, the first signal NOT gate is not included in the upper tube overcurrent detection circuit 150. At this time, in the case that the overcurrent comparison circuit 140 outputs a high level, it indicates that the overcurrent phenomenon occurs at the detection resistor end; and in the case that the upper tube overcurrent detection circuit 150 outputs a high level, it indicates that the overcurrent event occurs at the upper tube.

[0094] As another example, in the case that the overcurrent comparison circuit 140 comprises the comparator 141 and the second signal NOT gate 142, if the first input end of the overcurrent comparison circuit 140 is the positive phase input end of the comparator 141, and the second input end of the overcurrent comparison circuit 140 is the negative phase input end of the comparator 141, the first signal NOT gate is included in the upper tube overcurrent detection circuit 150. At this time, in the case that the overcurrent comparison circuit 140 outputs a low level, it indicates that the overcurrent phenomenon occurs at the detection resistor end; and in the case that the upper tube overcurrent detection circuit 150 outputs a low level, it indicates that the overcurrent event occurs at the upper tube.

[0095] Referring to Figure 5 The delay circuit 170 can comprise an OR gate 71, an AND gate 72, a first NOT gate 73, a second NOT gate 74, a third NOT gate 75, a timer group 76, and an SR latch 77.

[0096] The timer group 76 comprises a plurality of timers, and the plurality of timers are connected in a manner that the Q terminal of a previous timer is connected to the D terminal of a subsequent timer. The input terminal of the OR gate 71 is the input terminal of the delay circuit 170, and the output terminal of the third NOT gate 75 is the output terminal of the delay circuit 170.

[0097] The input terminal of the AND gate 72 is connected to the output terminal of the OR gate 71 and the reset signal RESET_IN, and the output terminal of the AND gate 72 is connected to the input terminal of the first NOT gate 73. The output terminal of the first NOT gate 73 is connected to the input terminal of the timer group 76, and the output terminal of the timer group 76 is connected to the S terminal of the SR latch 77. The R terminal of the SR latch 77 is connected to the output terminal of the second NOT gate 74, and the input terminal of the second NOT gate 74 is connected to the reset signal RESET_IN. The Q terminal of the SR latch 77 is connected to the input terminal of the third NOT gate 75.

[0098] The OR gate 71 can be composed of three sub-OR gates. The first input terminal of the first sub-OR gate is connected to the output terminal OCP_M1 of the first detection circuit, and the second input terminal of the first sub-OR gate can be connected to the first input terminal of the second sub-OR gate, both of which receive the output signal OCP_SENSE of the comparator signal NOT gate 180. The second input terminal of the second sub-OR gate is connected to the output terminal OCP_M2 of the second detection circuit. The output terminal of the first sub-OR gate is connected to the first input terminal of the third sub-OR gate, and the output terminal of the second sub-OR gate is connected to the second input terminal of the third sub-OR gate. The input terminals of the first sub-OR gate and the second sub-OR gate are the input terminals of the OR gate 71, and the output terminal of the third sub-OR gate is the output terminal of the OR gate 71.

[0099] Taking the case that the first signal or the second signal is high to indicate that an overcurrent event occurs as an example, in the initial state, the reset signal RESET_IN can be set to high. Thus, when any of OCP_M1, OCP_SENSE and OCP_M2 is high, the timer group 76 starts to work. Taking the case that the timer group 76 comprises five rising edge timers and one clock cycle is set to 500 nanoseconds as an example, the counting time is 4-5 clock cycles, that is, the overcurrent detection time is about 2-2.5 microseconds. From the moment when any overcurrent signal is pulled high, when the fifth rising edge appears, the S terminal of the SR latch 77 is pulled high, and the Q terminal outputs high. Finally, through the third NOT gate 75, the output signal OCP_EN of the delay circuit 170 is low, indicating that the overcurrent event actually occurs. That is, when the duration of the overcurrent event exceeds 2 microseconds, it is determined that the overcurrent event actually occurs. Thus, by judging whether the overcurrent signal reaches the predetermined duration, the overcurrent event can be avoided from being triggered by mistake, and the stability of the overcurrent protection circuit is improved.

[0100] Referring to Figure 6, the high level outputted by the OR gate 71 lasts before the fifth clock rising edge, and it can be considered that the overcurrent event has not really occurred, so the OCP_EN is not pulled low, and the RESET_IN has no effect on the high level OCP_EN signal.

[0101] Referring to Figure 7 , the high level outputted by the OR gate 71 lasts before the fifth clock rising edge, and it can be considered that the overcurrent event has not really occurred, so the OCP_EN is not pulled low, and the RESET_IN has no effect on the high level OCP_EN signal.

[0102] After the overcurrent event is triggered, the RESET_IN is pulled low and then pulled high, so that the OCP_EN signal is pulled high, the function of resetting the overcurrent event is realized, the full-bridge driving circuit returns to normal work, and the power supply does not need to be cut off for resetting, and the use convenience of the overcurrent protection circuit is enhanced.

[0103] Referring to Figure 8 , the high level outputted by the OR gate 71 lasts before the fifth clock rising edge, and it can be considered that the overcurrent event has not really occurred, so the OCP_EN is not pulled low, and the RESET_IN has no effect on the high level OCP_EN signal.

[0104] Optionally, the RESET_IN signal can pass through two continuous NOT gates before reaching the input end of the AND gate 72, and the two continuous NOT gates can play the role of a buffer, so that the delay circuit 170 is more stable.

[0105] In addition, the utility model also provides an electrical equipment, the electrical equipment includes full-bridge driving circuit and the overcurrent protection circuit provided by any one of the above embodiment.

[0106] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

[0107] The above description of disclosed embodiments enables one of ordinary skill in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An overcurrent protection circuit, characterized by comprising: The over-current protection circuit is applied to a full-bridge driving circuit, and comprises a detection resistor, a threshold setting circuit, an over-current comparison circuit, an upper tube over-current detection circuit and a pre-driving circuit. A current output end of the full-bridge driving circuit is connected to a first end of the detection resistor. A first input end of the over-current comparison circuit is connected to the first end of the detection resistor, and a second end of the detection resistor is grounded. The threshold setting circuit is connected to a second input end of the over-current comparison circuit. An input end of the upper tube over-current detection circuit is connected to a gate of an upper bridge arm switching device in the full-bridge driving circuit and an output end of the full-bridge driving circuit. An output end of the over-current comparison circuit and an output end of the upper tube over-current detection circuit are connected to an input end of the pre-driving circuit. An output end of the pre-driving circuit is connected to a gate of a switching device in the full-bridge driving circuit, and is used for controlling the switching device in the full-bridge driving circuit to make the full-bridge driving circuit turn off in a case that a first signal or a second signal representing an over-current state is acquired, wherein the first signal and the second signal are high-level or low-level signals with consistent level states.

2. The circuit of claim 1, wherein, The threshold setting circuit comprises a first resistor and a second resistor. A first end of the first resistor is connected to a reference voltage, a second end of the first resistor is connected to a first end of the second resistor, and a second end of the second resistor is grounded. The second end of the first resistor is connected to the second input end of the over-current comparison circuit.

3. The circuit of claim 1, wherein, The upper tube over-current detection circuit comprises a first detection circuit and a second detection circuit which have the same structure. The upper bridge arm switching device in the full-bridge driving circuit comprises a first MOS tube and a second MOS tube. A gate of the first MOS tube is connected to a gate of a first mirror switch tube in the first detection circuit, and a drain of the first MOS tube is connected to a drain of the first mirror switch tube. The first mirror switch tube is a mirror tube of the first MOS tube. A gate of the second MOS tube is connected to a gate of a second mirror switch tube in the second detection circuit, and a drain of the second MOS tube is connected to a drain of the second mirror switch tube. The second mirror switch tube is a mirror tube of the second MOS tube.

4. The circuit of claim 3, wherein, The first detection circuit comprises a first mirror switch tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a voltage stabilizing diode and a buffer. A first end of the third resistor and a first end of the fourth resistor are connected to a high-voltage power supply, a second end of the third resistor is connected to a source of the fifth MOS tube, and a second end of the fourth resistor is connected to a source of the sixth MOS tube and a source of the first mirror switch tube. The gate of the fifth MOS is connected with the gate of the sixth MOS and the drain of the fifth MOS; the drain of the fifth MOS is connected with the anode of the voltage stabilizing diode and the first end of the fifth resistor; the cathode of the voltage stabilizing diode is connected with high voltage power supply; The drain of the sixth MOS is connected with the anode of the voltage stabilizing diode, the first end of the seventh resistor, the gate of the ninth MOS and the first end of the sixth resistor; the cathode of the voltage stabilizing diode is connected with high voltage power supply; the second end of the seventh resistor is connected with the source of the ninth MOS, and the second end of the seventh resistor and the source of the ninth MOS are connected with high voltage power supply; The second end of the fifth resistor is connected with the source of the fourteenth MOS; the second end of the sixth resistor is connected with the source of the fifteenth MOS; the gate of the fourteenth MOS and the gate of the fifteenth MOS are connected with first bias voltage; The drain of the fourteenth MOS is connected with the source of the seventh MOS; the drain of the fifteenth MOS is connected with the source of the eighth MOS; the gate of the seventh MOS and the gate of the eighth MOS are connected with second bias voltage; The drain of the ninth MOS is connected with the first end of the eighth resistor; the second end of the eighth resistor is connected with the source of the tenth MOS; the drain of the tenth MOS is connected with the source of the eleventh MOS and the gate of the twelfth MOS; the gate of the tenth MOS is connected with high level TIE_H; the gate of the eleventh MOS is connected with second bias voltage; The source of the twelfth MOS is connected with the drain of the thirteenth MOS and the input of the buffer; the output of the buffer is the output of the upper tube overcurrent detection circuit; The gate of the thirteenth MOS is connected with third bias voltage, and the source of the thirteenth MOS is connected with low voltage power supply; The drain of the seventh MOS, the drain of the eighth MOS, the drain of the eleventh MOS and the drain of the twelfth MOS are grounded.

5. The circuit of claim 4, wherein, The fifth MOS, the sixth MOS, the ninth MOS and the thirteenth MOS are P-type MOS; the seventh MOS, the eighth MOS, the tenth MOS, the eleventh MOS, the twelfth MOS, the fourteenth MOS and the fifteenth MOS are N-type MOS.

6. The circuit of claim 4, wherein, The first detection circuit further comprises a first signal NOT gate; The input of the first signal NOT gate is connected with the output of the buffer; the output of the first signal NOT gate is the output of the upper tube overcurrent detection circuit.

7. The circuit of claim 1, wherein, The overcurrent comparison circuit comprises a second signal NOT gate and a comparator; The first input of the comparator is the first input of the overcurrent comparison circuit; the second input of the comparator is the second input of the overcurrent comparison circuit; the output of the comparator is connected with the input of the second signal NOT gate; the output of the second signal NOT gate is the output of the overcurrent comparison circuit.

8. The circuit according to any one of claims 1 to 7, characterized in that The circuit further comprises a delay circuit; The output end of the overcurrent comparison circuit and the output end of the upper tube overcurrent detection circuit are connected to the input end of the pre-driver circuit, comprising: The output end of the overcurrent comparison circuit is connected to the first input end of the delay circuit; the output end of the upper tube overcurrent detection circuit is connected to the second input end of the delay circuit; The output end of the delay circuit is connected to the input end of the pre-driver circuit.

9. The circuit of claim 8, wherein, The delay circuit comprises an OR gate, an AND gate, a first NOT gate, a second NOT gate, a third NOT gate, a timer group and an SR latch; The timer group comprises a plurality of timers; the connection mode of the plurality of timers is that the Q end of a previous timer is connected to the D end of a subsequent timer; The input end of the OR gate is the input end of the delay circuit; The input end of the AND gate is connected to the output end of the OR gate and a reset signal; the output end of the AND gate is connected to the input end of the first NOT gate; The output end of the first NOT gate is connected to the input end of the timer group; The output end of the timer group is connected to the S end of the SR latch; The R end of the SR latch is connected to the output end of the second NOT gate; the input end of the second NOT gate is connected to the reset signal; The Q end of the SR latch is connected to the input end of the third NOT gate; the output end of the third NOT gate is the output end of the delay circuit.

10. An electrical device, characterized by The device comprises a full-bridge driving circuit and the overcurrent protection circuit provided in any one of claims 1-9.

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