Gateway adaptive to various analog communication terminals

Abstract

The utility model relates to a gateway self-adaptive to various analog communication terminals, and relates to the field of gateways. In the self-adaptive gain amplifier, the output end of a programmable gain amplifier is connected with a peak value detection unit for detecting the peak value of an amplified signal, the output end of the peak value detection unit is connected with one input of a hysteresis comparator, and the other input of the hysteresis comparator is connected with a reference voltage source; the output of the hysteresis comparator is electrically connected with an adaptive gain amplifier controller, the adaptive gain amplifier controller is connected with an adjustable bias voltage source and a control pin of a programmable gain amplifier, and the output voltage of the adjustable bias voltage source acts on the input of the programmable gain amplifier; the output end of the programmable gain amplifier is connected with the analog-to-digital converter, and the analog-to-digital converter is electrically connected with the gateway processor. According to the invention, the method is adaptive to any analog signal communication terminal, and adaptive acquisition of analog signals meeting requirements is realized.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of gateway especially relates to a kind of gateway of self-adapting multiple analog communication terminal. BACKGROUND

[0002] With the development of Internet of Things technology, the terminals supported by the Internet of Things network are increasing, and the Internet of Things network for building management, monitoring and maintenance terminals cannot be supported by the gateway.

[0003] In many existing industrial application scenarios, many terminals will use different specifications of analog signals for data transmission, such as different signal levels of some analog signal sensors, resulting in obvious differences in peak values of analog signals. To adapt to the Internet of Things construction in this industrial scenario, multiple analog signal interfaces or gateways supporting different analog signal acquisition are often configured. This may lead to the complexity of the topology of the Internet of Things network and increase the deployment cost of the network. Therefore, a gateway that self-adapts to multiple analog communication terminals is needed to solve the above problems. SUMMARY

[0004] To solve the above technical problems or at least partially solve the above technical problems, the utility model provides a gateway that self-adapts to multiple analog communication terminals.

[0005] The utility model provides a gateway that self-adapts to multiple analog communication terminals, comprising: a gateway processor, the gateway processor is connected with a programmable analog signal acquisition circuit, the programmable analog signal acquisition circuit comprises: an analog signal acquisition circuit, an input end is connected to an adaptive gain amplifier of the analog signal acquisition circuit, an output end of the adaptive gain amplifier is connected with an analog-to-digital converter, and the analog-to-digital converter is electrically connected with the gateway processor.

[0006] Among them, the adaptive gain amplifier comprises: a programmable gain amplifier, the output end of the programmable gain amplifier is connected with a peak value detection unit, one input of the peak value detection unit is connected with the other input of a hysteresis comparator, the output of the hysteresis comparator is electrically connected with an adaptive gain amplifier controller, the adaptive gain amplifier controller is connected with an adjustable bias voltage source and the control pin of the programmable gain amplifier, and the output voltage of the adjustable bias voltage source acts on the input of the programmable gain amplifier;The output end of the programmable gain amplifier is connected with the analog-to-digital converter, and the analog-to-digital converter is electrically connected with the gateway processor.

[0007] Further, the analog signal acquisition circuit comprises: an analog signal differential H input line and an analog signal differential L input line; the analog signal differential H input line and the analog signal differential L input line are respectively connected with anti-interference resistors in series, the analog signal differential H input line and the analog signal differential L input line are respectively connected with filter capacitors grounded, the analog signal differential H input line and the analog signal differential L input line are respectively connected with positive and negative clamping diodes, a filter capacitor is arranged between the analog signal differential H input line and the analog signal differential L input line, the analog signal differential H input line is connected with an upper pull power supply through a resistor, and the analog signal differential H input line is grounded through a resistor.

[0008] Further, the peak detection unit comprises: an operational amplifier U4A, a non-inverting input end of the operational amplifier U4A is connected to an output end of the programmable gain amplifier, an output end of the operational amplifier U4A is connected with a sampling capacitor C4 grounded through a diode D6, and a diode D5 is coupled between the output end and an inverting input end of the operational amplifier U4A; the sampling capacitor C4 is connected in parallel with a reset switch S1, a non-grounded plate of the sampling capacitor C4 is connected to a non-inverting input end of an operational amplifier U4B, an output end of the operational amplifier U4B is fed back to an inverting input end, and the output end of the operational amplifier U4B is coupled to the output end of the operational amplifier U4A through a resistor R14.

[0009] Further, the gateway processor is connected with a digital signal acquisition circuit; the digital signal acquisition circuit comprises: a plurality of optocouplers, a transmitting end of each optocoupler is connected with a digital input interface, wherein the transmitting end of the optocoupler is connected with a digital input; a collector of a receiving end of each optocoupler is connected with a 3.3V voltage, and an emitter is grounded through a resistor; the gateway processor is connected with an emitter of the receiving end of each optocoupler through a digital input IO interface.

[0010] Further, the gateway processor is connected with a digital signal output circuit; each of the digital signal output circuits comprises: a voltage division circuit composed of two series resistors connected with a digital output IO interface of the gateway processor, a coupling resistor connected between the two resistors of the voltage division circuit, a coupling resistor connected to a base of a first-stage transistor in a Darlington transistor, a coupling resistor between a base and an emitter of a second-stage transistor in the Darlington transistor, a common end connected to an output power supply positive pole through a clamping diode connected to a collector of the second-stage transistor, and a collector of the second-stage transistor connected with a digital signal relay.

[0011] Further, the gateway processor is connected with any one or a combination of several of 4G wireless communication circuit, WiFi communication circuit, RS232 communication circuit, RS485 communication circuit and Ethernet communication circuit.

[0012] Further, the gateway processor is connected with the adaptive gain amplifier controller.

[0013] Further, the power module for supplying power includes: a power adapter for converting 220V AC power into 12V DC power; and a DC-DC voltage stabilizing unit for converting the 12V DC power into 5V, 3.8V and 3.3V DC power.

[0014] Compared with the prior art, the above technical solution provided by the embodiment of the utility model has the following advantages:

[0015] The programmable analog signal acquisition circuit is used for collecting analog signals, and the programmable analog signal acquisition circuit comprises an adaptive gain amplifier; in the adaptive gain amplifier, an output end of the programmable gain amplifier is connected to a peak value detection unit for detecting a peak value of an amplified signal, an output end of the peak value detection unit is connected to one input of a hysteresis comparator, another input of the hysteresis comparator is connected to a reference voltage source, an output of the hysteresis comparator is connected to an adaptive gain amplifier controller, the adaptive gain amplifier controller is connected to an adjustable bias voltage source and a control pin of the programmable gain amplifier, and an output voltage of the adjustable bias voltage source acts on an input of the programmable gain amplifier; an output end of the programmable gain amplifier is connected to an analog-to-digital converter, and the analog-to-digital converter is electrically connected to a gateway processor. When an arbitrary analog signal is input into the programmable gain amplifier through the analog signal acquisition circuit, the peak value detection unit detects the peak value of the amplified signal, the hysteresis comparator compares the peak value of the amplified signal and a reference voltage provided by the reference voltage source, and feeds back to the adaptive gain amplifier controller, and the gain amplifier controller adjusts the programmable gain amplifier and the adjustable bias voltage source according to the peak value of the amplified signal, so that gain multiple adjustment and input signal bias voltage adjustment are realized, thereby adapting to an arbitrary analog signal communication terminal, and adaptive collection of analog signals meeting the requirements is realized. BRIEF DESCRIPTION OF DRAWINGS

[0016] The drawings incorporated into the specification and constituting a part of the specification show embodiments consistent with the utility model and, together with the specification, serve to explain the principle of the utility model.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings needed to be used in the embodiment or the prior art description will be briefly introduced as follows, and obviously, other drawings can also be obtained by those skilled in the art without any creative labor under the premise of not paying any creative labor.

[0018] Figure 1 A schematic diagram of the gateway for adapting to multiple analog communication terminals is provided in the utility model;

[0019] Figure 2 A schematic diagram of the analog signal acquisition circuit is provided in the utility model;

[0020] Figure 3 A schematic view of the peak detection unit is provided in the present application.

[0021] Figure 4 A schematic view of the digital signal acquisition circuit is provided in the present application.

[0022] Figure 5 A schematic view of the multi-channel digital signal output circuit is provided in the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0024] Referring to Figure 1 The embodiments of the present application provide a gateway adaptive to multiple analog communication terminals, which comprises:

[0025] A gateway processor, which is connected to a programmable analog signal acquisition circuit, and the programmable analog signal acquisition circuit can adapt to terminals using different analog signal amplitude communication.

[0026] Specifically, the programmable analog signal acquisition circuit comprises:

[0027] An analog signal acquisition circuit, as shown in Figure 2 The analog signal acquisition circuit comprises: an analog signal differential H input circuit and an analog signal differential L input circuit; the analog signal differential H input circuit and the analog signal differential L input circuit are respectively connected in series with an anti-interference resistor R15 and an anti-interference resistor R16; the analog signal differential H input circuit and the analog signal differential L input circuit are respectively connected with a filter capacitor C1 and a filter capacitor C3 grounded, and are respectively connected with a positive and negative clamping diode D3 and a positive and negative clamping diode D4, and a filter capacitor C2 is arranged between the analog signal differential H input circuit and the analog signal differential L input circuit; the analog signal differential H input circuit is connected with an upper pull power supply through a resistor R14, and the analog signal differential H input circuit is grounded through a resistor R17.

[0028] An adaptive gain amplifier is connected to the input end of the analog signal acquisition circuit, the output end of the adaptive gain amplifier is connected with an analog-to-digital converter, and the analog-to-digital converter is electrically connected with the gateway processor.

[0029] The adaptive gain amplifier comprises a programmable gain amplifier, an output end of the programmable gain amplifier is connected to a peak value detection unit for detecting a peak value of an amplified signal, an output end of the peak value detection unit is connected to one input of a hysteresis comparator, another input of the hysteresis comparator is connected to a reference voltage source, an output of the hysteresis comparator is connected to an adaptive gain amplifier controller, the adaptive gain amplifier controller is connected to an adjustable bias voltage source and a control pin of the programmable gain amplifier, and an output voltage of the adjustable bias voltage source acts on an input of the programmable gain amplifier; an output end of the programmable gain amplifier is connected to the analog-to-digital converter, and the analog-to-digital converter is connected to the gateway processor. When an arbitrary analog signal is input into the programmable gain amplifier through the analog signal acquisition circuit, the peak value detection unit detects a peak value of an amplified signal, the hysteresis comparator compares the peak value of the amplified signal with a reference voltage provided by the reference voltage source, and feeds back to the adaptive gain amplifier controller, and the gain amplifier controller adjusts the programmable gain amplifier and the adjustable bias voltage source according to the peak value of the amplified signal, so as to realize gain multiple adjustment and input signal bias voltage adjustment, thereby adapting to an arbitrary analog signal communication terminal and adaptively acquiring a required analog signal.

[0030] In the implementation process, the gateway processor is connected to the adaptive gain amplifier controller. The adaptive gain amplifier sends its gain adjustment state to the gateway processor, so as to support the gateway processor to convert and send analog signals with different gains.

[0031] In the implementation process, as shown in Figure 3 The peak value detection unit comprises an operational amplifier U4A, an output end of the operational amplifier U4A is connected to an output end of the programmable gain amplifier, the output end of the operational amplifier U4A is connected to a sampling capacitor C4 grounded through a diode D6, and a diode D5 is coupled between the output end and an inverting input end of the operational amplifier U4A; the sampling capacitor C4 is connected in parallel with a reset switch S1, a non-grounded plate of the sampling capacitor C4 is connected to a non-inverting input end of an operational amplifier U4B, an output end of the operational amplifier U4B is fed back to an inverting input end, and the output end of the operational amplifier U4B is coupled to the output of the operational amplifier U4A through a resistor R14.

[0032] The gateway processor is connected to the digital signal acquisition circuit to support the acquisition of high-level digital signals. As shown in Figure 4 The digital signal acquisition circuit comprises a plurality of optocouplers, a transmitting end of each optocoupler is connected to a digital input interface, wherein the transmitting end of the optocoupler is connected to a digital input; a collector of a receiving end of each optocoupler is connected to a 3.3V voltage, an emitter is grounded through a resistor, and a gateway processor is connected to an emitter of the receiving end of each optocoupler through a digital input IO interface.

[0033] The gateway processor is connected to a digital signal output circuit to support the output of high-level digital signals. Each digital signal output circuit includes: a voltage divider circuit composed of two series resistors connected to the digital output IO interface of the gateway processor, the two resistors of the voltage divider circuit are connected to a coupling resistor, the coupling resistor is connected to the base of the first-stage transistor in the Darlington transistor, the coupling resistor is connected between the base and emitter of the two-stage transistor in the Darlington transistor, the collectors of the two-stage transistors are connected to the common end through a clamping diode, the common end is connected to the positive pole of the output power supply, and the collectors of the two-stage transistors are connected to the digital signal relay. Figure 5 As shown, Figure 5 A multi-channel digital signal output circuit is shown in the figure. Resistors R1 and R2, connected in series, form a voltage divider circuit. Resistors R3 and R4, connected in series, form another voltage divider circuit. These two voltage divider circuits are connected to Darlington transistors Q1 and Q2, respectively, through coupling resistors R5 and R6. Coupling resistor R5 is connected to the base of the first-stage transistor in Darlington transistor Q1, and coupling resistor R6 is connected to the base of the first-stage transistor in Darlington transistor Q2. Resistors R6 and R7 are coupled between the base and emitter of the two-stage transistors in Darlington transistor Q1, respectively. The collectors of the two-stage transistors are connected to a common terminal via a clamping diode D1. Resistors R9 and R10 are coupled between the base and emitter of the two-stage transistor in Darlington transistor Q2, respectively. The collectors of the two-stage transistors are connected to a common terminal via a clamping diode D2. The common terminal is connected to the positive terminal of the output power supply. The collectors of the two-stage triodes in the Darlington transistor Q1 are connected to the digital signal relay K1 , and the collectors of the two-stage triodes in the Darlington transistor Q2 are connected to the digital signal relay K2 .

[0034] During the specific implementation process, the gateway processor is connected to any one or a combination of a 4G wireless communication circuit, a WiFi communication circuit, an RS232 communication circuit, an RS485 communication circuit, and an Ethernet communication circuit. By connecting more communication circuits, the gateway of the present application can support the forwarding of multiple communication protocol information.

[0035] A gateway that is adaptive to multiple analog communication terminals includes a power supply module, which includes: a power adapter that converts 220V AC power into 12V DC power; and a DC-DC voltage stabilizing unit that converts 12V DC voltage into 5V, 3.8V and 3.3V DC power.

[0036] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0037] In the embodiments provided by the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the circuit description is only a logical function division. In actual implementation, another division manner can be used. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling between the displayed or discussed elements can be indirect coupling through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0038] The above description is merely specific embodiments of the present application, enabling those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A gateway for adapting a plurality of analog communication terminals, characterized by The application relates to a gateway processor connected to a programmable analog signal acquisition circuit, wherein the programmable analog signal acquisition circuit comprises an analog signal acquisition circuit, an input end of the analog signal acquisition circuit is connected to an adaptive gain amplifier, an output end of the adaptive gain amplifier is connected to an analog-to-digital converter, and the analog-to-digital converter is electrically connected to the gateway processor. The adaptive gain amplifier comprises a programmable gain amplifier, an output end of the programmable gain amplifier is connected to a peak value detection unit, an output of the peak value detection unit is connected to one input of a hysteresis comparator, another input of the hysteresis comparator is connected to a reference voltage source, an output of the hysteresis comparator is electrically connected to an adaptive gain amplifier controller, the adaptive gain amplifier controller is connected to an adjustable bias voltage source and a control pin of the programmable gain amplifier, and an output voltage of the adjustable bias voltage source acts on an input of the programmable gain amplifier; the output end of the programmable gain amplifier is connected to the analog-to-digital converter, and the analog-to-digital converter is electrically connected to the gateway processor. The analog signal acquisition circuit comprises analog signal differential H input lines and analog signal differential L input lines; the analog signal differential H input lines and the analog signal differential L input lines are respectively connected in series with anti-interference resistors, the analog signal differential H input lines and the analog signal differential L input lines are respectively connected to filter capacitors grounded, the analog signal differential H input lines and the analog signal differential L input lines are respectively connected to positive and negative clamping diodes, filter capacitors are arranged between the analog signal differential H input lines and the analog signal differential L input lines, the analog signal differential H input lines are connected to an upper pull power source through resistors, and the analog signal differential H input lines are grounded through resistors.

2. The gateway for adaptive multi-mode analog communication terminals of claim 1, wherein, The peak value detection unit comprises an operational amplifier U4A, a non-inverting input end of the operational amplifier U4A is connected to an output end of the programmable gain amplifier, an output end of the operational amplifier U4A is connected to a sampling capacitor C4 grounded through a diode D6, and a diode D5 is coupled between the output end and an inverting input end of the operational amplifier U4A; the sampling capacitor C4 is connected in parallel with a reset switch S1, a non-grounded plate of the sampling capacitor C4 is connected to a non-inverting input end of an operational amplifier U4B, an output end of the operational amplifier U4B is fed back to an inverting input end, and the output end of the operational amplifier U4B is coupled to an output of the operational amplifier U4A through a resistor R14.

3. The gateway of claim 1, wherein, The gateway processor is connected to a digital signal acquisition circuit; the digital signal acquisition circuit comprises a plurality of optical couplings, an emitting end of each optical coupling is connected to a digital input interface, wherein the emitting end of the optical coupling is connected to a digital input; a collector of a receiving end of each optical coupling is connected to a 3.3V voltage, and an emitter is grounded through a resistor; and the gateway processor is connected to an emitter of the receiving end of each optical coupling through a digital input IO interface.

4. The gateway of claim 1, wherein, ​ 5. The gateway of claim 1, wherein, The gateway processor is connected with digital signal output circuit; each of the digital signal output circuit comprises: a voltage dividing circuit composed of two series resistors connected with the digital output IO interface of the gateway processor, a coupling resistor connected between the two resistors of the voltage dividing circuit, the coupling resistor connected to the base of the first stage transistor of Darlington transistor, the coupling resistor between the base and the emitter of the second stage transistor of Darlington transistor, the collector of the second stage transistor connected to the common terminal through the clamping diode, the common terminal connected to the positive pole of the output power supply, and the collector of the second stage transistor connected with the digital signal relay.

6. The gateway of claim 1, wherein, The gateway processor is connected with any one or combination of several of the following communication circuits: 4G wireless communication circuit, WiFi communication circuit, RS232 communication circuit, RS485 communication circuit and Ethernet communication circuit.

7. The gateway of claim 1, wherein, The gateway processor is connected with the adaptive gain amplifier controller.

8. The gateway of claim 1, wherein, The power supply module for power supply comprises: a power adapter for converting 220V AC into 12V DC; and a DC-DC voltage stabilizing unit for converting 12V DC voltage into 5V, 3.8V and 3.3V DC.

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