Consumable chip and consumable box with same

Abstract

The utility model relates to a consumable chip and a consumable box with the same, the consumable chip comprises a substrate, at least one low voltage terminal, at least one high voltage terminal and at least one detection terminal, the low voltage terminal, the high voltage terminal and the detection terminal are arranged on the substrate, the high voltage terminal and the detection terminal are arranged at an interval, the number of the high voltage terminal and the detection terminal is two, and the high voltage terminal and the detection terminal are arranged at an interval; the consumable chip further comprises a conductive structure, the conductive structure comprises a conductive lead, the conductive lead comprises a connecting section and a blocking section, one end of the connecting section is electrically connected with at least one low-voltage terminal, the other end of the connecting section is connected with the blocking section, and the two ends of the blocking section correspond to the high-voltage terminals and the detection terminals respectively. And the two ends of the blocking section respectively extend to the part between the high-voltage terminal and the detection terminal in the corresponding group.

Description

[0001] This application is a divisional application of the application with the application number 2022900005709 and the application name "Consumable Chip and Consumable Box with the Same", the application date of which is January 29, 2022. TECHNICAL FIELD

[0002] The present application relates to the technical field of printing equipment, in particular to a consumable chip and a consumable box with the same. BACKGROUND

[0003] The printing equipment needs to be used with the consumable box. The common consumable box is an ink cartridge. The ink cartridge is provided with an ink cartridge chip. The ink cartridge chip is used to store brand information, ink type information, ink color information and ink dosage information. After the ink cartridge is installed in the printing equipment, it needs to be authenticated before it can be normally used. Therefore, the ink cartridge chip plays a crucial role in whether the printing equipment can normally use the ink cartridge.

[0004] In order to connect with the ink cartridge and the ink cartridge chip, the printing equipment end is provided with a plurality of contact pins. Correspondingly, the ink cartridge chip is provided with a plurality of terminals corresponding to the plurality of contact pins. In the related art, the contact pins of the printing equipment end include high-voltage contact pins and detection contact pins. The terminals of the ink cartridge chip include high-voltage terminals, detection terminals and signal transmission terminals. The signal transmission terminals include a plurality of conductive terminals, such as power terminals, ground terminals and data terminals. In order to verify whether the ink cartridge is installed in place, the printing equipment verifies the installation by verifying the contact conditions of the high-voltage terminals and the high-voltage contact pins, and the detection terminals and the detection contact pins. If the printing equipment judges that the contact conditions of the high-voltage terminals and the high-voltage contact pins, and the detection terminals and the detection contact pins are good, it is determined that the signal transmission terminals of the ink cartridge chip and the contact pins of the printing equipment end are also in good contact.

[0005] However, sometimes the high-voltage terminals and the adjacent detection terminals of the ink cartridge chip may be short-circuited due to ink leakage or deformation of the contact pins, which may cause damage to the ink cartridge chip and the printing equipment, causing unnecessary economic loss and time loss to the consumer.

[0006] In the related art, a scheme of setting a short-circuit detection circuit at the printing equipment end is disclosed. The short-circuit detection circuit is used to detect the voltage change of the contact pins of the printing equipment end, so as to judge whether the terminals on the ink cartridge chip are short-circuited. However, the above short-circuit detection scheme is performed after the ink cartridge chip is installed on the printing equipment end. At this time, although the short-circuit phenomenon is detected, the storage elements on the ink cartridge chip may have been damaged by short-circuit. In addition, there are printing equipment on the market that do not set a short-circuit detection circuit. For such printing equipment, there is a great safety hazard.

[0007] In the related art, a scheme of setting a short circuit detection mechanism at the ink cartridge chip is also disclosed. Although the scheme can independently complete the detection of the short circuit phenomenon at the ink cartridge chip, the scheme needs to additionally set a detection terminal and a corresponding hardware circuit on the ink cartridge chip substrate, which is high in cost and complex, and may potentially interfere with the normal communication between the ink cartridge chip and the printing device. Utility model content

[0008] Therefore, it is necessary to provide a consumable chip capable of independently processing a short circuit abnormality, simple in structure and low in cost, and a consumable cartridge with the same.

[0009] To achieve the above object, the technical scheme provided by the present application is as follows:

[0010] A consumable chip, comprising a memory, a substrate, at least one low-voltage terminal electrically connected to the memory, at least one high-voltage terminal, and at least one detection terminal disposed on the substrate, the high-voltage terminal and the detection terminal are spaced apart, and the number of the high-voltage terminal and the detection terminal is two groups and spaced apart.

[0011] The consumable chip further comprises a conductive structure, the conductive structure comprises at least one conductive lead, the conductive lead comprises a connecting segment and a blocking segment, one end of the connecting segment is electrically connected to at least one low-voltage terminal, the other end is connected to the blocking segment, the two ends of the blocking segment correspond to a group of high-voltage terminals and detection terminals respectively, and the two ends of the blocking segment respectively extend to between the high-voltage terminal and the detection terminal in the corresponding group.

[0012] In one of the embodiments, a first slot is formed on the sidewall of the substrate, and a conductive layer is arranged in the first slot and forms the low-voltage terminal; and / or

[0013] A second slot is formed on the sidewall of the substrate, and a conductive layer is arranged in the second slot and forms the high-voltage terminal; and / or

[0014] A third slot and a fourth slot are arranged on the sidewall of the substrate, the fourth slot is formed along the length direction of the substrate, and the third slot is arranged on the sidewall of the fourth slot, a conductive layer is arranged in the third slot and forms the detection terminal.

[0015] In one of the embodiments, the second slot is a right-angle slot having a long-side sidewall and a short-side sidewall, and the long-side sidewall is provided with a conductive layer and forms the high-voltage terminal.

[0016] In one of the embodiments, the low-voltage terminal is any one of an enable terminal, a clock terminal, a ground terminal, a data terminal, and a power terminal.

[0017] In one of the embodiments, the conductive lead is a metal lead.

[0018] In one of the embodiments, the conductive lead is in T shape or L shape.

[0019] In one of the embodiments, the low-voltage terminal connected with the conductive lead is a ground terminal.

[0020] A consumable chip comprises a memory, a substrate, at least one low-voltage terminal electrically connected with the memory, at least one high-voltage terminal, and at least one detection terminal, the high-voltage terminal and the detection terminal are arranged in intervals,

[0021] The consumable chip further comprises a conductive structure, the conductive structure comprises at least one conductive lead, the conductive lead comprises a connecting segment and a blocking segment, one end of the connecting segment is electrically connected with at least one low-voltage terminal, the other end is connected with the blocking segment, and the end of the blocking segment extends between the high-voltage terminal and the detection terminal.

[0022] In one of the embodiments, the number of the high-voltage terminals and the detection terminals is two groups and arranged in intervals, wherein:

[0023] There are at least two conductive structures between each group of the high-voltage terminals and the detection terminals; or

[0024] There is one conductive structure between one group of the high-voltage terminals and the detection terminals, and there are at least two conductive structures between another group of the high-voltage terminals and the detection terminals.

[0025] A consumable box comprises a consumable box body and a consumable chip, the consumable chip is arranged on the consumable box body.

[0026] A consumable chip comprises a memory, a substrate, at least one low-voltage terminal electrically connected with the memory, at least one high-voltage terminal, and at least one detection terminal, the high-voltage terminal and the detection terminal are arranged in intervals, the consumable chip further comprises a conductive structure, one end of the conductive structure is electrically connected with the low-voltage terminal, and the other end of the conductive structure extends between the high-voltage terminal and the detection terminal.

[0027] It can be understood that, in the present application, the conductive structure is arranged, and one end of the conductive structure away from the low-voltage terminal extends between the high-voltage terminal and the detection terminal, so that if the high-voltage terminal and the detection terminal are short-circuited due to ink or the like, the high voltage on the high-voltage terminal will be guided to the corresponding low-voltage terminal through the conductive structure, so as to divide and reduce the high voltage through the low-voltage terminal, and prevent the high voltage on the high-voltage terminal from being applied to the detection terminal; that is, the detection terminal does not receive the high-voltage signal, so as to play a role of short-circuit detection and short-circuit protection, and avoid the consumable chip and the printing device from being burned out or damaged due to the high voltage.

[0028] In one embodiment, the high-voltage terminals and the detection terminals are arranged in two groups and are spaced apart, and at least one low-voltage terminal is connected to at least one conductive structure, one end of the conductive structure is electrically connected to the low-voltage terminal, and the other end extends to between at least one group of high-voltage terminals and detection terminals.

[0029] In one embodiment, there are at least two conductive structures between each group of high-voltage terminals and detection terminals; or

[0030] There is one conductive structure between one group of high-voltage terminals and detection terminals, and there are at least two conductive structures between another group of high-voltage terminals and detection terminals.

[0031] In one embodiment, the conductive structure is a metal lead.

[0032] In one embodiment, the conductive structure is T-shaped or L-shaped.

[0033] In one embodiment, a first notch is formed on the sidewall of the substrate, and a conductive layer is arranged in the first notch to form the low-voltage terminal; and / or

[0034] A second notch is formed on the sidewall of the substrate, and a conductive layer is arranged in the second notch to form the high-voltage terminal; and / or

[0035] A third notch and a fourth notch are arranged on the sidewall of the substrate, the fourth notch is formed along the length direction of the substrate, and the third notch is arranged on the sidewall of the fourth notch, and a conductive layer is arranged in the third notch to form the detection terminal.

[0036] In one embodiment, the second notch is a right-angle notch having a long-side sidewall and a short-side sidewall, and the long-side sidewall is provided with a conductive layer to form the high-voltage terminal.

[0037] In one embodiment, the conductive structure includes a connecting segment and a blocking segment, one end of the connecting segment is electrically connected to the low-voltage terminal, the other end of the connecting segment is electrically connected to the blocking segment, and the blocking segment extends between the high-voltage terminal and the detection terminal. The present application also provides the following technical solutions: a consumable cartridge including a consumable cartridge body and a consumable chip as described above, and the consumable chip is arranged on the consumable cartridge body.

[0038] A manufacturing method of a consumable chip for manufacturing the consumable chip described above.

[0039] Compared with the related art, the consumable chip sets the conductive structure, and the conductive structure extends to between the high-voltage terminal and the detection terminal away from one end of the low-voltage terminal, so that if the high-voltage terminal and the detection terminal are short-circuited due to ink or the like, the high voltage on the high-voltage terminal will be guided to the corresponding low-voltage terminal through the conductive structure, so that the low-voltage terminal divides and reduces the voltage, preventing the high voltage on the high-voltage terminal from being applied to the detection terminal; that is, the detection terminal does not receive the high-voltage signal, so as to play a role in short-circuit detection and short-circuit protection, avoiding the consumable chip and the printing device from being burned out or damaged due to high voltage. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 Structure diagram of the consumable chip provided in the present application Figure 1 ;

[0041] Figure 2 Structure diagram of the consumable chip provided in the present application Figure 2 ;

[0042] Figure 3 Structure diagram of the consumable chip provided in the present application Figure 3 ;

[0043] Figure 4 Structure diagram of the consumable chip provided in the present application Figure 1 ;

[0044] Figure 5 Schematic diagram of the terminal of the consumable chip provided in the present application in contact with the stylus of the printing device

[0045] Figure 6 Schematic diagram of the consumable chip provided in the present application with ink drops

[0046] Figure 7 Structure diagram of the consumable chip provided in the present application Figure 2 ;

[0047] Figure 8 Structure diagram of the consumable chip provided in the present application Figure 3 ;

[0048] Figure 9 Schematic diagram of the two detection terminals and the memory electrically connected provided in the present application

[0049] Figure 10 Structure diagram of the consumable chip provided in the present application

[0050] Figure 11 Structure diagram of the consumable chip provided in the present application

[0051] Figure 12A structural schematic diagram of consumable chip embodiment 4 provided in the present application;

[0052] Figure 13 A structural schematic diagram of consumable chip embodiment 5 provided in the present application;

[0053] Figure 14 A structural schematic diagram of consumable chip embodiment 6 provided in the present application;

[0054] Figure 15 A structural schematic diagram of consumable chip embodiment 7 provided in the present application;

[0055] Figure 16 A structural schematic diagram of consumable chip embodiment 8 provided in the present application;

[0056] Figure 17 A structural schematic diagram of consumable chip embodiment 9 provided in the present application;

[0057] Figure 18 A structural schematic diagram of consumable chip embodiment 10 provided in the present application;

[0058] Figure 19 A structural schematic diagram of consumable chip embodiment 11 provided in the present application;

[0059] Figure 20 A structural schematic diagram of consumable chip embodiment 12 provided in the present application Figure 1 ;

[0060] Figure 21 A structural schematic diagram of consumable chip embodiment 12 provided in the present application Figure 2 ;

[0061] Figures 1-9 A flowchart of a manufacturing method of a consumable chip provided in the present application.

[0062] Reference numerals: 100, consumable chip; 10, substrate; 10a, first surface; 11, first notch; 12, second notch; 13, third notch; 14, fourth notch; 100a, low-voltage terminal; 101, first low-voltage terminal; 101a, enable terminal; 101b, clock terminal; 101c, ground terminal; 101d, data terminal; 101e, power terminal; 102, second low-voltage terminal; 103, third low-voltage terminal; 104, memory; 105, fourth low-voltage terminal; 21, high-voltage terminal; 22, detection terminal; 3, conductive structure; 30, conductive lead; 301, connecting segment; 302, blocking segment; 303, first connecting segment; 304, first blocking segment; 305, second connecting segment; 306, second blocking segment; 31, first conductive lead; 311, third connecting segment; 312, third blocking segment; 32, second conductive lead; 321, fourth connecting segment; 322, fourth blocking segment; 33, third conductive lead; 34, fourth conductive lead. DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0064] It should be noted that when a component is referred to as being "mounted on" another component, it can be directly mounted on the other component or there can be a middle component. When a component is referred to as being "disposed on" another component, it can be directly disposed on the other component or there can be a middle component. When a component is referred to as being "fixed on" another component, it can be directly fixed on the other component or there can be a middle component.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing the particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0066] As shown in FIG. 1, the present application provides a consumable chip 100 mounted on a consumable cartridge for recording / inscribing relevant information of the consumable cartridge and realizing connection between the consumable cartridge and a printing device. Figure 2

[0067] ​The consumable chip 100 comprises a memory 104, a substrate 10, at least one low-voltage terminal 100a electrically connected to the memory 104, at least one high-voltage terminal 21 and at least one detection terminal 22 arranged on the substrate 10, the high-voltage terminal 21 and the detection terminal 22 are arranged at intervals, and the consumable chip 100 further comprises a conductive structure 3, one end of the conductive structure 3 is electrically connected to the low-voltage terminal, and the other end of the conductive structure 3 extends between the high-voltage terminal 21 and the detection terminal 22.

[0068] By arranging the conductive structure 3, and the one end of the conductive structure 3 extending to between the high-voltage terminal 21 and the detection terminal 22 away from the low-voltage terminal 100a, if the high-voltage terminal 21 and the detection terminal 22 are short-circuited due to ink or the like, the high voltage on the high-voltage terminal 21 will be guided to the corresponding low-voltage terminal 100a through the conductive structure 3, so as to divide and reduce the high voltage through the low-voltage terminal 100a, and prevent the high voltage on the high-voltage terminal 21 from being applied to the detection terminal 22; that is, the detection terminal 22 does not receive a high-voltage signal, so as to play a role of short-circuit detection and short-circuit protection, and avoid the consumable chip and the printing device from being burned out or damaged due to high voltage.

[0069] Further, the number of the high-voltage terminal 21 and the detection terminal 22 is two groups and arranged at intervals, at least one low-voltage terminal 100a is connected to at least one conductive structure 3, one end of the conductive structure 3 is electrically connected to the low-voltage terminal 100a, and the other end of the conductive structure 3 extends between at least one group of high-voltage terminals 21 and detection terminals 22.

[0070] It should be noted that one low-voltage terminal 100a can be connected to multiple conductive structures 3, one conductive structure 3 can be connected to multiple low-voltage terminals, and the other end of the conductive structure 3 can extend between one group of high-voltage terminals 21 and detection terminals 22, or can extend between two groups of high-voltage terminals 21 and detection terminals 22 respectively.

[0071] In some embodiments, the conductive structure 3 comprises a connecting segment 301 and a blocking segment 302, one end of the connecting segment 301 is electrically connected to the low-voltage terminal 100a, the other end of the connecting segment 301 is electrically connected to the blocking segment 302, and the blocking segment 302 extends between the high-voltage terminal 21 and the detection terminal 22.

[0072] It should be noted that the blocking segment 302 can extend between any one group of high-voltage terminals 21 and detection terminals 22, or can extend between two groups of high-voltage terminals 21 and detection terminals 22 respectively.

[0073] Further, as shown in Figure 3 The number of the high-voltage terminal 21 and the detection terminal 22 is two groups, and the two groups of terminals are arranged at intervals on the substrate 10;

[0074] The conductive structure 3 includes a conductive lead 30, which includes a connecting section 301 and a blocking section 302; one end of the connecting section 301 is electrically connected to at least one low-voltage terminal 100a, and the other end is connected to the blocking section 302; the two ends of the blocking section 302 correspond to a group of terminals respectively, and the two ends of the blocking section 302 extend respectively to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group.

[0075] In this embodiment, both sets of high-voltage terminals 21 and detection terminals 22 can be connected to the same low-voltage terminal 100 a through the blocking section 302 and the connecting section 301 of the conductive lead 30 .

[0076] Further, such as Figure 3 As shown, there are two groups of high-voltage terminals 21 and detection terminals 22, and the two groups of terminals are arranged on the substrate 10 at intervals;

[0077] The conductive structure 3 includes multiple conductive leads 30, one end of at least one conductive lead 30 is electrically connected to at least one low-voltage terminal 100a, and the other end extends between a group of high-voltage terminals 21 and a detection terminal 22; one end of at least one conductive lead 30 is electrically connected to at least one low-voltage terminal 100a, and the other end extends between another group of high-voltage terminals 21 and a detection terminal 22.

[0078] In this embodiment, the conductive structure includes a plurality of conductive leads 30, and at least one conductive lead 30 is connected to at least one low-voltage terminal 100a between any group of high-voltage terminals 21 and detection terminals 22. The wire leads 30 between two groups of high-voltage terminals 21 and detection terminals 22 can be connected to the same low-voltage terminal 100a, or different low-voltage terminals 100a.

[0079] In some embodiments, there are at least two conductive structures 3 between each set of high voltage terminals 21 and detection terminals 22; or

[0080] There is one conductive structure 3 between one group of high-voltage terminals 21 and the detection terminals 22 , and there are at least two conductive structures 3 between another group of high-voltage terminals 21 and the detection terminals.

[0081] Further, such as Figure 4 As shown, the conductive lead 30, the other end of which extends between a group of high-voltage terminals 21 and detection terminals 22, includes a first connecting section 303 and a first blocking section 304; one end of the first connecting section 303 is electrically connected to at least one low-voltage terminal 100a, and the other end is connected to the first blocking section 304; the two ends of the first blocking section 304 correspond to a group of terminals, and the two ends of the first blocking section 304 respectively extend between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group;

[0082] and / or,

[0083] The other end of the conductive lead 30 extending between the high-voltage terminal 21 and the detection terminal 22 of the other group includes a second connecting segment 305 and a second blocking segment 306; one end of the second connecting segment 305 is electrically connected to the at least one low-voltage terminal 100a, and the other end of the second connecting segment 305 is connected to the second blocking segment 306; the two ends of the second blocking segment 306 correspond to a group of terminals respectively, and the two ends of the second blocking segment 306 extend to the high-voltage terminal 21 and the detection terminal 22 of the corresponding group respectively.

[0084] In the embodiment, any one of the conductive leads 30 can simultaneously extend between the high-voltage terminal 21 and the detection terminal 22 of the corresponding group.

[0085] Specifically, as shown in Figure 5 , the low-voltage terminal 100a includes a first low-voltage terminal 101 and a second low-voltage terminal 102 arranged at intervals, the conductive structure 3 includes a first conductive lead 31 and a second conductive lead 32, one end of the first conductive lead 31 is electrically connected to the first low-voltage terminal 101, and the other end of the first conductive lead 31 extends between the high-voltage terminal 21 and the detection terminal 22, one end of the second conductive lead 32 is electrically connected to the second low-voltage terminal 102, and the other end of the second conductive lead 32 extends between the high-voltage terminal 21 and the detection terminal 22 corresponding to the first conductive lead 31.

[0086] When the consumable cartridge is installed on the printing device (as shown in Figure 6 ), the internal installation detection part of the printing device applies a high voltage (about 40V) to the high-voltage terminal 21, so as to detect whether the high-voltage terminal 21 is in electrical contact with the corresponding stylus on the printing device by detecting the voltage or current value transmitted to the output end of the installation detection part, and then determine whether the consumable cartridge is correctly installed on the printing device.

[0087] It needs to be explained that in the related art, sometimes the conductive material such as ink will be sputtered on the substrate 10 and cover the high-voltage terminal 21 and the detection terminal 22, causing the high-voltage terminal 21 and the detection terminal 22 to be in communication and short-circuit, resulting in damage to the consumable chip 100 and / or the printing device. After the printing device and the consumable chip 100 are in communication, the printing device detects the state of the consumable chip 100 using the internal circuit, for example, the installation state and the ink amount state; the printing device usually inputs a voltage of about 40V to one of the high-voltage terminals 21 and outputs through the other high-voltage terminal 21, and the voltage output by the other high-voltage terminal 21 is usually greater than 3.2V and less than 40V. At the same time, the printing device usually sends a voltage not higher than 3.2V or not higher than 5V to one of the two detection terminals 22, and the other detection terminal 22 outputs a voltage not higher than 3.2V or not higher than 5V, so that the voltage received by the two high-voltage terminals 21 is higher than the voltage received by the detection terminal 22, and because the voltage difference between the two is too large, if a short circuit occurs between the two and the high voltage is incorrectly applied to the low-voltage detection terminal 22, it may cause the consumable chip 100 to be damaged before the short-circuit protection function of the detection terminal 22 is triggered.

[0088] Therefore, based on the above-mentioned problems, the present application provides a new consumable chip 100, which is provided with a first conductive lead 31 and a second conductive lead 32, and the first conductive lead 31 and the second conductive lead 32 respectively extend from one end of the first low-voltage terminal 101 and the second low-voltage terminal 102 to between the high-voltage terminal 21 and the detection terminal 22. Therefore, if a short circuit occurs between the high-voltage terminal 21 and the detection terminal 22 due to the conductive material such as ink, the high voltage on the high-voltage terminal 21 will be guided to the corresponding first low-voltage terminal 101 and second low-voltage terminal 102 through the first conductive lead 31 and the second conductive lead 32, so as to divide and reduce the high voltage through the first low-voltage terminal 101 and the second low-voltage terminal 102, thereby preventing the high voltage on the high-voltage terminal 21 from being applied to the detection terminal 22; that is, the detection terminal 22 does not receive the high-voltage signal, so as to play a role in short-circuit detection and short-circuit protection, thereby avoiding the consumable chip 100 and the printing device from being burned and damaged due to high voltage.

[0089] The specific principle is as follows: as shown in Figure 8 If a short circuit occurs between the high-voltage terminal 21 and the detection terminal 22 due to ink droplets, the ink droplets will certainly cover the conductive lead extending between the high-voltage terminal 21 and the detection terminal 22, thereby causing the low-voltage terminal 100a connected with the conductive lead to trigger the short-circuit protection mechanism before the detection terminal 22.

[0090] When high voltage is led to the low voltage terminal 100a through the conductive lead, the cartridge chip will trigger the printing device to give an error prompt such as "request to turn off power" or "abnormal installation of cartridge", so that the printing device cannot print, prompting the user to check or replace the cartridge. When the high voltage input terminal and the enable terminal are short-circuited, the voltages of the high voltage input terminal and the high voltage output terminal will be pulled low by the enable terminal at the same time, at which time the printing device will prompt an error prompt such as "request to turn off power".

[0091] When the high voltage input terminal and the power terminal are short-circuited, the voltages of the high voltage input terminal and the high voltage output terminal will be pulled low by the power terminal at the same time, at which time the printing device will prompt an error prompt such as "request to turn off power".

[0092] When the high voltage input terminal and the power terminal, the ground terminal are short-circuited, the voltages of the high voltage input terminal and the high voltage output terminal will be pulled low at the same time, at which time the printing device will prompt an error prompt such as "request to turn off power".

[0093] When the high voltage output terminal and the clock terminal are short-circuited, the voltage of the high voltage output terminal will be pulled low by the clock terminal, while the high voltage input terminal will still normally send the installation detection signal to the high voltage output terminal, at which time the printing device cannot obtain the normal installation detection signal through the high voltage output terminal, at which time the printing device will prompt an error prompt such as "abnormal installation of cartridge".

[0094] When the high voltage output terminal and the data terminal are short-circuited, the voltage of the high voltage output terminal will be pulled low by the data terminal, while the high voltage input terminal will still normally send the installation detection signal to the high voltage output terminal, at which time the printing device cannot obtain the normal installation detection signal through the high voltage output terminal, at which time the printing device will prompt an error prompt such as "abnormal installation of cartridge".

[0095] When the high voltage output terminal and the data terminal, the ground terminal are short-circuited, the voltage of the high voltage output terminal will be pulled low, while the high voltage input terminal will still normally send the installation detection signal to the high voltage output terminal, at which time the printing device cannot obtain the normal installation detection signal through the high voltage output terminal, at which time the printing device will prompt an error prompt such as "abnormal installation of cartridge".

[0096] As an option, the substrate 10 includes a first face 10a and a second face (not shown) arranged opposite to each other, the first low voltage terminal 101, the second low voltage terminal 102, the conductive lead 30, and the high voltage terminal 21 and the detection terminal 22 are all arranged on the first face 10a, and the memory 104 is arranged on the second face.

[0097]

[0098] ​It should be explained that the high voltage can be greater than the working voltage of the consumable chip 100, i.e. the voltage applied to the chip terminal. Generally, the working voltage of the consumable chip 100 is 3.3V or 5V, and accordingly, the high voltage can be a voltage higher than 3.3V or higher than 5V, and the low voltage can be a voltage lower than 3.3V or lower than 5V.

[0099] In some embodiments, the sidewall of the substrate 10 is provided with a first slot 11, and the first slot 11 is provided with a conductive layer and forms a low-voltage terminal 100a; and / or

[0100] The sidewall of the substrate 10 is provided with a second slot 12, and the second slot 12 is provided with a conductive layer and forms a high-voltage terminal 21; and / or

[0101] The sidewall of the substrate 10 is provided with a third slot 13 and a fourth slot 14, the fourth slot 14 is formed along the length direction of the substrate 10 (i.e. the x-axis direction in the figure), and the third slot 13 is arranged on the sidewall of the fourth slot 14, and the third slot 13 is provided with a conductive layer and forms a detection terminal 22. Figure 4

[0102] As shown in the figure, the first low-voltage terminal 101 can be any one of an enable terminal 101a, a clock terminal 101b, a ground terminal 101c, a data terminal 101d and a power terminal 101e. The second low-voltage terminal 102 can also be any one of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and the power terminal 101e. In this embodiment, the first low-voltage terminal 101 is the power terminal 101e, and the second low-voltage terminal 102 is the enable terminal 101a. Figure 7 Further, the first low-voltage terminal 101 and / or the second low-voltage terminal 102 can be formed by arranging a conductive layer on the substrate 10. The first low-voltage terminal 101 and / or the second low-voltage terminal 102 are solid terminals, and the shape can be set as any shape such as a waist hole shape, an oval shape, a semicircular shape or a rectangular shape. Here, the conductive layer is made of a material with conductive performance, such as a silver layer, a copper layer, a copper alloy layer, etc.

[0103] Optionally, the first low-voltage terminal 101 and / or the second low-voltage terminal 102 can be formed by plating a conductive layer directly on the substrate 10, or can be formed by arranging a conductive layer in the first slot 11 (as shown in the figure) formed on the substrate 10.

[0104] Figure 4

[0105] ​​​Optionally, the first slot 11 is flush with the lower side of the substrate 10. Optionally, the first slot 11 is rectangular, oval, semicircular, or other shape. In this embodiment, the first slot 11 is rectangular.

[0106] Further, the terminals selected between the first low-voltage terminal 101 and the second low-voltage terminal 102 are not the same. In other words, if the first low-voltage terminal 101 is the enable terminal 101a, then the second low-voltage terminal 102 is a terminal other than the enable terminal 101a, such as the clock terminal 101b, the ground terminal 101c, the data terminal 101d, or the power terminal 101e; if the first low-voltage terminal 101 is the data terminal 101d, then the second low-voltage terminal 102 is a terminal other than the data terminal 101d, such as the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, or the power terminal 101e, and so on. It can be understood that, through the above arrangement, the first conductive lead 31 and the second conductive lead 32 can be connected to different terminals, respectively, thereby improving the voltage reduction / voltage division effect.

[0107] Optionally, the substrate 10 is provided with the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d, and the power terminal 101e, and the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d, and the power terminal 101e are arranged in an array. The detection terminal 22 is connected to the ground terminal 101c through a connection resistor, so that the detection terminal 22 is grounded through the ground terminal 101c to release some abnormal large current on the detection terminal 22 through the ground terminal 101c, thereby protecting the consumable chip 100 from being burned out by the large current. The data terminal 101d is used for data transmission with an external printing device, and the power terminal 101e is used for power supply for the consumable chip 100.

[0108] In this embodiment, as shown in FIG. 1, the enable terminal 101a and the clock terminal 101b are arranged side by side; the ground terminal 101c, the data terminal 101d, and the power terminal 101e are arranged side by side. Of course, in other embodiments, the arrangement of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d, and the power terminal 101e can be arranged according to the overall design of the actual consumable chip 100, and will not be described here. The same or similar arrangement is within the scope of the present embodiment. Figure 4 As shown in FIG. 1, the enable terminal 101a and the clock terminal 101b are arranged side by side; the ground terminal 101c, the data terminal 101d, and the power terminal 101e are arranged side by side. Of course, in other embodiments, the arrangement of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d, and the power terminal 101e can be arranged according to the overall design of the actual consumable chip 100, and will not be described here. The same or similar arrangement is within the scope of the present embodiment.

[0109] Figure 7 ​As shown, the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and the power terminal 101e can all be formed by a conductive layer coated on the substrate 10. The shapes of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and the power terminal 101e are not limited, and can be a waist hole shape, a circular shape, a semicircular shape, an oval shape or a rectangular shape, etc.

[0110] In an embodiment, as an example, the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and the power terminal 101e are all set to a waist hole shape. In another embodiment, as shown, Figure 4 the enable terminal 101a and the clock terminal 101b are set to a waist hole shape, and at least one of the ground terminal 101c, the data terminal 101d or the power terminal 101e can be formed by the first notch 11 opened on the substrate 10 and the conductive layer arranged in the first notch 11 opened on the substrate 10.

[0111] As shown, Figure 7 In the present embodiment, the number of high-voltage terminals 21 and detection terminals 22 is two groups, and the two groups of terminals are arranged on the substrate 10 at intervals, and the high-voltage terminals 21 in the two groups are electrically connected, so that the two high-voltage terminals 21 respectively form a detection loop with the corresponding high-voltage contact pins on the printing device side abutting, so that the printing device can realize installation detection of the high-voltage terminals 21. The detection terminals 22 in the two groups are electrically connected, so that the two detection terminals 22 respectively form a detection loop with the corresponding detection contact pins on the printing device side abutting, so that the printing device can realize installation detection of the detection terminals 22.

[0112] As an option, a resistor R1 or a sensor is arranged between the two high-voltage terminals 21, the resistor R1 is used for installation detection, that is, the installation detection part on the printing device judges the installation state of the high-voltage terminal 21 and the corresponding contact pin of the printing device according to the corresponding current value or voltage value detected by the resistor R1. The sensor can detect the ink amount of the consumable cartridge.

[0113] Further, as shown, Figure 9 the substrate 10 is provided with a second notch 12, and the second notch 12 has a plurality of side walls, at least one of which is plated with a conductive layer to form a high-voltage terminal 21 on the substrate 10. Of course, in other embodiments, the high-voltage terminal 21 can also be directly plated with a conductive layer on the substrate 10 to form directly.

[0114] As an option, the second notch 12 is a right-angle notch, i.e. is set in a rectangular shape, the high-voltage contact pin contacts the long-side wall of the right-angle notch, and the printing device and the consumable chip 100 are in communication; wherein the right-angle notch has a long-side wall and a short-side wall, the long-side wall is provided with a conductive layer and forms the high-voltage terminal 21, the right-angle notch can be plated with copper on the long-side wall, the short-side wall is not plated with copper, and the short-side wall only serves as a limiting function, effectively limiting the movement of the high-voltage contact pin, avoiding poor contact between the high-voltage contact pin and the corresponding high-voltage terminal 21 or avoiding short-circuiting between the high-voltage contact pin and other low-voltage terminals 100a, which can damage the consumable chip 100.

[0115] As an option, as shown in Figure 8 , the consumable chip 100 further comprises a memory 104, which can be arranged on the second surface of the substrate 10, for storing information related to the ink cartridge, two resistors R2 are connected in series between the two detection terminals 22, and then connected in parallel with the resistor R3 and connected to the ground terminal 101c, the memory 104 is electrically connected to the ground terminal 101c, and then the detection terminals 22 are electrically connected to the memory 104.

[0116] Further, as shown in Figure 8 , a third notch 13 is formed on the substrate 10, and a conductive layer is arranged in the third notch 13, and the detection pin contacts the conductive layer in the third notch 13 to realize data communication / electric connection.

[0117] As an option, the conductive layer is plated on the groove wall of the third notch 13, thereby forming the above-mentioned detection terminal 22 on the substrate 10.

[0118] Optionally, the third notch 13 can be a semicircular groove, a rectangular groove or set in other forms. The groove bottom of the third notch 13 can be a plane or a curved surface, as long as it can fix the detection pin. The third notch 13 is provided with a conductive layer, and the third notch 13 is used to electrically contact and fix the detection pin, preventing the signal detection pin from shaking.

[0119] As an option, as shown in Figure 8 , along the length direction of the substrate 10 (i.e. the x direction in Figure 4 , a fourth notch 14 is formed on the substrate 10, the third notch 13 is arranged on the side wall of the fourth notch 14, and the notch of the third notch 13 is arranged flush with the side wall of the fourth notch 14. It can be understood that the arrangement of the fourth notch 14 is beneficial to the drainage of the ink, thereby providing further protection against short-circuiting between the high-voltage terminal 21 and the detection terminal 22.

[0120] As shown in Figure 4As shown, the first conductive lead 31 includes a third connecting segment 311 and a third blocking segment 312, one end of the third connecting segment 311 is electrically connected to the first low-voltage terminal 101, the third blocking segment 312 is connected with the third connecting segment 311, and the other end of the third blocking segment 312 extends to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group, thereby forming a first double protection. The second conductive lead 32 includes a fourth connecting segment 321 and a fourth blocking segment 322, one end of the fourth connecting segment 321 is electrically connected to the second low-voltage terminal 102, the fourth blocking segment 322 is connected with the fourth connecting segment 321, and the other end of the fourth blocking segment 322 extends to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group and is spaced apart from the third blocking segment 312, thereby forming a second double protection, and the double protection can effectively ensure the voltage division and voltage reduction of the high voltage on the side of the high-voltage terminal 21, and better protect the detection terminal 22. Further, the first conductive lead 31 and the second conductive lead 32 are spaced apart and located between the high-voltage terminal 21 and the detection terminal 22; wherein the first conductive lead 31 is arranged closer to the detection terminal 22 relative to the second conductive lead 32; or the second conductive lead 32 is arranged closer to the detection terminal 22 relative to the first conductive lead 31. In other words, as an option, the third blocking segment 312 and the fourth blocking segment 322 are spaced apart, wherein the third blocking segment 312 is arranged closer to the detection terminal 22 relative to the fourth blocking segment 322; or the fourth blocking segment 322 is arranged closer to the detection terminal 22 relative to the third blocking segment 312. That is, the third blocking segment 312 and the fourth blocking segment 322 are arranged in a stacked manner, so that the voltage division and voltage reduction of the high voltage on the side of the high-voltage terminal 21 can be fully realized.

[0121] As an option, in an embodiment, the number of first conductive leads 31 is at least two; and / or the number of second conductive leads 32 is at least two; wherein the at least two first conductive leads 31 are connected to the same first low-voltage terminal 101, or are respectively connected to different first low-voltage terminals 101; the at least two second conductive leads 32 are connected to the same second low-voltage terminal 102, or are respectively connected to different second low-voltage terminals 102. Of course, in another embodiment, the number of first conductive leads 31 can also be one, and the number of second conductive leads 32 can also be one. Alternatively, the number of first conductive leads 31 is two, and the number of second conductive leads 32 can also be one; or the number of first conductive leads 31 is one, and the number of second conductive leads 32 can also be two, etc. It can be understood that the number of first conductive leads 31 and second conductive leads 32 can be selected according to specific design, and can refer to the description in embodiments 1-12.

[0122] Embodiment 1

[0123] As Figure 7 ,Figure 8 、 Figure 8 As shown in FIG. 2, the high-voltage terminals 21 and the detection terminals 22 are arranged in two groups, the first conductive lead 31 includes a third connecting segment 311 and a third blocking segment 312, one end of the third connecting segment 311 is electrically connected to the first low-voltage terminal 101, the third blocking segment 312 is connected to the third connecting segment 311, and both ends of the third blocking segment 312 correspond to a group of terminals respectively, and both ends of the third blocking segment 312 extend to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group respectively. The second conductive lead 32 includes a fourth connecting segment 321 and a fourth blocking segment 322, one end of the fourth connecting segment 321 is electrically connected to the second low-voltage terminal 102, the fourth blocking segment 322 is connected to the fourth connecting segment 321, and both ends of the fourth blocking segment 322 correspond to a group of terminals respectively, and both ends of the fourth blocking segment 322 extend to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group respectively.

[0124] Optionally, the first low-voltage terminal 101 is a data terminal 101d or a power terminal 101e, and the second low-voltage terminal 102 is an enable terminal 101a or a clock terminal 101b. In addition, in a group of terminals, the third blocking segment 312 and the fourth blocking segment 322 are arranged between the high-voltage terminal 21 and the detection terminal 22 to effectively form double blocking, so that when the consumable chip 100 is short-circuited, the voltage on the high-voltage terminal 21 is guided to the data terminal 101d or the power terminal 101e by the third blocking segment 312, and is guided to the enable terminal 101a or the clock terminal 101b by the fourth blocking segment 322 respectively to divide the voltage, so as to reduce the voltage signal accepted by the detection terminal 22, thereby achieving the protection.

[0125] Optionally, the first low-voltage terminal 101 is a power terminal 101e, and the second low-voltage terminal 102 is an enable terminal 101a. It can be understood that the power terminal 101e and the enable terminal 101a are arranged in different regions of the substrate 10. In this way, the layout of the entire consumable chip 100 is compact and reasonable, and the wiring of the first conductive lead 31 and the second conductive lead 32 is facilitated, and the length of the first conductive lead 31 and the second conductive lead 32 is effectively reduced, thereby saving costs.

[0126] Further, in the embodiment, the third blocking segment 312 and the fourth blocking segment 322 are arranged in parallel, and are both arranged in a straight line segment, that is, the straight line-shaped conductive layer is plated on the substrate 10 to form. Of course, the third blocking segment 312 and the fourth blocking segment 322 can also be formed in a shape other than a straight line, and can also be formed in any shape such as a curve, a polyline, etc. according to requirements.

[0127] Further, in the embodiment, the third blocking segment 312 and the fourth blocking segment 322 are arranged along the width direction of the substrate 10 (i.e. the direction perpendicular to the length direction of the substrate 10 as shown in FIG. 2), and the third blocking segment 312 and the fourth blocking segment 322 are arranged in parallel. Figure 10y direction in the y direction), the fourth blocking segment 322 and the third blocking segment 312 are stacked in the y direction; wherein, x and y are arranged perpendicularly, and the fourth blocking segment 322 is arranged relative to the third blocking segment 312 close to the detection terminal 22.

[0128] Optionally, a T-shape is formed between the third connecting segment 311 and the third blocking segment 312, and a T-shape is formed between the fourth connecting segment 321 and the fourth blocking segment 322. That is, the first conductive lead 31 is configured in a T-shape, and the second conductive lead 32 is configured in a T-shape. Of course, in other embodiments, the first conductive lead 31 and the second conductive lead 32 can also be configured in other shapes, which are not limited here.

[0129] Furthermore, in this embodiment, the number of the first conductive lead 31 is set to one, and the number of the second conductive lead 32 is also set to one.

[0130] Example 2

[0131] like Figure 11 As shown, the structure of Example 2 is basically the same as that of Example 1, and the same parts are not repeated here. The difference is that: there are two first conductive leads 31, one end of which is connected to the power terminal 101e, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in one group of terminals; one end of the other first conductive lead 31 is also connected to the power terminal 101e, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in the other group of terminals.

[0132] Alternatively, in this embodiment, the two first conductive leads 31 are both arranged in an L shape, and the number of the second conductive lead 32 is one and arranged in a T shape.

[0133] Example 3

[0134] like Figure 12 As shown, the structure of Example 3 is basically the same as that of Example 1, and the same parts are not repeated here. The difference is that: there are two second conductive leads 32, one end of which is connected to the enable terminal 101a, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in one group of terminals; one end of the other second conductive lead 32 is also connected to the enable terminal 101a, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in the other group of terminals.

[0135] Alternatively, in this embodiment, the number of the first conductive lead 31 is one and is arranged in a T-shaped structure, and the second conductive lead 32 is arranged in an L-shape.

[0136] Example 4

[0137] like Figure 13As shown, the structure of Example 4 is basically the same as that of Example 3, and the same parts are not repeated here. The difference is that: there are two second conductive leads 32, one end of which is connected to the enable terminal 101a, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in one group of terminals; one end of the other second conductive lead 32 is connected to the clock terminal 101b, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in the other group of terminals.

[0138] Alternatively, in this embodiment, the number of the first conductive lead 31 is one and is arranged in a T-shaped structure, and the second conductive lead 32 is arranged in an L-shape.

[0139] Example 5

[0140] like Figure 13 As shown, the structure of Example 5 is basically the same as that of Example 1, and the same parts are not repeated here. The difference is that: in this embodiment, the consumable chip 100 also includes a third low-voltage terminal 103, and the conductive lead 30 also includes a third conductive lead 33; wherein, the first conductive lead 31 includes a third connecting segment 311 and a third blocking segment 312, one end of the third connecting segment 311 is electrically connected to the first low-voltage terminal 101, the third blocking segment 312 is connected to the third connecting segment 311, and the two ends of the third blocking segment 312 correspond to a group of terminals respectively, and the two ends of the third blocking segment 312 extend respectively to between the high-voltage terminal 21 and the detection terminal 22 in each group; one end of the second conductive lead 32 is electrically connected to the second low-voltage terminal 102, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in one group of terminals; one end of the third conductive lead 33 is electrically connected to the third low-voltage terminal 103, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the other group of terminals.

[0141] Optionally, the third low-voltage terminal 103 includes any one of an enable terminal 101 a , a clock terminal 101 b , a ground terminal 101 c , a data terminal 101 d , and a power terminal 101 e .

[0142] Further, the selected terminals among the first low voltage terminal 101, the second low voltage terminal 102 and the third low voltage terminal 103 are not coincident. In other words, the first low voltage terminal 101, the second low voltage terminal 102 and the third low voltage terminal 103 are different terminals on the substrate 10. For example, the first low voltage terminal 101 is an enable terminal 101a, the second low voltage terminal 102 is a clock terminal 101b, and the third low voltage terminal 103 is a terminal other than the enable terminal 101a and the clock terminal 101b, such as a ground terminal 101c, a data terminal 101d or a power terminal 101e. For another example, the first low voltage terminal 101 is the ground terminal 101c, the second low voltage terminal 102 is the power terminal 101e, and the third low voltage terminal 103 is a terminal other than the ground terminal 101c and the power terminal 101e, such as the enable terminal 101a, the clock terminal 101b or the data terminal 101d. The above are two examples, and other types of cases are not listed here. Different variations still belong to the scope of the application.

[0143] Specifically, in an embodiment, continuing to refer to Figure 13 , the third low voltage terminal 103 is the data terminal 101d, the first low voltage terminal 101 is the ground terminal 101c, and the second low voltage terminal 102 is the power terminal 101e. That is, the third connection segment 311 is connected to the ground terminal 101c, the third barrier segment 312 extends away from one end of the third connection segment 311 to between the high voltage terminal 21 and the detection terminal 22 in each group, one end of the second conductive lead 32 is electrically connected to the power terminal 101e, and the other end extends to between the high voltage terminal 21 and the detection terminal 22 in one of the groups, one end of the third conductive lead 33 is electrically connected to the data terminal 101d, and the other end extends to between the high voltage terminal 21 and the detection terminal 22 in the other group.

[0144] Further, in the embodiment, the fourth barrier segment 322 and the third barrier segment 312 are arranged in a stacked manner in the y direction (as shown in Figure 13 , where x and y are arranged vertically, and the third barrier segment 312 is arranged closer to the detection terminal 22 than the fourth barrier segment 322. At the same time, the first conductive lead 31 is also arranged closer to the detection terminal 22 than the third conductive lead 33. In this way, when the consumable chip 100 has a short circuit, the high voltage on the high voltage terminal 21 is first divided by the second conductive lead 32 or the third conductive lead 33, and then grounded and reduced in voltage by the first conductive lead 31, so that the detection terminal 22 no longer receives a high voltage, i.e., the protection of the detection terminal 22 is achieved.

[0145] As an option, as shown in Figure 14As shown, the third connecting segment 311 and the third blocking segment 312 form a T-shaped structure, i.e., the first conductive lead 31 is arranged in a T-shaped structure. The second conductive lead 32 is arranged in an L-shaped structure, and the third conductive lead 33 is also arranged in an L-shaped structure, and the third conductive lead 33 is symmetrically arranged with the second conductive lead 32 with the ground terminal 101c as the symmetric point.

[0146] In the present embodiment, the number of the first conductive lead 31, the second conductive lead 32 and the third conductive lead 33 is each set to one.

[0147] Embodiment 6

[0148] As shown, the structure of Embodiment 6 is basically the same as that of Embodiment 5, and the same parts will not be described here again. The difference is that: Figure 15 The number of the first conductive lead 31 is two, one end of one of the first conductive leads 31 is connected to the ground terminal 101c, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in one of the groups of terminals; one end of the other first conductive lead 31 is also connected to the ground terminal 101c, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the other group of terminals.

[0149] Among them, the first conductive lead 31 is arranged in an L-shaped structure, the second conductive lead 32 is arranged in an L-shaped structure, and the third conductive lead 33 is also arranged in an L-shaped structure.

[0150] Embodiment 7

[0151] As shown, the structure of Embodiment 7 is basically the same as that of Embodiment 2, and the same parts will not be described here again. The difference is that: the two ends of the third blocking segment 312 correspond to a group of terminals respectively, and the two ends of the third blocking segment 312 extend between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group. One end of the third blocking segment 312 is connected to the third connecting segment 311, and the third connecting segment 311 is connected to the first low-voltage terminal 101. The fourth blocking segment 322 corresponds to a group of terminals, one end of the fourth blocking segment 322 is connected to the fourth connecting segment 321, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group of terminals. One end of the fourth blocking segment 322 is connected to the fourth connecting segment 321, and the fourth connecting segment 321 is connected to the second low-voltage terminal 102. That is, it can be understood that the first conductive lead 31 and the second conductive lead 32 are arranged between one group of terminals, and the first conductive lead 31 is arranged between the other group of terminals. Here, the first low-voltage terminal 101 and the second low-voltage terminal 102 can be any one of the enable terminal 101a, the clock terminal 101b, the data terminal 101d, the power terminal 101e or the ground terminal 101c.

[0152] Figure 16

[0153] ​​Alternatively, one end of the third connecting segment 311 is electrically connected to the ground terminal 101c, meaning that the first conductive lead 31 is connected to the ground terminal 101c, and the second conductive lead 32 is connected to terminals other than the ground terminal 101c, such as the enable terminal 101a, the clock terminal 101b, the data terminal 101d, and the power terminal 101e. Furthermore, the third blocking segment 312 is closer to the detection terminal 22 than the fourth blocking segment 322. Thus, in one terminal group having the first conductive lead 31 and the second conductive lead 32, when a short circuit occurs between the high-voltage terminal 21 and the detection terminal 22, the voltage is first divided by the first blocking segment 322 and then reduced by the blocking segment 312, thereby achieving dual protection. In the other terminal group, the voltage is directly reduced by the blocking segment 312.

[0154] Optionally, the first conductive lead 31 is configured as a T-shaped structure, and the second conductive lead 32 is configured as an L-shaped structure.

[0155] Example 8

[0156] like Figure 17 As shown, the structure of Example 8 is substantially the same as that of Example 2, and the identical parts are not further described here. The difference lies in that the two ends of the fourth blocking segment 322 correspond to a group of terminals, and the two ends of the fourth blocking segment 322 extend between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group of terminals. That is, one end of the fourth blocking segment 322 is connected to the fourth connecting segment 321, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group of terminals. The fourth connecting segment 321 is connected to the fifth low-voltage terminal 102. The third blocking segment 312 corresponds to a group of terminals. One end of the third blocking segment 312 is connected to the third connecting segment 311, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in one group of terminals. The third connecting segment 311 is connected to the first low-voltage terminal 101. In other words, it can be understood that the first conductive lead 31 and the second conductive lead 32 are provided between one group of terminals, and the second conductive lead 32 is provided in the other group of terminals. Here, the first low-voltage terminal 101 and the second low-voltage terminal 102 may be any one of the enable terminal 101 a , the clock terminal 101 b , the data terminal 101 d , the power terminal 101 e , or the ground terminal 101 c .

[0157] In this embodiment, the first low-voltage terminal 101 is a power terminal 101e, and the second low-voltage terminal 102 is an enable terminal 101a. The first conductive lead 31 is configured as an L-shaped structure, and the second conductive lead 32 is configured as a T-shaped structure.

[0158] Example 9

[0159] like Figure 17As shown, the structure of the embodiment 9 is basically the same as that of the embodiment 1, and the same parts are not repeated here, and the difference is that in the present embodiment, the consumable chip 100 further comprises a third low-voltage terminal 103 and a fourth low-voltage terminal 105, and the conductive lead 30 further comprises a third conductive lead 33 and a fourth conductive lead 34; here in order to facilitate the description of the relationship between each conductive lead and each low-voltage terminal, the two groups of terminals are defined as the first group and the second group.

[0160] Specifically, one end of the first conductive lead 31 is electrically connected to the first low-voltage terminal 101, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the first group; one end of the second conductive lead 32 is electrically connected to the second low-voltage terminal 102, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the first group; one end of the third conductive lead 33 is electrically connected to the third low-voltage terminal 103, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the second group; one end of the fourth conductive lead 34 is electrically connected to the fourth low-voltage terminal 105, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the second group. In this way, double protection is formed between the two groups of terminals respectively.

[0161] Optionally, the third low-voltage terminal 103 comprises any one of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and the power terminal 101e; the fourth low-voltage terminal 105 comprises any one of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and the power terminal 101e.

[0162] Further, the selected terminals between the first low-voltage terminal 101, the second low-voltage terminal 102, the third low-voltage terminal 103 and the fourth low-voltage terminal 105 do not coincide. In other words, the first low-voltage terminal 101, the second low-voltage terminal 102, the third low-voltage terminal 103 and the fourth low-voltage terminal 105 are different terminals on the substrate 10 respectively. For example, the first low-voltage terminal 101 is the enable terminal 101a, the second low-voltage terminal 102 is the clock terminal 101b, and the third low-voltage terminal 103 is the data terminal 101d, and then the fourth low-voltage terminal 105 is the terminal other than the enable terminal 101a, the clock terminal 101b and the data terminal 101d, such as the ground terminal 101c or the power terminal 101e. It can be understood that the above terminal selection can be selected according to the actual situation, and the simple and reasonable layout is included in the present application.

[0163] Specifically, as shown in the embodiment 9, Figure 18As shown, for a compact and rational layout, in this embodiment, the first low-voltage terminal 101 is a power terminal 101e, the second low-voltage terminal 102 is an enable terminal 101a, the third low-voltage terminal 103 is a data terminal 101d, and the fourth low-voltage terminal 105 is a clock terminal 101b. Thus, because the enable terminal 101a and the clock terminal 101b are located in the same area of ​​the substrate, the power terminal 101e and the data terminal 101d are also located in the same area of ​​the substrate, and the first conductive lead 31 and the second conductive lead 32 correspond to the first group, and the third conductive lead 33 and the fourth conductive lead 34 correspond to the second group, the above arrangement not only makes the extension path of the conductive leads the shortest and most optimal, but also makes the layout more compact and rational.

[0164] Alternatively, in this embodiment, the first conductive lead 31 , the second conductive lead 32 , the third conductive lead 33 and the fourth conductive lead 34 have the same shape and are all arranged in an L-shaped structure.

[0165] Example 10

[0166] like Figure 19 As shown, the structure of Example 10 is basically the same as that of Example 7, and the same parts are not repeated here. The difference is that the consumable chip includes a third blocking section 312, the two ends of which correspond to a group of terminals, and the two ends of the third blocking section 312 extend between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group. One end of the third blocking section 312 is connected to the third connecting section 311, and the third connecting section 311 is connected to the first low-voltage terminal 101. The fourth blocking section 322 and the fourth connecting section 321 are not provided. In other words, it can be understood that a first conductive lead 31 is provided between one group of terminals, and a first conductive lead 31 is also provided between the other group of terminals. Here, the first low-voltage terminal 101 can be any one of the enable terminal 101a, the clock terminal 101b, the data terminal 101d, the power terminal 101e, or the ground terminal 101c.

[0167] Alternatively, one end of the connecting section 311 is electrically connected to the ground terminal 101c, that is, the first conductive lead 31 is connected to the ground terminal 101c. Thus, in a group of terminals having the first conductive lead 31, when a short circuit occurs between the high-voltage terminal 21 and the detection terminal 22, the blocking section 312 can reduce the voltage, thereby achieving short-circuit protection.

[0168] Optionally, the first conductive lead 31 is configured as a T-shaped structure.

[0169] Example 11

[0170] like Figure 20As shown, the structure of Example 11 is basically the same as that of Example 10, and the same parts are not repeated here. The difference is that: there are two first conductive leads 31, one end of which is connected to the ground terminal 101c, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in one group of terminals; one end of the other first conductive lead 31 is also connected to the ground terminal 101c, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in the other group of terminals.

[0171] The first conductive lead 31 is configured to be L-shaped.

[0172] Example 12

[0173] like Figure 21 and Figure 22 As shown, the structure of Example 12 is similar to that of Example 10 and Example 11, and the same parts are not repeated here. The difference is that the area occupied by each terminal on the substrate 10 is larger than the terminal area in Example 10 and Example 11, which is beneficial to improving the connection stability between the contact pins on the printer side and the chip terminals.

[0174] It should be noted that although conductive leads 30 are used in all of the above embodiments, the present application is not limited to the specific composition of the conductive structure 3, such as metal leads. Lead structures composed of other materials with conductive functions can be used to replace the conductive leads 30, such as alloys, conductive rubbers, conductive plastics, polymer conductive materials, etc.

[0175] The present application also provides a method for manufacturing a consumable chip, which is used to prepare the above-mentioned consumable chip.

[0176] like ​ As shown, the manufacturing method of the consumable chip includes the following steps: arranging a memory 104, at least one low-voltage terminal 100a electrically connected to the memory 104, at least one high-voltage terminal 21 and at least one detection terminal 22 on a substrate 10, wherein the high-voltage terminal 21 and the detection terminal 22 are spaced apart;

[0177] A conductive structure 3 is arranged on the substrate 10 , one end of the conductive structure 3 is electrically connected to the low voltage terminal 100 a , and the other end of the conductive structure 3 is extended between the high voltage terminal 21 and the detection terminal 22 .

[0178] In one embodiment, the number of the high voltage terminals 21 and the detection terminals 22 is two, and the method further includes:

[0179] Two sets of terminals are spaced apart on the substrate 10;

[0180] The at least one low-voltage terminal 100a is connected to the at least one conductive structure 3, one end of the conductive structure 3 is electrically connected to the low-voltage terminal 100a, and the other end extends between the at least one set of high-voltage terminals 21 and the detection terminal 22.

[0181] In one embodiment, the method further comprises:

[0182] At least two conductive structures 3 are arranged between each set of high-voltage terminals 21 and detection terminals 22; or

[0183] One conductive structure 3 is arranged between one set of high-voltage terminals 21 and detection terminals 22, and at least two conductive structures 3 are arranged between another set of high-voltage terminals 21 and detection terminals 22.

[0184] In one embodiment, the method further comprises: using a metal lead as the conductive structure 3.

[0185] In one embodiment, the method further comprises: arranging the conductive structure 3 as a T shape or an L shape.

[0186] In one embodiment, the method further comprises:

[0187] A first slot 11 is formed on the side wall of the substrate 10, a conductive layer is arranged in the first slot 11, and a low-voltage terminal 100a is formed; and / or

[0188] A second slot 12 is formed on the side wall of the substrate 10, a conductive layer is arranged in the second slot 12, and a high-voltage terminal 21 is formed; and / or

[0189] A third slot 13 and a fourth slot 14 are formed on the side wall of the substrate 10, the fourth slot 14 is formed along the length direction of the substrate 10, the third slot 13 is arranged on the side wall of the fourth slot 14, a conductive layer is arranged in the third slot 13, and a detection terminal 22 is formed.

[0190] In one embodiment, the method further comprises:

[0191] The second slot 12 is arranged as a right-angled slot having a long side wall and a short side wall, a conductive layer is arranged on the long side wall, and a high-voltage terminal 21 is formed.

[0192] In one embodiment, the conductive structure 3 includes a connecting segment 301 and a blocking segment 302, and the method further comprises: electrically connecting one end of the connecting segment 301 to the low-voltage terminal 100a, electrically connecting the other end of the connecting segment 301 to the blocking segment 302, and extending the blocking segment 302 between the high-voltage terminal 21 and the detection terminal 22.

[0193] In one embodiment, the number of high-voltage terminals 21 and detection terminals 22 is two sets;

[0194] The conductive structure 3 comprises conductive leads 30, which comprise connection segments 301 and barrier segments 302; the method further comprises:

[0195] Two groups of terminals are arranged on the substrate 10 at intervals;

[0196] One end of the connection segment 301 is electrically connected to at least one low-voltage terminal 100a, and the other end is connected to the barrier segment 302; the two ends of the barrier segment 302 correspond to a group of terminals respectively, and the two ends of the barrier segment 302 extend to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group respectively.

[0197] In one embodiment, the number of high-voltage terminals 21 and detection terminals 22 is two groups;

[0198] The conductive structure 3 comprises a plurality of conductive leads 30, and the method further comprises:

[0199] Two groups of terminals are arranged on the substrate 10 at intervals;

[0200] One end of at least one conductive lead 30 is electrically connected to at least one low-voltage terminal 100a, and the other end extends to between a group of high-voltage terminals 21 and detection terminals 22; one end of at least one conductive lead 30 is electrically connected to at least one low-voltage terminal 100a, and the other end extends to between another group of high-voltage terminals 21 and detection terminals 22.

[0201] In one embodiment, the conductive lead 30 extending to between a group of high-voltage terminals 21 and detection terminals 22 comprises a first connection segment 303 and a first barrier segment 304; the method further comprises:

[0202] One end of the first connection segment 303 is electrically connected to at least one low-voltage terminal 100a, and the other end is connected to the first barrier segment 304; the two ends of the first barrier segment 304 correspond to a group of terminals respectively, and the two ends of the first barrier segment 304 extend to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group respectively;

[0203] And / or,

[0204] The conductive lead 30 extending to between another group of high-voltage terminals 21 and detection terminals 22 comprises a second connection segment 305 and a second barrier segment 306; the method further comprises:

[0205] One end of the second connecting segment 305 is electrically connected with at least one low-voltage terminal 100a, and the other end is connected with the second barrier segment 306; both ends of the second barrier segment 306 correspond to a group of terminals respectively, and both ends of the second barrier segment 306 are extended to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group respectively.

[0206] In one embodiment, the at least one low-voltage terminal 100a includes a first low-voltage terminal 101 and a second low-voltage terminal 102 arranged at intervals, and the conductive structure 3 includes a first conductive lead 31 and a second conductive lead 32; the method further includes:

[0207] One end of the first conductive lead 31 is electrically connected with the first low-voltage terminal 101, and the other end is extended to between the high-voltage terminal 21 and the detection terminal 22; one end of the second conductive lead 32 is electrically connected with the second low-voltage terminal 102, and the other end is extended to between the high-voltage terminal 21 and the detection terminal 22 corresponding to the first conductive lead 31.

[0208] In one embodiment, the number of the high-voltage terminal 21 and the detection terminal 22 is two groups, the first conductive lead 31 includes a third connecting segment 311 and a third barrier segment 312, the second conductive lead 32 includes a fourth connecting segment 321 and a fourth barrier segment 322, and the method further includes:

[0209] The two groups of terminals are arranged at intervals on the substrate 10; one end of the third connecting segment 311 is electrically connected with the first low-voltage terminal 101, the third barrier segment 312 is connected with the third connecting segment 311, one end of the fourth connecting segment 321 is electrically connected with the second low-voltage terminal 102, and the fourth barrier segment 322 is connected with the fourth connecting segment 321;

[0210] Both ends of the third barrier segment 312 correspond to a group of terminals respectively, and both ends of the third barrier segment 312 are extended to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group respectively; or, the third barrier segment 312 corresponds to a group of terminals, one end of the third barrier segment 312 is connected with the third connecting segment 311, and the other end is extended to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group;

[0211] The two ends of the fourth barrier section 322 correspond to a group of terminals respectively, and the two ends of the fourth barrier section 322 extend to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group respectively; or the fourth barrier section 322 corresponds to a group of terminals, one end of the fourth barrier section 322 is connected with the fourth connecting section 321, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group.

[0212] In one embodiment, the number of the first conductive leads 31 is at least two; and / or the number of the second conductive leads 32 is at least two; the method further comprises:

[0213] The at least two first conductive leads 31 are connected to the same first low-voltage terminal 101, or are connected to different first low-voltage terminals 101 respectively;

[0214] The at least two second conductive leads 32 are connected to the same second low-voltage terminal 102, or are connected to different second low-voltage terminals 102 respectively.

[0215] In one embodiment, the number of the high-voltage terminals 21 and the detection terminals 22 is two groups; the consumable chip further comprises a third low-voltage terminal 103, and the conductive leads 30 further comprise a third conductive lead 33; the first conductive leads 31 comprise a third connecting section 311 and a third barrier section 312; the method further comprises:

[0216] The two groups of terminals are arranged on the substrate 10 at intervals; one end of the third connecting section 311 is electrically connected with the first low-voltage terminal 101, the third barrier section 312 is connected with the third connecting section 311, the two ends of the third barrier section 312 correspond to a group of terminals respectively, and the two ends of the third barrier section 312 extend to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group respectively;

[0217] One end of the second conductive lead 32 is electrically connected with the second low-voltage terminal 102, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in one of the groups;

[0218] One end of the third conductive lead 33 is electrically connected with the third low-voltage terminal 103, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in the other group.

[0219] In one embodiment, the number of the high-voltage terminals 21 and the detection terminals 22 is two groups, the consumable chip further comprises a third low-voltage terminal 103, the conductive leads 30 further comprise a third conductive lead 33, and the number of the first conductive leads 31 is two; the method further comprises:

[0220] two groups of terminals are arranged on the substrate 10 at intervals;

[0221] one end of one of the first conductive leads 31 is connected to the first low-voltage terminal 101, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group of terminals; one end of the other first conductive lead 31 is connected to the first low-voltage terminal 101, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group of terminals;

[0222] one end of the second conductive lead 32 is electrically connected to the second low-voltage terminal 102, and the other end extends between one of the high-voltage terminals 21 and the detection terminal 22;

[0223] one end of the third conductive lead 33 is electrically connected to the third low-voltage terminal 103, and the other end extends between the other high-voltage terminal 21 and the detection terminal 22.

[0224] In one embodiment, the number of high-voltage terminals 21 and detection terminals 22 is two groups, and the consumable chip further includes a third low-voltage terminal 103 and a fourth low-voltage terminal 105, and the conductive leads 30 further include a third conductive lead 33 and a fourth conductive lead 34; the method further includes:

[0225] two groups of terminals are arranged on the substrate 10 at intervals;

[0226] one end of the first conductive lead 31 is electrically connected to the first low-voltage terminal 101, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group of terminals; one end of the second conductive lead 32 is electrically connected to the second low-voltage terminal 102, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group of terminals corresponding to the first conductive lead 31.

[0227] one end of the third conductive lead 33 is electrically connected to the third low-voltage terminal 103, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the other group of terminals; one end of the fourth conductive lead 34 is electrically connected to the fourth low-voltage terminal 105, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the other group of terminals corresponding to the third conductive lead 33.

[0228] In one embodiment, the method further includes: arranging the first conductive lead 31 in a T-shaped structure or an L-shaped structure; and / or, arranging the second conductive lead 32 in a T-shaped structure or an L-shaped structure.

[0229] In one embodiment, the method further comprises: spacing the first conductive lead 31 and the second conductive lead 32 between the high-voltage terminal 21 and the detection terminal 22;

[0230] The first conductive lead 31 is arranged closer to the detection terminal 22 than the second conductive lead 32, or the second conductive lead 32 is arranged closer to the detection terminal 22 than the first conductive lead 31.

[0231] In one embodiment, the first low-voltage terminal 101 is any one of an enable terminal 101a, a clock terminal 101b, a ground terminal 101c, a data terminal 101d, and a power terminal 101e.

[0232] And / or, the second low-voltage terminal 102 is any one of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d, and the power terminal 101e.

[0233] In one embodiment, the first low-voltage terminal 101 is the ground terminal 101c, and the second low-voltage terminal 102 is any one of the enable terminal 101a, the clock terminal 101b, the data terminal 101d, and the power terminal 101e.

[0234] In one embodiment, the method further comprises: forming a first slot 11 on the substrate 10, and forming at least one of the ground terminal 101c, the data terminal 101d, and the power terminal 101e by arranging a conductive layer in the first slot 11.

[0235] And / or, the ground terminal 101c, the data terminal 101d, or the power terminal 101e is arranged side by side.

[0236] In one embodiment, the method further comprises: forming a second slot 12 on the sidewall of the substrate 10, the second slot 12 having a plurality of second slot walls, and forming the high-voltage terminal 21 by arranging a conductive layer on at least one of the second slot walls.

[0237] And / or, forming a third slot 13 on the sidewall of the substrate 10, and forming the detection terminal 22 by arranging a conductive layer in the third slot 13.

[0238] The manufacturing method of the consumable chip according to the embodiments of the present application corresponds to the consumable chip, and the technical features and advantages of the embodiments of the consumable chip are applicable to the embodiments of the manufacturing method of the consumable chip. The steps of the manufacturing method of the consumable chip can be combined arbitrarily, and there is no sequence.

[0239] Any technical features of the above embodiments can be combined, and for the sake of brevity, not all possible combinations are described, however, any combination of the technical features is considered to be within the scope of the present specification.

[0240] Those skilled in the art should know that the above embodiments are only used to illustrate the present application, but not as a limitation to the present application, and any suitable changes and modifications made to the above embodiments within the spirit and scope of the present application shall fall within the scope of the present application.

Claims

1. A consumable chip, comprising a memory, a substrate, at least one low-voltage terminal electrically connected to the memory, at least one high-voltage terminal, and at least one detection terminal disposed on the substrate, wherein the high-voltage terminal and the detection terminal are spaced apart, characterized in that, The high-voltage terminals and the detection terminals are two groups and are arranged at intervals, and a resistor or a sensor is arranged between the two high-voltage terminals; and the low-voltage terminal is any one of an enable terminal, a clock terminal, a ground terminal, a data terminal, and a power terminal. The consumable chip further comprises a conductive structure, one end of the conductive structure is electrically connected to the low-voltage terminal, and the other end of the conductive structure extends between the high-voltage terminal and the detection terminal, and the conductive structure is used to guide the high voltage on the high-voltage terminal to the corresponding low-voltage terminal when a short circuit occurs between the high-voltage terminal and the detection terminal, so that the low-voltage terminal divides and reduces the voltage of the high-voltage terminal.

2. The consumable chip of claim 1, wherein, The conductive structure comprises at least one conductive lead, and the conductive lead comprises a connecting segment and a blocking segment, one end of the connecting segment is electrically connected to at least one low-voltage terminal, the other end of the connecting segment is connected to the blocking segment, and the two ends of the blocking segment correspond to a group of high-voltage terminals and detection terminals respectively, and the two ends of the blocking segment extend to between the high-voltage terminal and the detection terminal in the corresponding group respectively.

3. The consumable chip of claim 2, wherein, The conductive lead is in a T shape or an L shape.

4. The consumable chip of claim 2, wherein, The conductive lead is a metal lead.

5. The consumable chip of claim 1, wherein, a first notch is formed in the sidewall of the substrate, and a conductive layer is arranged in the first notch to form the low-voltage terminal; and / or a second notch is formed in the sidewall of the substrate, and a conductive layer is arranged in the second notch to form the high-voltage terminal; and / or a third notch and a fourth notch are arranged in the sidewall of the substrate, the fourth notch is formed along the length direction of the substrate, and the third notch is arranged on the sidewall of the fourth notch, and a conductive layer is arranged in the third notch to form the detection terminal.

6. The consumable chip of claim 5, wherein, The second notch is a right-angle notch, which has a long-side sidewall and a short-side sidewall, and the long-side sidewall is provided with a conductive layer to form the high-voltage terminal.

7. The consumable chip of claim 1, wherein, The input voltage of the high-voltage terminal is higher than that of the detection terminal.

8. The consumable chip of claim 1, wherein, There are at least two conductive structures between the high-voltage terminals and the detection terminals in each group; or There is one conductive structure between the high-voltage terminals and the detection terminals in one group, and there are at least two conductive structures between the high-voltage terminals and the detection terminals in another group.

9. A consumable cartridge, characterized by, The consumable cartridge comprises a cartridge body and a consumable chip as claimed in any one of claims 1 to 8, and the consumable chip is arranged on the cartridge body.

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