Electronic package

By configuring dams at the edge of the encapsulation layer to limit the overflow of encapsulation material, the problem of unwetted solder balls caused by undercoat overflow is solved, achieving a stable connection and effective electrical connection of the semiconductor package and improving reliability.

CN223471594UActive Publication Date: 2025-10-24SILICONWARE PRECISION IND CO LTD
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Patent Information

Application Number
CN202422846612.4
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Priority Date
2024-11-14
Filing Date
2024-11-21
Publication Date
2025-10-24
Estimated Expiration
2034-11-21

AI Technical Summary

Technical Problem

Existing semiconductor packages are prone to overflow during the formation of the primer, resulting in unwetted solder balls, which affects the firm bonding and electrical connection with the circuit board, leading to poor reliability.

Method used

A dam is configured at the edge of the first surface of the encapsulation layer to limit the overflow range of the encapsulation material and prevent it from contacting the wiring structure. Electronic devices and wiring structures are connected by conductive bumps, and the conductive bumps are encapsulated with encapsulation material.

Benefits of technology

This effectively avoids the problem of unwetted conductive components, ensures that the package is firmly bonded to the support structure and achieves effective electrical connection, and improves the reliability of the product.

✦ Generated by Eureka AI based on patent content.

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Abstract

An electronic package is mainly characterized in that a dam body is formed at the edge of the electronic package to prevent a packaging material from overflowing to the lower part, so that the packaging material does not contact a conductive element below the packaging material, and the problem that the conductive element is not wetted during subsequent reflow soldering of the conductive element can be avoided.
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Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor packaging technology, and in particular to an electronic package with improved reliability. BACKGROUND

[0002] In order to ensure the continuous miniaturization and multi-functionality of electronic products and communication devices, semiconductor packaging needs to be developed towards miniaturization, multi-pin connection, high-speed operation and high functionality. For example, in advanced process packaging, common packaging types such as fan-out wiring process with embedded components, etc.

[0003] Figures 1A-1D A cross-sectional view of a conventional semiconductor package 1 manufacturing process.

[0004] As shown in Figure 1A , a full-surface semi-finished product 8 including a plurality of packaging modules 1a is provided on a carrier 9, wherein the packaging module 1a includes: a cladding layer 15, at least one semiconductor chip 11, a plurality of conductive pillars 13, a circuit structure 10, a wiring structure 14, and a plurality of solder balls 17.

[0005] As shown in Figure 1B , the full-surface semi-finished product 8 is subjected to a singulation process along a cutting path L as shown in Figure 1A to separate each of the packaging modules 1a.

[0006] As shown in Figure 1C , at least one electronic device 16 is disposed on the circuit structure 10 by a plurality of conductive bumps 160. Then, an underfill 18 is formed between the circuit structure 10 and the electronic device 16 to cover the conductive bumps 160.

[0007] As shown in Figure 1D , the carrier 9 is removed to obtain a semiconductor package 1. Then, the semiconductor package 1 is mounted on a circuit board 19 by reflowing the solder balls 17.

[0008] However, in the conventional semiconductor package 1 manufacturing process, when the underfill 18 is formed, the underfill 18 is prone to overflow, causing the underfill 18 to often overflow from the edge of the circuit structure 10 along the cladding layer 15 onto the wiring structure 14, as shown in Figure 1C , so that the underfill 18 contacts the solder balls 17, as shown in Figure 1D , and even covers the solder balls 17, so that when the solder balls 17 are reflowed subsequently, the solder balls 17 are prone to the problem of non-wetting, causing the semiconductor package 1 to not be stably bonded to the circuit board 19, and unable to effectively electrically connect the circuit board 19, or even fall off from the circuit board 19, resulting in problems such as poor product reliability.

[0009] Therefore, how to overcome the problems of the prior art has become a difficult problem to be solved in the industry. Utility model content

[0010] In view of the various deficiencies of the prior art, the present application provides an electronic package, comprising: a cladding layer having opposite first and second surfaces, and an edge of the first surface forming a dam; an electronic element embedded in the cladding layer; a circuit structure provided on the first surface of the cladding layer and externally exposed from the dam; a wiring structure provided on the second surface of the cladding layer; a plurality of conductive elements provided on the wiring structure; an electronic device provided on the circuit structure by a plurality of conductive bumps; and a packaging material formed between the circuit structure and the electronic device to cover the plurality of conductive bumps.

[0011] The present application also provides a method for manufacturing an electronic package, comprising: providing a whole-surface semi-finished product comprising a plurality of electronic modules, wherein each electronic module comprises: a cladding layer having opposite first and second surfaces, an electronic element embedded in the cladding layer, a circuit structure provided on the first surface of the cladding layer, a wiring structure provided on the second surface of the cladding layer, and a plurality of conductive elements provided on the wiring structure; removing the material of the circuit structure between each electronic module to expose the first surface of the cladding layer; forming a dam on the exposed first surface of the cladding layer between each electronic module; performing a singulation process on the whole-surface semi-finished product along a cutting path to separate each electronic module, so that the dam is formed at the edge of the first surface of the cladding layer; providing an electronic device on the circuit structure by a plurality of conductive bumps; and forming a packaging material between the circuit structure and the electronic device to cover the plurality of conductive bumps.

[0012] In the foregoing electronic package and method for manufacturing the same, the position of the dam corresponds to the cutting path. Alternatively, the position of the dam does not correspond to the cutting path.

[0013] In the foregoing electronic package and method for manufacturing the same, the dam is in the form of a step.

[0014] In the foregoing electronic package and method for manufacturing the same, the dam is in the form of a recess.

[0015] In the foregoing electronic package and method for manufacturing the same, the electronic element is electrically connected to the circuit structure.

[0016] In the foregoing electronic package and method for manufacturing the same, the electronic module further comprises a plurality of conductive pillars embedded in the cladding layer and electrically connected to the circuit structure and the wiring structure.

[0017] In the foregoing electronic package and method for manufacturing the same, the plurality of conductive elements are electrically connected to the wiring structure.

[0018] In the aforementioned electronic package and the manufacturing method thereof, the electronic device is electrically connected to the circuit structure through the plurality of conductive bumps.

[0019] In the aforementioned electronic package and the manufacturing method thereof, the encapsulation material is an underfill.

[0020] In the aforementioned electronic package and the manufacturing method thereof, the encapsulation material extends into the dam but does not extend into the circuit structure.

[0021] As can be seen from the above, the electronic package of the present application mainly configures a dam on the edge of the first surface of the encapsulation layer to limit the overflow range of the encapsulation material and stop the encapsulation material from overflowing onto the circuit structure, so that the encapsulation material does not contact the conductive element. Therefore, compared with the prior art, the electronic package of the present application can avoid the problem of non-wetting of the conductive element when the conductive element is reflowed subsequently, thereby improving the reliability of the product. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figures 1A-1D FIG. 1 is a cross-sectional view of a manufacturing method of a conventional semiconductor package.

[0023] Figures 2A-2E FIG. 2 is a cross-sectional view of a manufacturing method of an electronic package of the present application.

[0024] Figure 3 FIG. 3 is a cross-sectional view of another embodiment of the electronic package of the present application. Figure 2E

[0025] REFERENCE NUMERALS

[0026] 1 semiconductor package

[0027] 1a package module

[0028] 10, 20 circuit structure

[0029] 11 semiconductor chip

[0030] 13, 23 conductive pillar

[0031] 14, 24 circuit structure

[0032] 15, 25 encapsulation layer

[0033] 16, 26 electronic device

[0034] 160, 260 conductive bump

[0035] 17 solder ball

[0036] 18 underfill

[0037] 19 circuit board ​

[0038] 2 electronic package

[0039] 2a electronic module

[0040] 200 dielectric layer

[0041] 201 wiring layer

[0042] 21 electronic element

[0043] 210 adhesive layer

[0044] 22 electrically conductive body

[0045] 220 protective film

[0046] 240 insulating layer

[0047] 241 wiring layer

[0048] 25a first surface

[0049] 25b second surface

[0050] 27 electrically conductive element

[0051] 28 encapsulation material

[0052] 29, 39 dam

[0053] 290 recess

[0054] 291 hollow

[0055] 30 carrier structure

[0056] 8 full-face semi-finished product

[0057] 9 carrier

[0058] 90 release layer

[0059] 91 bonding layer

[0060] D, R width

[0061] L cutting path DETAILED DESCRIPTION

[0062] The present application is herein described, by way of example only, with the

[0063] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in this application without affecting the efficacy and purpose that can be achieved by this application. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of this application. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of this application without substantially changing the technical content.

[0064] Figures 2A-2E It is a cross-sectional schematic diagram of a method for manufacturing the electronic package 2 of the present application.

[0065] like Figure 2A As shown, a full-page semi-finished product 8 including multiple electronic modules 2a is provided on a carrier 9, wherein the electronic module 2a includes: a covering layer 25, at least one electronic component 21, multiple conductive columns 23, a circuit structure 20, a wiring structure 24 and multiple conductive elements 27.

[0066] In this embodiment, the carrier 9 is, for example, a plate made of a semiconductor material (such as silicon or glass), on which a release layer 90 and a bonding layer 91 made of, for example, an insulating material are sequentially formed by, for example, coating.

[0067] The coating layer 25 has a first surface 25 a and a second surface 25 b opposite to each other.

[0068] In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, or an encapsulant or molding compound such as epoxy. For example, the coating layer 25 can be formed using a liquid compound, injection, lamination, or compression molding.

[0069] The electronic component 21 is embedded in the coating layer 25, and the electrode pads of the electronic component 21 are combined and electrically connected to multiple conductors 22, wherein the electronic component 21 is an active component, a passive component or a combination of the two, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

[0070] In this embodiment, the electronic component 21 is a semiconductor chip, which is disposed on the wiring structure 24 through an adhesive layer 210, and is covered by a protective film 220 such as a passivation material, and the conductive body 22.

[0071] Further, the conductive body 22 is, for example, a conductive line, a spherical ball such as a solder ball, or a columnar body such as a copper column, a solder bump, or a stud conductive member made by a soldering machine, but is not limited thereto.

[0072] The conductive column 23 is embedded in the covering layer 25, and the material forming the conductive column 23 is a metal material such as copper or a solder material.

[0073] The wiring structure 20 is disposed on the first surface 25a of the covering layer 25 and electrically connects the conductive column 23 and the conductive body 22.

[0074] In this embodiment, the wiring structure 20 includes a plurality of dielectric layers 200 and a wiring layer 201 such as a redistribution layer (RDL) disposed on the dielectric layers 200, and the outermost dielectric layer 200 can be used as a solder resist layer, and the outermost wiring layer 201 is exposed to the solder resist layer to serve as an electrical contact pad. Alternatively, the wiring structure 20 can include only a single dielectric layer 200 and a single wiring layer 201.

[0075] Further, the material forming the wiring layer 201 is copper, and the material forming the dielectric layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP), or a solder resist material such as green paint or ink.

[0076] The wiring structure 24 is disposed on the second surface 25b of the covering layer 25 and electrically connects the conductive column 23.

[0077] In this embodiment, the wiring structure 24 includes an insulating layer 240 and a wiring layer 241 such as a redistribution layer (RDL) disposed on the insulating layer 240, and the outermost insulating layer 240 can be used as a solder resist layer, and the outermost wiring layer 241 is exposed to the solder resist layer to serve as an electrical contact pad.

[0078] Further, the material forming the wiring layer 241 is copper, and the material forming the insulating layer 240 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP), or a solder resist material such as green paint or ink.

[0079] The conductive element 27 is a solder ball or a metal bump such as a copper bump, which is disposed on the electrical contact pad of the wiring structure 24 and electrically connected to the wiring layer 241 .

[0080] In this embodiment, the entire semi-finished product 8 is disposed on the carrier 9 with one side of its wiring structure 24 , so that the conductive element 27 is embedded in the bonding layer 91 .

[0081] like Figure 2B As shown, the material of the circuit structure 20 between each electronic module 2a is removed to expose the first surface 25a of the cladding layer 25. A portion of the material on the exposed first surface 25a of the cladding layer 25 is also removed to form a recess 290 on the first surface 25a of the cladding layer 25, connecting the circuit structure 20 and the cladding layer 25. Next, a hollow portion 291 is formed on the bottom surface of the recess 290, penetrating the cladding layer 25 and the wiring structure 24. Furthermore, a stepped dam 29 is formed on the first surface 25a of the cladding layer 25 at the edge of each electronic module 2a.

[0082] In this embodiment, the width D of the concave portion 290 is greater than the width R of the hollow portion 291. For example, a tool with a wider cutting end is used to form the concave portion 290, and a tool with a narrower cutting end is used to form the hollow portion 291.

[0083] like Figure 2C As shown, along Figure 2B The cutting path L shown is used to singulate the entire semi-finished product 8 to separate the electronic modules 2a, so that the dam 29 is formed on the edge of the first surface 25a of the cladding layer 25. Then, at least one electronic device 26 is placed on the circuit structure 20 via a plurality of conductive bumps 260.

[0084] In this embodiment, the cutting path L corresponds to the position of the hollow portion 291 , so that the dam 29 is stepped.

[0085] The electronic device 26 is electrically connected to the electrical contact pads of the circuit layer 201 via a plurality of conductive bumps 260 such as solder bumps, copper bumps or other conductive bumps. For example, the electronic device 26 is an optical communication component such as a photonic integrated circuit component (PIC).

[0086] like Figure 2D As shown, a packaging material 28 such as an underfill is formed between the circuit structure 20 and the electronic device 26 to cover the conductive bumps 260 to obtain the electronic package 2 .

[0087] In this embodiment, the packaging material 28 extends into the dam 29 but does not extend onto the wiring structure 24 .

[0088] As shown in Figure 2E The carrier 9 and the release layer 90 and the bonding layer 91 thereon are removed to expose the conductive elements 27. Then, the electronic package 2 is mounted on a carrier structure 30 by reflowing the conductive elements 27.

[0089] In this embodiment, the carrier structure 30 is in the form of a substrate, such as a core layer or a coreless package substrate. Alternatively, the carrier structure 30 can be other board materials, such as a lead frame, a wafer, or other carrier boards with metal routing, without being limited to the above.

[0090] Therefore, the manufacturing method of the present application mainly uses the dam 29 on the edge of the first surface 25a of the encapsulation layer 25 to limit the overflow range of the encapsulation material 28 by the surface tension thereof to stop the encapsulation material 28 from overflowing onto the routing structure 24, so that the encapsulation material 28 does not contact the conductive elements 27. Compared with the prior art, the electronic package 2 of the present application can avoid the problem of non-wetting of the conductive elements 27 when reflowing the conductive elements 27 subsequently, so that the electronic package 2 can be stably bonded to the carrier structure 30 and effectively electrically connected to the carrier structure 30, improving the reliability of the product.

[0091] Please refer to Figure 3 In another embodiment, a wider cutting tool is used to remove the material of the routing structure 20 between the electronic modules 2a to expose the first surface 25a of the encapsulation layer 25, and then a wider cutting tool is used to form a recess in the first surface 25a of the exposed encapsulation layer 25, which is not through the encapsulation layer 25, to serve as the dam 39, and the position of the dam 39 does not correspond to the cutting path L, so that the dam 39 is formed in the form of a recess on the edge of the first surface 25a of the encapsulation layer 25. Therefore, the structure of the dam is various and is not particularly limited.

[0092] The present application also provides an electronic package 2, which comprises an encapsulation layer 25, at least one electronic element 21 embedded in the encapsulation layer 25, a plurality of conductive pillars 23 embedded in the encapsulation layer 25, a routing structure 24, a plurality of conductive elements 27 disposed on the routing structure 24, an electronic device 26, and an encapsulation material 28.

[0093] The encapsulation layer 25 has opposite first and second surfaces 25a and 25b, and the edge of the first surface 25a is formed with a dam 29, 39.

[0094] The routing structure 20 is disposed on the first surface 25a of the encapsulation layer 25 and exposes the dam 29, 39.

[0095] The wiring structure 24 is disposed on the second surface 25b of the encapsulation layer 25.

[0096] The electronic device 26 is disposed on the wiring structure 20 by the plurality of conductive bumps 260.

[0097] The encapsulation material 28 is formed between the wiring structure 20 and the electronic device 26, so that the encapsulation material 28 encapsulates the plurality of conductive bumps 260.

[0098] In an embodiment, the dam 29 is stepped.

[0099] In an embodiment, the dam 39 is a recess.

[0100] In an embodiment, the electronic element 21 is electrically connected to the wiring structure 20.

[0101] In an embodiment, the conductive pillar 23 is electrically connected to the wiring structure 20 and the wiring structure 24.

[0102] In an embodiment, the plurality of conductive elements 27 are electrically connected to the wiring structure 24.

[0103] In an embodiment, the electronic device 26 is electrically connected to the wiring structure 20 by the plurality of conductive bumps 260.

[0104] In an embodiment, the encapsulation material 28 is an underfill.

[0105] In an embodiment, the encapsulation material 28 extends into the dam 29, 39 but does not extend to the wiring structure 24.

[0106] In summary, the electronic package of the present application prevents the encapsulation material from overflowing onto the wiring structure by the configuration of the dam, so that the encapsulation material does not contact the conductive element. Therefore, the electronic package of the present application can avoid the problem of non-wetting of the conductive element when reflowing the conductive element in the subsequent process, thereby improving the reliability of the product.

[0107] The above embodiments are used to illustrate the principles and effects of the present application, but not to limit the present application. Any person skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application should be subject to the claims.

Claims

1. An electronic package, characterized by Comprising: a cap layer having opposite first and second surfaces, and an edge of the first surface forming a dam; an electronic element embedded in the cap layer; a circuit structure disposed on the first surface of the cap layer and externally exposed from the dam; a wiring structure disposed on the second surface of the cap layer; a plurality of conductive elements disposed on the wiring structure; an electronic device disposed on the circuit structure by a plurality of conductive bumps; and an encapsulation material formed between the circuit structure and the electronic device to encapsulate the plurality of conductive bumps. The dam is in a stepped shape.

2. The electronic package of claim 1, wherein, The dam is a recess.

3. The electronic package of claim 1, wherein, The electronic element is electrically connected to the circuit structure.

4. The electronic package of claim 1, wherein, The electronic package further comprises a plurality of conductive pillars embedded in the cap layer and electrically connected to the circuit structure and the wiring structure.

5. The electronic package of claim 1, wherein, The plurality of conductive elements are electrically connected to the wiring structure.

6. The electronic package of claim 1, wherein, The electronic device is electrically connected to the circuit structure by the plurality of conductive bumps.

7. The electronic package of claim 1, wherein, The encapsulation material is an underfill.

8. The electronic package of claim 1, wherein, The encapsulation material extends into the dam but not to the wiring structure.

9. The electronic package of claim 1, wherein, ​

Citation Information

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