Test probe card

Abstract

The utility model relates to a test probe card, which is applied to the field of wafer chip testing and comprises a limiting unit arranged on a control panel and used for installing a wafer chip, and the wafer chip is conducted with the control panel through a connecting unit. The device has the advantages that the wafer chip is installed on the limiting unit, the wafer chip is connected with the control panel through the connecting unit, a large amount of manual welding time is saved, time and labor are saved, and meanwhile the situation that when the tail of a probe is directly welded to a welding spot area of the control panel manually, the welding efficiency is improved is reduced. And channel errors exist, and the height of a winding needle and a probe is higher than that of a needle tip, so that the wafer chip testing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of wafer chip testing technology, and in particular to a test probe card. Background Technology

[0002] The test probe card connects to the control panel of the test machine and the wafer chip to perform preliminary measurements of the chip's electrical performance, transmit signals to test the wafer chip parameters, and screen out defective chips to ensure that only qualified chips enter the subsequent production process.

[0003] In related technologies, the test probe cards are manually soldered to the corresponding solder joints on the control panel under a microscope, with one probe corresponding to one solder joint. The connection between the wafer chip and the control panel is achieved by directly soldering the tail of the probe to the solder joint on the control panel.

[0004] The aforementioned test probe cards use a manual method to directly solder the tail of each probe to the solder joint area of ​​the control panel. The appearance and quality of the solder joints are difficult to guarantee, and there are situations where soldering errors occur, the probe is wound around the probe, or the probe height is higher than the tip of the probe, which can damage the wafer chip. This method is time-consuming and labor-intensive, resulting in low wafer chip testing efficiency. Summary of the Invention

[0005] To address the problems in related technologies where single probes are manually soldered directly to the control panel solder joint area, resulting in inconsistent solder joint appearance and quality, soldering errors, and probes being higher than the probe tip, potentially damaging the wafer chip, this application provides a test probe card with the following technical solution: It includes a limiting unit mounted on the control panel for mounting the wafer chip, and the wafer chip is connected to the control panel via a connection unit.

[0006] In one specific implementation, the limiting unit includes a mounting base disposed on a control panel, and the wafer chip is disposed on the mounting base.

[0007] In one specific implementation, the connection unit includes a test board mounted on a mounting base. The test board is provided with a plurality of test pins, which partially pass through the mounting base and are connected to the wafer chip. The test board is connected to the control panel through a plurality of contacts.

[0008] In one specific implementation, the test board is a flexible circuit board.

[0009] In one specific implementation, the ends of the test probes facing away from the control panel are respectively connected to the pins of the wafer chip, and the ends of the test probes facing the control panel are respectively connected to the pins of the test board.

[0010] In one specific implementation, the test board is provided with a first pad, the control panel is provided with a second pad, and a plurality of the contacts are respectively located between the first pad and the second pad.

[0011] In one specific implementation, several of the contacts are arranged in a circumferential array along the first pad.

[0012] In one specific implementation, the axes of the first pad and the second pad coincide.

[0013] In one specific implementation, several of the test pins are located at the center of the first pad.

[0014] In one specific implementation scheme, the mounting base is provided with a positioning post, and the test plate is provided with a positioning hole that matches the positioning post, with the positioning post passing through the positioning hole.

[0015] In summary, this application has at least the following beneficial technical effects: by mounting the wafer chip on the limiting unit, the wafer chip is connected to the control panel through the connection unit, which saves a lot of time and effort for manual soldering. At the same time, it reduces the possibility of channel errors, pin wrapping, and probe height exceeding the tip when the probe tail is directly soldered to the solder joint area of ​​the control panel, thus improving the testing efficiency of the wafer chip. Attached Figure Description

[0016] Figure 1 It is a schematic diagram of the overall structure of an embodiment of the present application.

[0017] Figure 2 This is a schematic diagram illustrating the structure of the test board in the embodiments of this application.

[0018] Reference numerals: 1. Limiting unit; 2. Connecting unit; 3. Mounting base; 4. Test board; 5. Test probe; 6. Contact; 7. First pad; 8. Positioning hole; 9. Control panel. Detailed Implementation

[0019] The following is in conjunction with the appendix Figure 1-2 This application will be described in further detail.

[0020] This application discloses a test probe card.

[0021] Reference Figure 1 and Figure 2The test probe card includes a limiting unit 1 mounted on a control panel 9 for mounting wafer chips. The wafer chips are connected to the control panel 9 via a connecting unit 2. The limiting unit 1 includes a mounting base 3 mounted on the control panel 9, with the wafer chips positioned on the end face of the mounting base 3 facing away from the control panel 9. Therefore, mounting the wafer chips on the mounting base 3 and connecting them to the control panel 9 via the connecting unit 2 saves significant time and effort associated with manual soldering. It also reduces the possibility of channel errors, probe wrapping, and probe height exceeding the tip when manually soldering the probe tails directly to the solder joint area of ​​the control panel 9, thus improving wafer chip testing efficiency.

[0022] Reference Figure 1 and Figure 2 The connection unit 2 includes a test board 4 mounted on a mounting base 3. A plurality of test pins 5 are connected to the test board 4. Each test pin 5 partially passes through the mounting base 3 and is connected to the wafer chip. The test board 4 is connected to the control panel 9 via a plurality of contacts 6. In this embodiment, the test board 4 is a flexible circuit board. Flexible circuit boards have good heat dissipation and solderability, can be freely bent, rolled, and folded, and can withstand millions of dynamic bends without damaging the wires. The ends of the test pins 5 facing away from the control panel 9 (the tips) are connected to the pins of the wafer chip, and the ends of the test pins 5 facing the control panel 9 (the tails) are connected to the pins of the test board 4. Figure 1 The arrows in the diagram represent the implementation path from the wafer chip to the tester loop.

[0023] Therefore, the wafer chip is mounted on the mounting base 3, and the tip of the test probe 5 contacts the wafer chip to achieve conductivity. The tail of the test probe 5 is connected to the pin of the test board 4. The test board 4 is connected to the control panel 9 through the contact 6. The control panel 9 transmits the signal to the tester through the channel loop, thereby realizing the testing of the wafer chip on the mounting base 3. By utilizing the conductivity between the tail of the test probe 5 and the pin of the test board 4, and the conductivity between the test board 4 and the control panel 9 through the contact 6, the manual single-pin soldering action is reduced, saving a lot of manufacturing time. At the same time, it reduces the possibility of soldering channel errors, probe wrapping, and probe height exceeding the tip, thus improving the wafer chip testing efficiency.

[0024] Reference Figure 1 and Figure 2 The test board 4 is connected to a first pad 7, and the control panel 9 is fixedly connected to a second pad. The axes of the first pad 7 and the second pad coincide. A plurality of contacts 6 are located between the first pad 7 and the second pad and are arranged in an array around the first pad 7. A plurality of test pins 5 are located at the center of the first pad 7. The stability of the conduction between the test board 4 and the control panel 9 is enhanced by the first pad 7 and the second pad. In this embodiment, the plurality of contacts 6 are formed by the pressing of solder balls.

[0025] Reference Figure 1 and Figure 2 The mounting base 3 is fixedly connected to two positioning posts. The test plate 4 has two positioning holes 8 that match the size of the positioning posts. The two positioning posts pass through the positioning holes 8 respectively. The positioning holes 8 limit the position of the positioning posts, thereby reducing the possibility of the test plate 4 shifting position and realizing the positioning between the mounting base 3 and the test plate 4.

[0026] The implementation principle of this application embodiment is as follows: a wafer chip is mounted on a mounting base 3, the tip of a test probe 5 contacts the wafer chip to achieve conductivity, the tail of the test probe 5 is connected to the pins of a test board 4, the test board 4 is connected to a control panel 9 through a contact 6, and the control panel 9 transmits signals to the tester through a channel loop, thereby realizing the testing of the wafer chip on the mounting base 3. By utilizing the conductivity between the tail of the test probe 5 and the pins of the test board 4, and the conductivity between the test board 4 and the control panel 9 through the contact 6, the manual single-pin soldering action is reduced, saving a significant amount of manufacturing time and effort. It also reduces the possibility of soldering channel errors, probe wrapping, and probe height exceeding the tip, thus improving the wafer chip testing efficiency.

[0027] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

Claims

1. A test probe card, characterized in that: The device includes a limiting unit (1) for mounting a wafer chip on a control panel (9), and the wafer chip is connected to the control panel (9) via a connecting unit (2); the limiting unit (1) includes a mounting base (3) on the control panel (9), and the wafer chip is mounted on the mounting base (3); the connecting unit (2) includes a test board (4) on the mounting base (3), the test board (4) is provided with a plurality of test pins (5), and the plurality of test pins (5) are partially passed through the mounting base (3) and connected to the wafer chip, and the test board (4) is connected to the control panel (9) via a plurality of contacts (6).

2. The test probe card according to claim 1, characterized in that: The test board (4) is a flexible circuit board.

3. The test probe card according to claim 1, characterized in that: The ends of several test pins (5) facing away from the control panel (9) are respectively connected to the pins of the wafer chip, and the ends of several test pins (5) facing the control panel (9) are respectively connected to the pins of the test board (4).

4. The test probe card according to claim 1, characterized in that: The test board (4) is provided with a first pad (7), the control panel (9) is provided with a second pad, and a plurality of contacts (6) are respectively located between the first pad (7) and the second pad.

5. The test probe card according to claim 4, characterized in that: Several of the contacts (6) are arranged in a circumferential array along the first pad (7).

6. The test probe card according to claim 4, characterized in that: The axes of the first pad (7) and the second pad coincide.

7. The test probe card according to claim 4, characterized in that: Several of the test pins (5) are located at the center of the first pad (7).

8. The test probe card according to claim 1, characterized in that: The mounting base (3) is provided with a positioning post, and the test plate (4) is provided with a positioning hole (8) that matches the positioning post. The positioning post passes through the positioning hole (8).

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