Charging transmission identification circuit and charging transmission device

Abstract

The utility model discloses a charging transmission identification circuit and a charging transmission device, and the identification circuit is arranged between a first USB interface and a second USB interface and between a VBUS power supply interface and the second USB interface, and is used for identifying the simultaneous conduction of the VBUS power supply interface and the second USB interface and the simultaneous conduction of the first USB interface and the second USB interface, and carrying out the identification of a USB protocol. According to the charging transmission identification circuit and the charging transmission device provided by the embodiment of the utility model, the identification sequence of the power interface and the USB interface can be achieved only by using the simple MOS tube and the NAND gate identification circuit, so that a USB protocol can be identified. The simple identification circuit is used to achieve the effect of charging and transmission at the same time, errors are not prone to occurring, and the design cost is better reduced.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, and in particular to a charging transmission identification circuit and a charging transmission device. Background Technology

[0002] To address the issue of charging a device while simultaneously transmitting data, a Y-type cable has emerged on the market. Connector 1 is a Type A female connector for external devices, connector 2 is a MicroB male connector for the device itself, and connector 3 is a Type B male connector for the power adapter. This allows the power adapter and external devices to be connected to the device simultaneously, enabling data transmission while the device is charging.

[0003] However, this type of Y-cable has a safety issue. When port 2 of the Y-cable is connected to the device terminal, the device terminal detects that the USB_ID interface is grounded. The device terminal's control battery then supplies power to the VBUS of port 2 on the Y-cable in reverse, causing the device terminal's charger to enter BOOST mode (the device terminal supplies power externally). Subsequently, when the adapter is plugged into port 3 of the Y-cable, the device terminal's charger enters BUCK mode (the adapter supplies power to the device terminal). Therefore, the device terminal's charger is simultaneously in both BOOST and BUCK modes, causing charger malfunction and potentially damaging the device terminal's battery.

[0004] like Figure 1 As shown, conventional Y-shaped cables require specific plugging and unplugging procedures for both the charging and data transfer ports to achieve simultaneous charging and data transfer; otherwise, data transfer errors may occur. This is because the USB protocol needs to detect power supply for a few seconds before detecting the USB signal to achieve USB protocol recognition. Therefore, the conventional way to use a Y-shaped cable is for the user to plug in the USB port first, then the power port, to achieve protocol recognition. However, manually distinguishing the ports before plugging and unplugging is prone to errors, leading to USB recognition errors and a poor user experience.

[0005] Either the design is relatively complex, such as Figure 2 As shown, various adapter chips are required to achieve this. Using an MCU chip or USB hub chip, after the USB interface and power supply interface are connected, the MCU chip or USB hub chip performs the conversion, allowing the device to distinguish the USB interface and thus recognize the USB. However, this design is relatively complex and expensive. Utility Model Content

[0006] One of the objectives of this utility model embodiment is to provide a charging transmission identification circuit and a charging transmission device to solve the problems of poor user experience or high cost of Y-type cables due to complex design while achieving charging and data transmission.

[0007] To solve the above-mentioned technical problems, in a first aspect, this utility model provides a charging transmission identification circuit. The identification circuit is disposed between the first USB interface and the second USB interface, and between the VBUS power supply interface and the second USB interface, for identifying that the VBUS power supply interface, the first USB interface and the second USB interface are simultaneously turned on, and for identifying the USB protocol.

[0008] Preferably, the identification circuit includes:

[0009] First diode D1, second diode D2, switching circuit;

[0010] Among them, the first diode and the second diode are used to prevent reverse current injection;

[0011] The switching circuit is used to turn off when it detects that the first USB port or the VBUS power supply port is plugged in alone for charging, and to turn on when it detects that the first USB port or the VBUS power supply port is plugged in simultaneously for charging.

[0012] Preferably, the switching circuit includes:

[0013] The NAND gate circuit includes a MOSFET Q2. The first diode is connected to the first USB interface of the Y-type line, and the second diode is connected to the VBUS power supply interface of the Y-type line. The first diode and the second diode are respectively connected to the S terminal of the MOSFET Q2, and the G terminal of the MOSFET is connected to the second USB interface of the Y-type line.

[0014] The input terminals of the NAND gate are connected to the first USB interface and the power supply interface, respectively, and the output terminal is connected to the gate (G) terminal of the MOSFET Q2.

[0015] Preferably, when charging is performed by plugging into either the first USB port or the VBUS power supply port alone, the NAND gate output is high, and MOSFET Q2 is controlled by the NAND gate and is in the off state; when the first USB port and the VBUS power supply port are powered at the same time, the NAND gate output is low, controlling MOSFET Q2 to turn on.

[0016] The first USB port and the VBUS power supply port supply power to the second USB port through the MOSFET Q2. The back-end device of the second USB port detects the supply voltage and identifies the USB protocol.

[0017] Preferably, the NAND gate circuit includes:

[0018] The components include a third diode D3, a fourth diode D4, a second resistor R2, and a MOSFET Q1. The third diode D3 and the fourth diode D4 are connected to the VBUS power supply interface and the first USB interface, respectively. The MOSFET Q1 is connected to the third diode D3 and the fourth diode D4.

[0019] Secondly, this utility model provides a charging transmission device, the charging transmission device comprising:

[0020] First USB port, VBUS port and second USB port;

[0021] The first USB interface is connected to the second USB interface; the VBUS interface is connected to the second USB interface;

[0022] The charging transmission device further includes an identification circuit disposed between the first USB interface and the second USB interface, and between the VBUS power supply interface and the second USB interface, for identifying the conduction of the VBUS power supply interface, the first USB interface and the second USB interface respectively, and for identifying the USB protocol.

[0023] Preferably, the identification circuit includes:

[0024] First diode D1, second diode D2, switching circuit;

[0025] Among them, the first diode and the second diode are used to prevent reverse current injection;

[0026] The switching circuit is used to turn off when it detects that the first USB port or the VBUS power supply port is plugged in alone for charging, and to turn on when it detects that the first USB port or the VBUS power supply port is plugged in simultaneously for charging.

[0027] Preferably, the switching circuit includes:

[0028] The NAND gate circuit includes a MOSFET Q2. The first diode is connected to the first USB interface of the Y-type line, and the second diode is connected to the VBUS power supply interface of the Y-type line. The first diode and the second diode are respectively connected to the S terminal of the MOSFET Q2, and the G terminal of the MOSFET is connected to the second USB interface of the Y-type line.

[0029] The input terminals of the NAND gate are connected to the first USB interface and the power supply interface, respectively, and the output terminal is connected to the gate (G) terminal of the MOSFET Q2.

[0030] Preferably, the NAND gate circuit includes:

[0031] The components include a third diode D3, a fourth diode D4, a second resistor R2, and a MOSFET Q1. The third diode D3 and the fourth diode D4 are connected to the VBUS power supply interface and the first USB interface, respectively. The MOSFET Q1 is connected to the third diode D3 and the fourth diode D4.

[0032] Compared with the prior art, the charging transmission identification circuit and charging transmission device provided by the present invention have at least the following beneficial effects:

[0033] Using only simple MOSFETs and NAND gates for identification, the system can correctly identify the power interface and USB interface sequentially, thus recognizing the USB protocol. This simple identification circuit achieves simultaneous charging and data transfer, is less prone to errors, and offers a cost-effective design. Attached Figure Description

[0034] The preferred embodiments will be described below in a clear and easy-to-understand manner, in conjunction with the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages and implementation methods of this utility model.

[0035] Figure 1 A schematic diagram of a prior art charging transmission device;

[0036] Figure 2 A schematic diagram of a prior art charging transmission device;

[0037] Figure 3 This is a schematic diagram of a charging transmission device according to an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of a charging transmission device according to an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of a charging transmission device according to an embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of a charging transmission identification circuit according to an embodiment of the present invention. Detailed Implementation

[0041] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the specific implementation methods of this utility model will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of this utility model. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0042] To keep the drawings concise, each figure only schematically shows the parts relevant to the utility model, and these do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of the components with the same structure or function is schematically depicted, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."

[0043] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0044] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0045] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0046] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0047] The following detailed description of the implementation of the technical solution of this utility model will be based on some specific embodiments.

[0048] like Figure 3 As shown, this application embodiment relates to a charging transmission device, which includes:

[0049] First USB port, VBUS port and second USB port;

[0050] The first USB interface is connected to the second USB interface; the VBUS interface is connected to the second USB interface;

[0051] The charging transmission device further includes an identification circuit disposed between the first USB interface and the second USB interface, and between the VBUS power supply interface and the second USB interface, for identifying the conduction of the VBUS power supply interface, the first USB interface and the second USB interface respectively, and for identifying the USB protocol.

[0052] The charging and transmission device may include a first USB interface (also called an input USB interface), a VBUS interface, and a second USB interface (also called an output USB interface); the first USB interface and the second USB interface are connected; the VBUS interface and the second USB interface are connected to form a Y-shaped data cable. The VBUS interface is used to connect an adapter (i.e., a power adapter), the second USB interface is used to connect a device terminal, the first USB interface is used to connect a Universal Serial Bus powered device (USB), i.e., a peripheral device, and the second interface may be a USB interface.

[0053] like Figure 3 As shown, this utility model embodiment provides a charging transmission device, including an identification circuit disposed between the first USB interface and the second USB interface, and between the VBUS power supply interface and the second USB interface, for identifying that the VBUS power supply interface, the first USB interface and the second USB interface are simultaneously turned on, and for identifying the USB protocol.

[0054] The connection between the first USB port and the second USB port enables subsequent identification of the USB protocol. At the same time, the power adapter connected to the VBUS power supply interface supplies power to the device terminal connected to the second USB port 30. The power adapter ensures sufficient power supply, effectively avoiding insufficient power supply caused by direct power supply from the USB port, and effectively detecting the VBUS 5V voltage.

[0055] Preferably, the identification circuit includes:

[0056] First diode D1, second diode D2, switching circuit;

[0057] Among them, the first diode and the second diode are used to prevent reverse current injection;

[0058] The switching circuit is used to turn off when it detects that the first USB port or the VBUS power supply port is plugged in alone for charging, and to turn on when it detects that the first USB port or the VBUS power supply port is plugged in simultaneously for charging.

[0059] Preferably, the switching circuit includes:

[0060] The NAND gate circuit includes a MOSFET Q2. The first diode is connected to the first USB interface of the Y-type line, and the second diode is connected to the VBUS power supply interface of the Y-type line. The first diode and the second diode are respectively connected to the S terminal of the MOSFET Q2, and the G terminal of the MOSFET is connected to the second USB interface of the Y-type line.

[0061] The input terminals of the NAND gate are connected to the first USB interface and the power supply interface, respectively, and the output terminal is connected to the gate (G) terminal of the MOSFET Q2.

[0062] Preferably, the NAND gate circuit includes:

[0063] The components include a third diode D3, a fourth diode D4, a second resistor R2, and a MOSFET Q1. The third diode D3 and the fourth diode D4 are connected to the VBUS power supply interface and the first USB interface, respectively. The MOSFET Q1 is connected to the third diode D3 and the fourth diode D4.

[0064] The NAND gate circuit includes: a third diode D3, a fourth diode D4, a second resistor R2, and a MOSFET Q1.

[0065] When VBUS_5V_IN is plugged in alone, VBUS_5V_IN is high and USB_5V_IN is low. Because the pull-up resistor R2 and D4 / R4 form a pull-down mechanism, the gate (G) of Q1 is low, so the Q1 MOSFET is turned off. At this time, both the source (S) and gate (G) of Q2 are high, Vgs = 0V, causing Q2 to turn off, and USB_5V_OUT is low. Since the backend does not detect the VBUS 5V voltage, the USB handshake protocol is not performed.

[0066] When USB_5V_IN is plugged in alone, USB_5V_IN is high and VBUS_5V_IN is low. Because the pull-up resistor R2 and D3 / R3 form a pull-down mechanism, the gate (G) of Q1 is low, so the Q1 MOSFET is turned off. At this time, both the source (S) and gate (G) of Q2 are high, Vgs = 0V, causing Q2 to turn off, and USB_5V_OUT is low. Since the backend does not detect the VBUS 5V voltage, the USB handshake protocol is not performed.

[0067] When both VBUS_5V_IN and USB_5V_IN are plugged in simultaneously, both VBUS_5V_IN and USB_5V_IN are at a high level. Because of the pull-up resistor R2, the gate (G) of Q1 is at a high level, turning Q1 on. This causes the gate (G) of Q2 to be pulled down to a low level, resulting in Vgs < 0V, which turns on Q2, and USB_5V_OUT outputs a 5V high level. The backend detects the VBUS 5V voltage, initiates the USB handshake protocol, and establishes a connection.

[0068] This utility model embodiment provides a charging transmission identification circuit. The identification circuit is disposed between the first USB interface and the second USB interface, and between the VBUS power supply interface and the second USB interface. It is used to identify that the VBUS power supply interface, the first USB interface and the second USB interface are simultaneously turned on, and to identify the USB protocol.

[0069] Preferably, the identification circuit includes:

[0070] First diode D1, second diode D2, switching circuit;

[0071] Among them, the first diode and the second diode are used to prevent reverse current injection;

[0072] The switching circuit is used to turn off when it detects that the first USB port or the VBUS power supply port is plugged in alone for charging, and to turn on when it detects that the first USB port or the VBUS power supply port is plugged in simultaneously for charging.

[0073] Preferably, the switching circuit includes:

[0074] The NAND gate circuit includes a MOSFET Q2. The first diode is connected to the first USB interface of the Y-type line, and the second diode is connected to the VBUS power supply interface of the Y-type line. The first diode and the second diode are respectively connected to the S terminal of the MOSFET Q2, and the G terminal of the MOSFET is connected to the second USB interface of the Y-type line.

[0075] The input terminals of the NAND gate are connected to the first USB interface and the power supply interface, respectively, and the output terminal is connected to the gate (G) terminal of the MOSFET Q2.

[0076] When charging is performed by plugging into either the first USB port or the VBUS power supply port alone, the NAND gate output is high, and MOSFET Q2 is turned off under the control of the NAND gate. When the first USB port and the VBUS power supply port are powered simultaneously, the NAND gate output is low, controlling MOSFET Q2 to turn on. The power from the first USB port and the VBUS power supply port supplies power to the second USB port through MOSFET Q2. The back-end device of the second USB port detects the power supply voltage and performs USB protocol identification.

[0077] Preferably, the NAND gate circuit includes:

[0078] The components include a third diode D3, a fourth diode D4, a second resistor R2, and a MOSFET Q1. The third diode D3 and the fourth diode D4 are connected to the VBUS power supply interface and the first USB interface, respectively. The MOSFET Q1 is connected to the third diode D3 and the fourth diode D4.

[0079] When charging is performed by plugging in either the first USB port or the VBUS power supply port alone, the NAND gate output is high, and the MOSFET is controlled by the NAND gate and is in the off state; when the first USB port and the VBUS power supply port are powered at the same time, the NAND gate output is low, and the MOSFET is turned on.

[0080] The first USB port and the VBUS power supply port supply power to the second USB port through a MOSFET. The back-end device of the second USB port detects the supply voltage and identifies the USB protocol.

[0081] The NAND gate circuit includes: a third diode D3, a fourth diode D4, a second resistor R2, and a MOSFET Q1.

[0082] When VBUS_5V_IN is plugged in alone, VBUS_5V_IN is high and USB_5V_IN is low. Because the pull-up resistor R2 and D4 / R4 form a pull-down mechanism, the gate (G) of Q1 is low, so the Q1 MOSFET is turned off. At this time, both the source (S) and gate (G) of Q2 are high, Vgs = 0V, causing Q2 to turn off, and USB_5V_OUT is low. Since the backend does not detect the VBUS 5V voltage, the USB handshake protocol is not performed.

[0083] When USB_5V_IN is plugged in alone, USB_5V_IN is high and VBUS_5V_IN is low. Because the pull-up resistor R2 and D3 / R3 form a pull-down mechanism, the gate (G) of Q1 is low, so the Q1 MOSFET is turned off. At this time, both the source (S) and gate (G) of Q2 are high, Vgs = 0V, causing Q2 to turn off, and USB_5V_OUT is low. Since the backend does not detect the VBUS 5V voltage, the USB handshake protocol is not performed.

[0084] When both VBUS_5V_IN and USB_5V_IN are plugged in simultaneously, both VBUS_5V_IN and USB_5V_IN are at a high level. Because of the pull-up resistor R2, the gate (G) of Q1 is at a high level, turning Q1 on. This causes the gate (G) of Q2 to be pulled down to a low level, resulting in Vgs < 0V, which turns on Q2, and USB_5V_OUT outputs a 5V high level. The backend detects the VBUS 5V voltage, initiates the USB handshake protocol, and establishes a connection.

[0085] This utility model provides a charging transmission identification circuit and device that uses only simple MOSFETs and NAND gates to identify the power interface and USB interface sequentially, thereby recognizing the USB protocol. The simple identification circuit achieves simultaneous charging and transmission, is less prone to errors, and offers advantages in design cost.

[0086] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0087] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0088] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0089] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0090] Furthermore, the functional units in the various embodiments of the application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software program module.

[0091] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. This program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk, etc.

[0092] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0093] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of this utility model. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.

Claims

1. A charging transmission identification circuit, characterized in that, The identification circuit is disposed between the first USB interface and the second USB interface, and between the VBUS power supply interface and the second USB interface, for identifying that the VBUS power supply interface and the first USB interface are simultaneously powered on with the second USB interface, and for identifying the USB protocol. The identification circuit includes: First diode D1, second diode D2, switching circuit; Among them, the first diode and the second diode are used to prevent reverse current injection; The switching circuit is used to turn off when it detects that the first USB port or the VBUS power supply port is plugged in alone for charging, and to turn on when it detects that the first USB port or the VBUS power supply port is plugged in simultaneously for charging.

2. The charging transmission identification circuit as described in claim 1, characterized in that, The switching circuit includes: The NAND gate circuit includes a MOSFET Q2. The first diode is connected to the first USB interface of the Y-type line, and the second diode is connected to the VBUS power supply interface of the Y-type line. The first diode and the second diode are respectively connected to the S terminal of the MOSFET Q2, and the G terminal of the MOSFET is connected to the second USB interface of the Y-type line. The input terminals of the NAND gate are connected to the first USB interface and the power supply interface, respectively, and the output terminal is connected to the gate (G) terminal of the MOSFET Q2.

3. The charging transmission identification circuit as described in claim 2, characterized in that, When charging is performed by plugging into the first USB port or the VBUS power supply port alone, the NAND gate output is high, and MOSFET Q2 is controlled by the NAND gate and is in the off state; when the first USB port and the VBUS power supply port are powered at the same time, the NAND gate output is low, controlling MOSFET Q2 to turn on. The first USB port and the VBUS power supply port supply power to the second USB port through the MOSFET Q2. The back-end device of the second USB port detects the supply voltage and identifies the USB protocol.

4. The charging transmission identification circuit as described in claim 3, characterized in that, The NAND gate circuit includes: The components include a third diode D3, a fourth diode D4, a second resistor R2, and a MOSFET Q1. The third diode D3 and the fourth diode D4 are connected to the VBUS power supply interface and the first USB interface, respectively. The MOSFET Q1 is connected to the third diode D3 and the fourth diode D4.

5. A charging transmission device, characterized in that, The charging transmission device includes: First USB port, VBUS port and second USB port; The first USB interface is connected to the second USB interface; the VBUS interface is connected to the second USB interface; The charging transmission device further includes an identification circuit disposed between the first USB interface and the second USB interface, and between the VBUS power supply interface and the second USB interface, for identifying the conduction of the VBUS power supply interface, the first USB interface, and the second USB interface, respectively, and for identifying the USB protocol, wherein the identification circuit includes: First diode D1, second diode D2, switching circuit; Among them, the first diode and the second diode are used to prevent reverse current injection; The switching circuit is used to turn off when it detects that the first USB port or the VBUS power supply port is plugged in alone for charging, and to turn on when it detects that the first USB port or the VBUS power supply port is plugged in simultaneously for charging.

6. The charging transmission device as described in claim 5, characterized in that, The switching circuit includes: The NAND gate circuit includes a MOSFET Q2. The first diode is connected to the first USB interface of the Y-type line, and the second diode is connected to the VBUS power supply interface of the Y-type line. The first diode and the second diode are respectively connected to the S terminal of the MOSFET Q2, and the G terminal of the MOSFET is connected to the second USB interface of the Y-type line. The input terminals of the NAND gate are connected to the first USB interface and the power supply interface, respectively, and the output terminal is connected to the gate (G) terminal of the MOSFET Q2.

7. The charging transmission device as described in claim 6, characterized in that, The NAND gate circuit includes: The components include a third diode D3, a fourth diode D4, a second resistor R2, and a MOSFET Q1. The third diode D3 and the fourth diode D4 are connected to the VBUS power supply interface and the first USB interface, respectively. The MOSFET Q1 is connected to the third diode D3 and the fourth diode D4.

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