DC anti-surge circuit
By combining the anti-surge setting circuit, the voltage doubling circuit and the MOS tube Q1, the problem of the inability to finely adjust the DC anti-surge circuit in the prior art is solved, and the effect of effectively protecting the subsequent circuit is achieved without increasing the burden.
Patent Information
- Application Number
- CN202422827232.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2034-11-19
AI Technical Summary
Existing DC surge protection circuits have additional burdens and cannot be finely adjusted when limiting surge voltage, resulting in an inability to fully protect subsequent circuits.
A combination of an anti-surge setting circuit, a voltage doubling circuit and a MOS tube Q1 is adopted. The voltage value of the NMOS tube is adjusted by the voltage doubling circuit, and the anti-surge voltage value is adjusted by the voltage regulator tube.
It achieves fine adjustment of the anti-surge voltage without adding extra burden, protects the subsequent circuit from damage, and ensures the normal operation of the system.
Smart Images
Figure CN223487859U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of surge protection circuit technology, and in particular to a DC surge protection circuit for use as a front-end surge protection circuit for DC-powered electronic products on aircraft. Background Technology
[0002] A DC surge protector circuit is a protective device used to protect downstream circuits from surge voltage impacts. It protects sensitive components from damage by limiting the surge energy that suddenly appears in the circuit, thereby ensuring the normal operation of the entire system.
[0003] The main DC surge protection solutions currently include: external capacitors, MOSFET soft-start at power-on, and surge protection diodes. While external capacitors can filter out most surges, the charging current at power-on can place an additional burden on the power supply system. MOSFET soft-start effectively limits the surge voltage at startup, and because the soft-start current is small, it has no impact on the preceding or following stages; however, it cannot intercept surges that suddenly occur during normal circuit operation. Surge protection diodes are usually connected in parallel with the power supply equipment. When the surge amplitude exceeds the diode's breakdown voltage, the diode breaks down, and current flows back to ground, thus protecting the equipment. However, diode breakdown is equivalent to a short circuit, resulting in a very large instantaneous current, which can also burden the power supply equipment. Furthermore, none of the above solutions allow for precise adjustment of the surge voltage, so they often cannot provide 100% protection for subsequent circuits.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this utility model, and therefore may include information that does not constitute prior art known to those skilled in the art. Utility Model Content
[0005] The purpose of this invention is to solve the technical problems existing in the background art. To this end, a DC surge protection circuit is provided.
[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows:
[0007] A DC surge protection circuit includes a surge protection setting circuit, a voltage multiplier circuit, and a MOSFET Q1;
[0008] The surge protection circuit includes resistors R1 and R2, as well as an external Zener diode.
[0009] One end of resistor R1 is electrically connected to the drain of MOSFET Q1, and the other end of resistor R1 is electrically connected to one end of resistor R2. The other end of resistor R2 is electrically connected to the power supply voltage terminal of the voltage multiplier circuit. An external Zener diode is connected in the line between resistor R2 and the power supply voltage terminal of the voltage multiplier circuit. The output terminal of the voltage multiplier circuit is electrically connected to the gate of MOSFET Q1.
[0010] The following is a further defined technical solution of this utility model: the voltage multiplier circuit includes a timer chip U1, the DISCH terminal of the timer chip U1 is electrically connected to resistors R3 and R4, the other end of resistor R3 is connected to the line between resistor R2 and the VDD terminal of the timer chip U1, the other end of resistor R4 is electrically connected to one end of capacitor C9, and the other end of capacitor C9 is grounded.
[0011] The following is a further technical solution of this utility model: the THRES terminal and TRIG terminal of the time base chip U1 are both grounded through capacitor C9.
[0012] The following is a further technical solution of this utility model: the VDD terminal and the RESET terminal of the time base chip U1 are electrically connected and grounded through capacitor C7.
[0013] The following is a further defined technical solution of this utility model: the CONT terminal of the time base chip U1 is grounded through capacitor C8.
[0014] The following is a further defined technical solution of this utility model: the OUT terminal of the timer chip U1 is connected to diodes D6, D5, D4, D3, and D2 in sequence; a capacitor C6 is connected between the input terminal of diode D6 and the output terminal of diode D5; a capacitor C3 is connected between the input terminal of diode D5 and the output terminal of diode D4; a capacitor C5 is connected between the input terminal of diode D4 and the output terminal of diode D3; a capacitor C2 is connected between the input terminal of diode D3 and the output terminal of diode D2; and the output terminal of diode D2 is electrically connected to the gate of MOSFET Q1.
[0015] The following is a further defined technical solution of this utility model: the output terminal of the diode D6 is grounded through capacitor C4.
[0016] The following is a further defined technical solution of this utility model: a Zener diode D10 is connected between the gate and source of the MOS transistor Q1, and the source of the MOS transistor Q1 is grounded through a capacitor C1.
[0017] Compared with the prior art, the present invention has the following technical effects:
[0018] This invention incorporates a surge protection setting circuit, a voltage multiplier circuit, and a MOSFET Q1. The voltage multiplier circuit sets the voltage value allowed through the NMOS transistor to achieve surge protection. Additionally, the surge protection setting circuit allows adjustment of the appropriate surge protection voltage value by adjusting the voltage regulation value of the Zener diode connected to ground at the SET pin.
[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a diagram of the external interface of the circuit module of this utility model;
[0022] Figure 2 This is a circuit block diagram of this utility model;
[0023] Figure 3 This is a circuit component connection diagram of this utility model. Detailed Implementation
[0024] To make the above-mentioned objects, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a full understanding of this utility model. However, this utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this utility model. Therefore, this utility model is not limited to the specific embodiments disclosed below.
[0025] In this embodiment of the invention, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to electrical connection; direct connection; or indirect connection through an intermediate medium; or the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this embodiment of the invention according to the specific circumstances.
[0026] This embodiment provides a DC surge protection circuit, which is assembled into modules, and the external interfaces of the modules are as follows: Figure 1 As shown: There are 4 pins in total. Pin 1 is the input terminal ( Figure 3 The left-side VIN terminal, pin 2 is the common terminal ( Figure 3 The left side is the COM terminal, and pin 3 is the output terminal. Figure 3 H2 end on the right side), 4 pins ( Figure 3 The SET terminal in the middle is connected to ground via an external Zener diode to set the surge voltage value, which is approximately 3 times the Zener diode's voltage regulation value.
[0027] like Figure 2 and 3 As shown, a DC surge protection circuit consists of a surge protection setting circuit, a voltage multiplier circuit, and a MOSFET Q1.
[0028] The surge protection circuit mainly consists of resistor R2 and a Zener diode connected to the SET pin.
[0029] The voltage multiplier circuit consists of a timer chip U1, resistors R3 and R4, capacitors C9, C8, C7, C6, C5, C4, C3, C2, and C1, diodes D6, D5, D4, D3, and D2, and a Zener diode D10. The timer chip U1 is model NE555.
[0030] One end of resistor R1 is electrically connected to the drain of MOSFET Q1, and the other end of resistor R1 is electrically connected to the negative terminal of transient voltage suppressor diode D8. The positive terminal of transient voltage suppressor diode D8 is grounded. One end of resistor R2 is connected in the line between resistor R1 and transient voltage suppressor diode D8, and the other end of resistor R2 is electrically connected to the VDD terminal of timer chip U1. The Zener diode connected to the SET pin is connected in the line between resistor R2 and the VDD terminal of timer chip U1. The DISCH terminal of timer chip U1 is electrically connected to resistors R3 and R4. The other end of resistor R3 is connected in the line between resistor R2 and the VDD terminal of timer chip U1. The other end of resistor R4 is electrically connected to one end of capacitor C9, and the other end of capacitor C9 is grounded. The THRES and TRIG terminals of timer chip U1 are both grounded through capacitor C9. The VDD and RESET terminals of timer chip U1 are electrically connected and grounded through capacitor C7. The CONT terminal of timer chip U1 is grounded through capacitor C8. The OUT terminal of the timer chip U1 is connected sequentially to diodes D6, D5, D4, D3, and D2. A capacitor C6 is connected between the input of diode D6 and the output of diode D5; a capacitor C3 is connected between the input of diode D5 and the output of diode D4; a capacitor C5 is connected between the input of diode D4 and the output of diode D3; and a capacitor C2 is connected between the input of diode D3 and the output of diode D2. The output of diode D2 is electrically connected to the gate of MOSFET Q1. The output of diode D6 is grounded through capacitor C4. A Zener diode D10 is connected between the gate and source of MOSFET Q1, and the source of MOSFET Q1 is grounded through capacitor C1.
[0031] The voltage multiplier circuit triples its power supply voltage (VDD terminal) and outputs it to the gate of NMOS transistor Q1. When there is a surge voltage at the input terminal (VIN terminal), since the source voltage of NMOS transistor Q1 cannot be higher than its gate voltage after it is turned on, the power supply voltage of the voltage multiplier circuit, powered by the Zener diode, remains unchanged. Therefore, when the surge voltage is greater than the output voltage of the voltage multiplier circuit, the output voltage of the entire module will not exceed the output voltage of the voltage multiplier circuit, thus achieving surge protection.
[0032] For example, if the power supply voltage is 28V, and the output voltage is required not to exceed 40V when a surge voltage occurs in the power supply system, then simply connect a 13V Zener diode to ground at the SET pin of the circuit module to ensure that the output voltage does not exceed 39V.
[0033] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model in any way. Any person skilled in the art can make many possible variations and modifications to the technical solution of this utility model using the disclosed methods and techniques, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of this utility model. Therefore, all equivalent changes made based on the shape, structure, and principle of this utility model without departing from its technical solution should be covered within the protection scope of this utility model.
Claims
1. A DC surge protection circuit, characterized in that, This includes surge protection circuitry, voltage multiplier circuitry, and MOSFET Q1; The surge protection circuit includes resistors R1 and R2, as well as an external Zener diode. One end of resistor R1 is electrically connected to the drain of MOSFET Q1, and the other end of resistor R1 is electrically connected to one end of resistor R2. The other end of resistor R2 is electrically connected to the power supply voltage terminal of the voltage multiplier circuit. An external Zener diode is connected in the line between resistor R2 and the power supply voltage terminal of the voltage multiplier circuit. The output terminal of the voltage multiplier circuit is electrically connected to the gate of MOSFET Q1.
2. The DC surge protection circuit as described in claim 1, characterized in that, The voltage multiplier circuit includes a timer chip U1. The DISCH terminal of the timer chip U1 is electrically connected to resistors R3 and R4. The other end of resistor R3 is connected to the line between resistor R2 and the VDD terminal of the timer chip U1. The other end of resistor R4 is electrically connected to one end of capacitor C9. The other end of capacitor C9 is grounded.
3. The DC surge protection circuit as described in claim 2, characterized in that, The THRES and TRIG terminals of the time base chip U1 are both grounded through capacitor C9.
4. A DC surge protection circuit as described in claim 2, characterized in that, The VDD and RESET terminals of the time base chip U1 are electrically connected and grounded through capacitor C7.
5. A DC surge protection circuit as described in claim 2, characterized in that, The CONT terminal of the time base chip U1 is grounded through capacitor C8.
6. A DC surge protection circuit as described in claim 2, characterized in that, The OUT terminal of the timer chip U1 is connected in sequence to diodes D6, D5, D4, D3, and D2. A capacitor C6 is connected between the input terminal of diode D6 and the output terminal of diode D5, a capacitor C3 is connected between the input terminal of diode D5 and the output terminal of diode D4, a capacitor C5 is connected between the input terminal of diode D4 and the output terminal of diode D3, and a capacitor C2 is connected between the input terminal of diode D3 and the output terminal of diode D2. The output terminal of diode D2 is electrically connected to the gate of MOSFET Q1.
7. A DC surge protection circuit as described in claim 6, characterized in that, The output terminal of diode D6 is grounded through capacitor C4.
8. A DC surge protection circuit as described in claim 2, characterized in that, A Zener diode D10 is connected between the gate and source of the MOS transistor Q1, and the source of the MOS transistor Q1 is grounded through a capacitor C1.