Circuit for expanding clock into multipath synchronous clocks in flow cytometer

Abstract

The utility model discloses a circuit for expanding a clock into multiple paths of synchronous clocks in a flow cytometer, which comprises a crystal oscillator module, the power supply end of the crystal oscillator module is electrically connected with a chip driving power supply through a filter, the output end of the crystal oscillator module is connected with the input end of a clock fan-out buffer, and the output end of the clock fan-out buffer is electrically connected with the chip driving power supply. A plurality of first source clock paths are led out from a plurality of output ends of the clock fan-out buffer respectively, the first source clock paths are connected with an input end of a clock distributor, a plurality of second source clock paths are led out from an output end of the clock distributor, and the second source clock paths output expanded multi-path synchronous clocks; and the control end of the clock distributor is electrically connected with the controller. The utility model discloses a circuit for expanding a clock into multiple paths of synchronous clocks in a flow cytometer. A plurality of synchronous clocks can be provided, and the synchronous clocks can be aligned through phase delay adjustment.

Description

Technical Field

[0001] This utility model relates to the field of flow cytometer technology, and in particular to a circuit for expanding a single clock in a flow cytometer into multiple synchronous clocks. Background Technology

[0002] Currently used flow cytometers typically have no more than 15 acquisition channels. They usually employ a single clock fan-out buffer to fan out multiple synchronous clocks to perform synchronous sampling and data alignment of multiple ADC (analog-to-digital converter) channels.

[0003] In newer multi-laser flow cytometers, the number of data acquisition channels is relatively large (various configurations typically have 10 to 40 acquisition channels). Each channel's ADC (analog-to-digital converter) requires a synchronization clock for data sampling, and multiple channels require multiple synchronization clocks. Conventional single-clock fan-out buffers can usually only fan out a few to a dozen synchronization clocks, with a maximum of generally no more than 16 synchronization clocks. Therefore, for multi-laser flow cytometers that require dozens of synchronization clocks, conventional single-clock fan-out buffers are insufficient to meet the synchronization clock requirements of numerous channels.

[0004] Furthermore, due to the chip's manufacturing process and packaging technology, there is a slight time difference between all outputs of the same clock fan-out buffer, meaning they are not strictly synchronized. However, data acquisition and alignment of multiple channels in a flow cytometer requires strict synchronization of multiple clocks. If these clocks are not strictly synchronized, sporadic data corruption or digital noise will occur. This unpredictable sporadic noise is often difficult to filter out using software filtering. Therefore, conventional single-clock fan-out buffer solutions have the drawback of not being able to strictly align the multiple output clocks. When the back-end processor performs data alignment and processing, it introduces a small amount of digital noise into the flow cytometer that is difficult to eliminate.

[0005] Disadvantages of existing technology:

[0006] 1) A single clock fanout buffer can only output a maximum of a dozen or so clock channels, which is usually insufficient to meet the needs of multi-laser flow cytometer applications, which often require a number of synchronous clocks for thirty or forty acquisition channels.

[0007] 2) The layout and trace length of the internal circuitry of a clock fan-out buffer directly affect signal transmission delay. Furthermore, the chip's manufacturing process and packaging technology also influence signal transmission speed. Therefore, there is a slight time difference between all outputs of the same clock fan-out buffer, making strict synchronization impossible. In multi-laser flow cytometers, timing requirements are stringent, necessitating strict synchronization of multiple clocks. Otherwise, a small amount of difficult-to-eliminate digital noise will be introduced during data alignment and processing in the backend processor. Therefore, a conventional single-clock fan-out buffer is unlikely to meet the strict synchronization requirements of multiple clocks.

[0008] Therefore, existing technologies urgently need to address the following technical issues:

[0009] In multi-laser flow cytometer applications, the number of synchronization clocks fanned out by a single clock fanout buffer is relatively small, which is difficult to meet the needs of multi-laser flow cytometers that often require thirty or forty synchronization clocks. Furthermore, due to the manufacturing process and packaging technology of the single clock fanout buffer, there is a small time difference between all the output clocks fanned out, which is difficult to strictly synchronize and align. This introduces a small amount of digital noise that is difficult to eliminate when the back-end processor performs data alignment and processing. Utility Model Content

[0010] This invention overcomes the shortcomings of the prior art and provides a circuit for expanding a single clock in a flow cytometer into multiple synchronous clocks; it can provide a large number of synchronous clocks, and these synchronous clocks can be aligned through phase delay adjustment.

[0011] To achieve the above objectives, the technical solution adopted by this utility model is as follows: a circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer, comprising: a crystal oscillator module, the power supply terminal of which is electrically connected to a chip driver power supply via a filter; the output terminal of which is connected to the input terminal of a clock fan-out buffer; several output terminals of the clock fan-out buffer respectively lead out several first source clock paths; the first source clock paths are connected to the input terminal of a clock distributor; the output terminal of the clock distributor leads out several second source clock paths; the second source clock paths output the expanded multiple synchronous clocks; and the control terminal of the clock distributor is electrically connected to a controller.

[0012] In a preferred embodiment of this utility model, the filter is a π-type filter, including an inductor L1. One end of the inductor L1 is connected to the chip driving power supply, and the other end of the inductor L1 is connected to the power supply terminal of the crystal oscillator module. The two ends of the inductor L1 are grounded at the same point through capacitors CA and CB and the ground terminal of the crystal oscillator module, respectively.

[0013] In a preferred embodiment of this invention, the output terminal of the crystal oscillator module is connected to the input terminal of the clock fan-out buffer via a transformer.

[0014] In a preferred embodiment of this invention, the high-voltage side of the transformer is connected to the output terminal of the crystal oscillator module, and the low-voltage side of the transformer is connected to the input terminal of the clock fan-out buffer.

[0015] In a preferred embodiment of this invention, the VREF terminal of the clock fan-out buffer is grounded through capacitor C0C, and the CLK0 terminal of the clock fan-out buffer and the reverse... The terminals are connected to the transformer via DC blocking and AC passing capacitors C0B and C0A, respectively, and the CLK0 terminal and the reverse terminal are connected... The terminal is connected through resistor R0; the VS terminal of the clock fan-out buffer is connected to the drive power supply, and the VS terminal is connected to one end of capacitor C0D. The other end of capacitor C0D is grounded at the same point as the IN_SEL terminal, CTRL_A terminal, CTRL_B terminal, CTRL_C terminal, SLEEP terminal, and GND terminal of the clock fan-out buffer. The VS terminal of the clock fan-out buffer is connected through resistor R0; the ...

[0016] In a preferred embodiment of this invention, the EP terminal of the clock distributor is grounded;

[0017] The EXT_CAP0 terminal of the clock distributor is grounded through parallel filter capacitors C1E and C1F;

[0018] The EXT_CAP1 terminal of the clock distributor is grounded through parallel filter capacitors C1C and C1D;

[0019] The VDD terminal of the clock distributor is grounded through the filter capacitor C1H, and the VDD terminal is connected to the power supply.

[0020] The CLK terminal and reverse of the clock distributor The terminals are respectively connected to the output terminal of the clock fan-out buffer through DC blocking and AC blocking capacitor C1B and DC blocking and AC blocking capacitor C1A, and the terminals of capacitors C1B and C1A connected to the output terminal of the clock fan-out buffer are electrically connected through resistor R1.

[0021] The IN_SEL terminal of the clock distributor is connected to the power supply via a pull-up resistor R1A;

[0022] The output of the clock distributor leads out an extended multi-channel synchronous clock.

[0023] The clock distributor end, The SCLK, SDIO, SDO, and CS / S2 terminals of the clock distributor are respectively connected to the control terminal of the controller, and the SCLK, SDIO, and SDO terminals of the clock distributor are interconnected with the SCLK, SDIO, and SDO terminals of other clock distributors besides itself.

[0024] In a preferred embodiment of this utility model, the transformer is a transmission line transformer with a turns ratio of 1:1.

[0025] The crystal oscillator module uses a SIT9121AI crystal oscillator.

[0026] The clock fan-out buffer uses the ADCLK854 clock fan-out buffer;

[0027] The clock distributor used is the AD9508 clock distributor;

[0028] The controller is either an MCU controller or an FPGA controller.

[0029] In a preferred embodiment of this utility model, the output terminal of the clock distributor leads to several second source clock paths, and the second source clock paths are further connected in series with several Nth-level clock distributors, where N is a non-zero natural number, and the control terminal of the Nth-level clock distributor is connected to the controller.

[0030] Compared with the prior art, the beneficial effects achieved by this utility model are as follows:

[0031] This invention discloses a circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer; it can provide a large number of synchronous clocks, and these synchronous clocks can be aligned through phase delay adjustment.

[0032] A scheme consisting of a single clock fan-out buffer and multiple cascaded clock distributors can greatly expand the number of output synchronization clocks, meeting the quantity requirements of multi-laser flow cytometers for multiple synchronization clocks. At the same time, each output clock of the clock distributor also has the functions of output frequency division and delay adjustment. The controller can flexibly configure the frequency of each output clock and adjust the phase delay of each output clock through the bus interface. Even if the back-end circuit does not have a phase-locked loop, the clocks can be strictly synchronized by adjusting the phase delay. Attached Figure Description

[0033] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0034] Figure 1 This is a control block diagram of a circuit in a flow cytometer that expands a single clock into multiple synchronous clocks, according to an embodiment of the present invention.

[0035] Figure 2This is a schematic diagram of the signal source excitation superposition circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer, as provided in an embodiment of this utility model. Detailed Implementation

[0036] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0037] The term "and / or" simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. Additionally, the character " / " generally indicates an "or" relationship between the related objects. Example 1

[0038] like Figure 1 As shown, a circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer includes: a crystal oscillator module, the power supply terminal of which is electrically connected to the chip driver power supply through a filter; the output terminal of the crystal oscillator module is connected to the input terminal of a clock fan-out buffer; several output terminals of the clock fan-out buffer respectively lead out several first source clock paths; the first source clock paths are connected to the input terminal of a clock distributor; the output terminal of the clock distributor leads out several second source clock paths; the second source clock paths output the expanded multiple synchronous clocks; and the control terminal of the clock distributor is electrically connected to a controller. Example 2

[0039] like Figure 1 As shown, a circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer includes: a crystal oscillator module; the power supply terminal of the crystal oscillator module is electrically connected to the chip driver power supply via a filter; the output terminal of the crystal oscillator module is connected to the input terminal of a clock fan-out buffer; several output terminals of the clock fan-out buffer respectively lead to several first source clock paths; the first source clock paths are connected to the input terminal of a clock distributor; the output terminal of the clock distributor leads to several second source clock paths; the second source clock paths output the expanded multiple synchronous clocks; and the control terminal of the clock distributor is electrically connected to a controller. Furthermore, the crystal oscillator module is configured separately through a hierarchical combination module of several levels of clock fan-out buffers and clock distributors.

[0040] Furthermore, more synchronous clocks are needed, and this can be further expanded through a three-stage cascade. Meanwhile, the second-stage clock distributor also has output frequency division and delay adjustment functions. The controller can flexibly configure the frequency of each output clock and adjust the phase delay of each output clock through the bus interface. Even without a phase-locked loop in the back-end circuit, the clocks can be strictly synchronized by adjusting the phase delay, thus solving the problem of a small amount of digital noise introduced by the fan-out buffer of a single clock in a flow cytometer due to the inability to strictly align the multiple synchronous clocks fanned out. This solution can expand to a sufficient number of synchronous clocks, and the phase delay of each output clock can be individually set by the controller for each clock distributor, thus ensuring strict synchronization of the output clocks. This solves the requirement for strict synchronization of multiple channels of synchronous clocks in multi-laser flow cytometers, greatly reducing the small amount of digital noise introduced by the inability to strictly align the synchronous clocks. If even more synchronous clocks are needed, they can be further expanded through a three-stage cascade.

[0041] This invention offers a highly flexible method for expanding multiple synchronous clocks through a cascading scheme. In principle, a circuit for expanding a single clock in a flow cytometer into multiple synchronous clocks can be cascaded in multiple stages to generate any number of synchronous clocks, sufficient to meet the needs of multi-laser flow cytometers for multiple synchronous clocks. Furthermore, the output clock frequency of each channel can be flexibly configured according to system requirements. Additionally, the delay time between channels can be adjusted to ensure strict synchronization and alignment of all clocks, solving the problem of a small amount of digital noise introduced by the inability to strictly align multiple synchronous clocks fanned out by a single clock fanout buffer in flow cytometers. Example 3

[0042] like Figure 1 , Figure 2 As shown, a circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer includes: a crystal oscillator module, the power supply terminal of which is electrically connected to the chip driver power supply through a filter, the filter being a π-type filter, and an inductor L1, one end of which is connected to the chip driver power supply, the other end of which is connected to the power supply terminal of the crystal oscillator module, and both ends of the inductor L1 are grounded at the same point through capacitors CA and CB and the ground terminal of the crystal oscillator module, respectively.

[0043] Specifically, the output of the crystal oscillator module is connected to the input of the clock fan-out buffer via a transformer. The high-voltage side of the transformer is connected to the output of the crystal oscillator module, and the low-voltage side is connected to the input of the clock fan-out buffer. Furthermore, the VREF terminal of the clock fan-out buffer is grounded through capacitor C0C, and the CLK0 terminal of the clock fan-out buffer is connected to the inverting... The terminals are connected to the transformer via DC blocking and AC passing capacitors C0B and C0A, respectively, and the CLK0 terminal and the reverse terminal are connected... The terminal is connected through resistor R0; the VS terminal of the clock fanout buffer is connected to the drive power supply, and the VS terminal is connected to one end of capacitor C0D. The other end of capacitor C0D is grounded at the same point as the IN_SEL terminal, CTRL_A terminal, CTRL_B terminal, CTRL_C terminal, SLEEP terminal, and GND terminal of the clock fanout buffer. The VS terminal of the clock fanout buffer is connected through resistor R0; the ...

[0044] Specifically, several output terminals of the clock fan-out buffer each lead to several first source clock paths, which are connected to the input terminals of the clock distributor. The output terminals of the clock distributor lead to several second source clock paths, which output extended multi-channel synchronous clocks. Furthermore, the control terminal of the clock distributor is electrically connected to the controller. Further, the EP terminal of the clock distributor is grounded; the EXT_CAP0 terminal of the clock distributor is grounded through parallel filter capacitors C1E and C1F; the EXT_CAP1 terminal of the clock distributor is grounded through parallel filter capacitors C1C and C1D; the VDD terminal of the clock distributor is grounded through capacitor C1H, and the VDD terminal is connected to the power supply; the CLK terminal of the clock distributor and the reverse... The terminals are connected to the output of the clock fan-out buffer via DC-blocking and AC-passing capacitors C1B and C1A, respectively, and the ends of C1B and C1A connected to the output of the clock fan-out buffer are electrically connected via resistor R1; the IN_SEL terminal of the clock distributor is connected to the power supply via pull-up resistor R1A; the output of the clock distributor leads out the extended multi-channel synchronous clock; the clock distributor... The clock distributor's SCLK, RESET, SCLK, SDIO, SDO, and CS / S2 terminals are connected to the controller's control terminals, and the clock distributor's SCLK, SDIO, and SDO terminals are interconnected with the SCLK, SDIO, and SDO terminals of other clock distributors besides itself.

[0045] Furthermore, the transformer used is a transmission line transformer with a 1:1 turns ratio; the crystal oscillator module uses a SIT9121AI crystal oscillator. The clock fan-out buffer uses an ADCLK854 clock fan-out buffer; the clock distributor uses an AD9508 clock distributor; and the controller uses an MCU controller or an FPGA controller. However, this is not the only option; other product models can be selected in other embodiments according to actual needs.

[0046] Working principle:

[0047] This utility model discloses a circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer. The scheme of cascading a single clock fan-out buffer and multiple clock distributors can greatly expand the number of output synchronous clocks, meeting the quantity requirements of multi-laser flow cytometers for multiple synchronous clocks. At the same time, each output clock of the clock distributor also has the functions of output frequency division and delay adjustment. The controller can flexibly configure the frequency of each output clock and adjust the phase delay of each output clock through the bus interface. Even if the back-end circuit does not have a phase-locked loop, the clocks can be strictly synchronized by adjusting the phase delay.

[0048] The crystal oscillator of this invention generates a source clock, which is then input to the first-stage clock fan-out buffer. After passing through the first-stage clock fan-out buffer, n synchronous clocks of the same frequency can be output. These n synchronous clocks are then input to the input terminals of the second-stage configurable clock distributor, which integrates output frequency division and delay adjustment. The controller configures the second-stage clock distributors separately through the bus interface. Each clock distributor in the second stage can output m synchronous clocks. In this way, by cascading the first and second stages, a total of n*m synchronous clocks can be obtained, which is sufficient to meet the multi-channel synchronous clock requirements of multi-laser flow cytometers.

[0049] The advantages of using the same source clock in this invention mainly include the following aspects:

[0050] 1. Improve system stability: Since all clock signals originate from the same source, their phase and frequency relationships are known. This ensures the synchronization of various parts of the system in time, reduces errors and failures caused by clock asynchrony, and thus improves the stability and reliability of the system.

[0051] 2. Reduced Design Complexity: Using a single source clock reduces the number of clock domains and avoids synchronization issues between different clock domains. This simplifies circuit design, reduces the design complexity of the clock management module, and lowers the difficulty of system implementation.

[0052] 3. Reduce clock skew and jitter: Since all clock signals originate from the same source, clock skew and jitter can be effectively reduced. Clock skew and jitter are significant factors affecting system performance; using a single source clock can effectively reduce these effects, improving system performance and accuracy.

[0053] 4. Reduced power consumption and cost: Using a single clock source reduces the need for external clock sources, thereby lowering system power consumption and cost. Furthermore, unified clock source management also helps optimize overall system power management.

[0054] 5. Easier to debug and maintain: Since all clock signals originate from the same source, system debugging and maintenance become much simpler. When problems arise, they are easier to locate and resolve because all clock signals follow the same standards and specifications. Example 4

[0055] This embodiment uses a method of cascading a single clock fan-out buffer and multiple clock distributors to expand a sufficient number of synchronous clocks. Furthermore, the frequency and phase delay of each output clock of the clock distributor can be set, making the frequency of each output clock flexibly adjustable and strictly synchronized. This effectively solves the requirement of strict synchronization of multiple channels in multi-laser flow cytometers and eliminates a small portion of digital noise introduced by multi-laser flow cytometers due to the inability to strictly align the synchronous clocks.

[0056] like Figure 2 The image shown is an example of a specific embodiment of this utility model, which is described in detail below:

[0057] Figure 2 Selection and application of key components:

[0058] Crystal Oscillator: The SiTime SIT9121AI-2DF-25E125.000000Y crystal oscillator is used. Its output frequency accuracy can reach six decimal places (one millionth of a Hertz), with only 0.6 picoseconds of RMS (root mean square) phase jitter. It can directly output LVDS type signals without the need for additional signal format conversion circuits. The clock signal is transmitted in LVDS format, which has many excellent characteristics. It is a high-speed, low-voltage differential signal with low power consumption, low bit error rate, low crosstalk and low radiation, and can be transmitted over long distances.

[0059] Clock Fan-Out Buffer: Utilizing Analog Devices' (ADI) ADCLK854 clock fan-out buffer, it features two selectable differential inputs, up to 12 LVDS or 24 CMOS outputs, a 70 picosecond time skew between output channels, and a 2.0 nanosecond propagation delay. This is selected via grounding pin 10 (IN_SEL). Pin 2 and CLK0 (pin 3) serve as the input differential clock signal ports; all 12 output clock signals are selected as LVDS format signals by grounding CTRL_A (pin 11), CTRL_B (pin 12), and CTRL_C (pin 13); SLEEP (pin 14) is grounded to enable the chip to work normally instead of being in sleep mode; pin 1 VREF is AC grounded through the filter capacitor C0C; the chip's power supply pins VS (pins 7, 18, 24, 30, 37, and 43) are connected to a 1.8V power supply, and the filter capacitor C0D filters the 1.8V power supply.

[0060] Clock distributor: Utilizes Analog Devices' (ADI) AD9508 clock distributor, featuring 1.65 GHz differential clock input / output, a 10-bit programmable divider, integer division ratios from 1 to 1024, up to 4 differential outputs or 8 CMOS outputs, excellent output isolation, automatic synchronization of all outputs, phase offset selection for output-to-output delay adjustment, 3 programmable logic level outputs: LVDS, HSTL, and CMOS, serial control port (SPI / I2C) or pin-programmable mode. The AD9508 provides clock fan-out capability and is designed for low jitter and low phase noise to optimize system performance, providing clocking for high-speed ADCs, DACs, DDS, DDC, DUC, and MxFE. The first-stage clock expansion chip, ADCLK854, has 12 LVDS outputs. Each output serves as a differential input to the second-stage clock expansion chip, AD9508. There are 12 AD9508s in total, and each AD9508 can output 4 synchronous LVDS clocks. Thus, through two stages of expansion, a total of 12 * 4 = 48 synchronous clocks are output. Pin 13 (VDD) of each AD9508 clock expansion chip is connected to a 2.5V power supply, and filtered by filter capacitors (C1H×××C12H). Pin 23 (IN_SEL) of each AD9508 clock expansion chip is pulled up to a 2.5V power supply through external pull-up resistors (R1A×××R12A) (IN_SEL pin is logic high), making the input ports (pin 21 CLK and pin 22) of each AD9508... Configured as differential input; each clock extension chip AD9508 is connected via an SPI bus interface (pin 19 SCLK / SCL / S0, pin 24 SDIO / SDA / S1, pin 4 SDO / S3, pin 1 CS / S2). The controller can flexibly configure the output frequency and phase delay time of each output clock of the AD9508 according to specific needs. The controller briefly pulls pin 20 low. This enables the AD9508 clock extension chip to perform hard output synchronization. After the pin is released, the output clocks of each channel are forced to align at the edges, regardless of their output frequency; pulling the RESET pin 18 low by the controller can reset the clock extension chip AD9508.

[0061] Controller: The controller can be an MCU or an FPGA. In flow cytometers, an FPGA is used as the controller. Because flow cytometers have numerous channels and data acquisition and processing for each channel need to be performed in parallel, an FPGA is used as the controller. The controller is mainly used for data processing, coordinating the normal operation of various components in the system according to a predetermined timing sequence, and configuring the second-stage clock distributor through a bus interface. It can flexibly set the frequency and phase delay time of each output clock of each clock distributor. By adjusting the phase delay time, the output clocks of each clock distributor can be strictly synchronized. The controller flexibly configures the output frequency and phase delay time of the second-stage clock distributor AD9508 through the SPI bus interface. By adjusting the phase delay time, all clocks output by AD9508 can be strictly synchronized. Additionally, the controller can briefly pull low pin 20 of the AD9508 clock distributor (…). This enables the AD9508 clock distributor to perform hard output synchronization; the controller can control the pulling down of pin 18 RESET of the AD9508 clock distributor to reset the AD9508 clock distributor.

[0062] like Figure 2 As shown, the functional modules of each part are described below:

[0063] The high-performance crystal oscillator module uses crystal oscillator OSC1, and capacitor CA, inductor L1, and capacitor CB form a π-type filter to provide 2.5V filtering to the power supply pin 6 (VDD) of crystal oscillator OSC1.

[0064] Pin 1 of the crystal oscillator module's OSC1 ( Connect to pin 6 to enable the high-performance crystal oscillator to work properly.

[0065] Transformer Tr1 is a 1:1 transmission line transformer used to match transmission lines with different impedances, enabling signal transmission between different transmission lines. Transmission line transformers achieve signal transmission through magnetic coupling, isolating signals between different circuits to prevent mutual interference. They also filter out unwanted high-frequency noise, resulting in clearer and more stable signals. Pin 5 of transformer Tr1 is connected to the output terminal OUT- of the high-performance crystal oscillator OSC1, and pin 4 is connected to the output terminal OUT+ of the high-performance crystal oscillator OSC1. Pin 1 of transformer Tr1 is connected to one end of the DC-blocking and AC-passing capacitor COB, and pin 3 of transformer Tr1 is connected to one end of the DC-blocking and AC-passing capacitor COA.

[0066] The other end of the DC blocking and AC passing capacitor COB is connected to the clock fanout buffer ADCLK854. Connect the negative terminal of the differential clock input to pin 2 (DC blocking and AC passing capacitor COA), and connect the other end of pin COA to the positive terminal of the differential clock input of pin CLK0 (pin 3) of the clock fan-out buffer ADCLK854. Connect the terminating resistor RO (100Ω) in parallel near the clock fan-out buffer ADCLK854. Between the negative terminal of the pin and the positive terminal of the CLK0 pin.

[0067] The clock fanout buffer ADCLK854 The negative terminal and the positive terminal of CLK0 receive the differential clock output from the high-performance crystal oscillator OSC1. Through the device's internal frequency replication mechanism, it provides a stable first-stage multi-channel synchronous clock output, and also functions as power supply noise filtering, electromagnetic interference suppression, and signal level conversion. The negative terminal of each differential output of the clock fan-out buffer ADCLK854 ( ××× Each of the following is connected to one end of the DC blocking and AC passing capacitor (C1B×××C12B): OUT0××× OUT11, and each differential output positive terminal of the clock fan-out buffer ADCLK854 is connected to one end of the DC blocking and AC passing capacitor (C1A×××C12A): OUT0××× OUT11, OUT11, OUT12A, OUT1A, OUT12B ...

[0068] The AD9508, serving as the second-stage clock extender, corresponds to each output of the ADCLK854 clock fan-out buffer. Since the ADCLK854 has 12 output clocks, the second stage has 12 AD9508 clock distributors to receive the 12 LVDS synchronous clocks output from the first-stage ADCLK854. Pin 23 (IN_SEL) of each AD9508 clock distributor is pulled up to 2.5V via an external pull-up resistor (R1A or R12A). The negative terminal of the differential clock input of each AD9508... Each of the following is connected to the other end of a DC-blocking and AC-passing capacitor (C1B×××C12B): the positive terminal (CLK) of the differential clock input of each AD9508 is connected to the other end of a DC-blocking and AC-passing capacitor (C1A×××C12A); pin 13 (VDD) of each AD9508 is connected to 2.5V and then connected to GND through a filter capacitor (C1H×××C12H). Pin 5 (EXT_CAP0) of each AD9508 clock distributor is connected to GND via filter capacitors (C1E, C1F×××C12E, C12F). Pin 14 (EXT_CAP1) of each AD9508 is connected to GND via filter capacitors (C1C, C1D×××C12C, C12D). Each AD9508 is connected to the controller's SPI bus interface via SPI bus interfaces (pin 19 SCLK / SCL / S0, pin 24 SDIO / SDA / S1, pin 4 SDO / S3, pin 1 CS / S2). Pin 20 of each AD9508... Each clock distributor (AD9508) is connected to the controller's I / O port via pin 18. Each AD9508 clock distributor connects to the controller's I / O ports, outputting four LVDS synchronous clocks with configurable frequencies and adjustable phase delay times. Twelve AD9508 clock distributors can output a total of 48 LVDS synchronous clocks. Of course, if 48 synchronous clocks are not required, the number of AD9508 clock distributors can be reduced according to actual needs.

[0069] Furthermore, the controller is primarily used for data processing, coordinating the normal operation of various components in the system according to a predetermined timing sequence. The controller configures each AD9508 clock distributor via the SPI bus, allowing flexible setting of the output frequency of any output clock from each AD9508 and adjustment of the phase delay time of any output clock from each AD9508. By adjusting the phase delay time, all clocks output by each AD9508 can be strictly synchronized. Additionally, the controller can briefly pull low pin 20 of each AD9508 clock distributor. This enables it to perform hard output synchronization. The controller can control the pulling down of pin 18 of each clock distributor AD9508. Reset it.

[0070] Working principle:

[0071] This invention discloses a circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer; it can provide a large number of synchronous clocks, and these synchronous clocks can be aligned through phase delay adjustment.

[0072] A scheme consisting of a single clock fanout buffer and multiple cascaded clock distributors (such as...) Figure 1 A source clock generated by a high-performance crystal oscillator is input to the first-stage clock fan-out buffer. This buffer outputs n synchronous clocks at the same frequency. These n synchronous clocks are then input to the second-stage configurable clock distributor, which integrates output frequency division and delay adjustment. The controller configures the second-stage clock distributors individually via a bus interface. Each second-stage clock distributor can output m synchronous clocks. By cascading the first and second stages, a total of n*m synchronous clocks can be obtained, sufficient to meet the multi-channel synchronous clock requirements of multi-laser flow cytometers. If more synchronous clocks are needed, a third-stage cascade can be used to further expand the range. Simultaneously, the second-stage clock distributor also features output frequency division and delay adjustment. The controller can flexibly configure the frequency of each output clock and adjust its phase delay via the bus interface. Even without a phase-locked loop (PLL) in the back-end circuit, adjusting the phase delay ensures strict synchronization of all clocks, thus solving the problem of a small amount of digital noise introduced by the fan-out buffer in flow cytometers due to the inability to strictly align the multiple synchronous clocks generated.

[0073] Figure 1 The circuit block diagram shown consists of four components: a high-performance crystal oscillator, a clock fan-out buffer, n configurable clock dividers with integrated output frequency division and delay adjustment, and a controller.

[0074] A single high-performance crystal oscillator is used to generate the system's source clock. If multiple independent crystal oscillators are used in the design to provide clock signals to different chips, it will increase the system cost, increase the circuit board area, and cause time synchronization problems. A good system design will choose to use a single master clock crystal oscillator as the clock source, and then distribute the source clock signal to each chip in the system through a clock buffer.

[0075] In summary, using the same source clock for multiple synchronous clocks can not only improve the stability and reliability of the system, but also simplify the design complexity, reduce power consumption and cost, and facilitate system debugging and maintenance.

[0076] A single clock fan-out buffer, acting as the first-stage clock extension, generates a first-stage multi-channel synchronous clock through an internal frequency replication mechanism after receiving a source clock from a high-performance crystal oscillator. It typically also performs format and level conversion, making circuit design simpler and more flexible. Clock buffers enhance the driving capability of clock signals, reduce signal jitter and noise, and ensure the normal operation of subsequent circuits. This is crucial for maintaining the stability and reliability of the entire electronic system. In multi-laser flow cytometers, data acquisition from multiple ADC channels needs to be synchronized. Clock buffers provide a consistent clock signal, ensuring that multiple ADC channels operate according to a predetermined timing sequence. However, due to the manufacturing process and packaging technology of the clock buffer chip itself, there is still a slight time difference between all the fan-out output clocks, meaning they are not strictly synchronized. Therefore, in applications with stringent synchronization requirements, it is necessary to adjust the phase delay of the output clocks of each channel during the second-stage clock allocation to ensure strict synchronization of the final output clocks. Ideally, this phase delay adjustment should be flexibly configurable by the controller.

[0077] For electronic systems requiring multiple clock signals, using a clock source with a clock fan-out buffer can effectively reduce system costs. Compared to using a crystal oscillator at each logic node, a clock buffer can provide more clock signal outputs while reducing the need for crystal oscillators, thereby reducing PCB size and cost.

[0078] n configurable clock distributors with integrated output frequency division and delay adjustment serve as the second-stage clock extension. Their inputs are connected to each output of the first-stage clock fan-out buffer. Each clock distributor can output m synchronous clocks. The controller can flexibly configure the second-stage clock distributors through the bus interface to adjust the frequency and phase delay of each output clock. Even without a phase-locked loop circuit at the back end, the clocks can be strictly synchronized by adjusting the phase delay time. This solves the problem of a small amount of digital noise introduced by the single clock fan-out buffer in flow cytometers due to the inability of multiple synchronous clocks fanned out to be strictly aligned.

[0079] Based on the preferred embodiments of this utility model, and through the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A circuit for expanding a single clock in a flow cytometer into multiple synchronous clocks, characterized in that, include: The crystal oscillator module has its power supply terminal electrically connected to the chip driver power supply via a filter. The output terminal of the crystal oscillator module is connected to the input terminal of a clock fan-out buffer. Several output terminals of the clock fan-out buffer lead out several first source clock paths, which are connected to the input terminal of a clock distributor. The output terminal of the clock distributor leads out several second source clock paths, which output extended multi-channel synchronous clocks. The control terminal of the clock distributor is electrically connected to a controller.

2. The circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer according to claim 1, characterized in that: The filter is a π-type filter, including an inductor L1. One end of the inductor L1 is connected to the chip driving power supply, and the other end of the inductor L1 is connected to the power supply terminal of the crystal oscillator module. The two ends of the inductor L1 are grounded at the same point through capacitors CA and CB and the ground terminal of the crystal oscillator module, respectively.

3. The circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer according to claim 2, characterized in that: The output of the crystal oscillator module is connected to the input of the clock fan-out buffer via a transformer.

4. The circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer according to claim 3, characterized in that: Furthermore, the high-voltage side of the transformer is connected to the output terminal of the crystal oscillator module, and the low-voltage side of the transformer is connected to the input terminal of the clock fan-out buffer.

5. The circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer according to claim 4, characterized in that: The VREF terminal of the clock fan-out buffer is grounded through capacitor C0C, and the CLK0 terminal of the clock fan-out buffer is connected to the inverting capacitor. The terminals are connected to the transformer via DC blocking and AC passing capacitors C0B and C0A, respectively, and the CLK0 terminal and the reverse terminal are connected... The terminal is connected through resistor R0; the VS terminal of the clock fan-out buffer is connected to the drive power supply, and the VS terminal is connected to one end of capacitor C0D. The other end of capacitor C0D is grounded at the same point as the IN_SEL terminal, CTRL_A terminal, CTRL_B terminal, CTRL_C terminal, SLEEP terminal, and GND terminal of the clock fan-out buffer. The VS terminal of the clock fan-out buffer is connected through resistor R0; the ...

6. The circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer according to claim 5, characterized in that: The EP terminal of the clock distributor is grounded; The EXT_CAP0 terminal of the clock distributor is grounded through parallel filter capacitors C1E and C1F; The EXT_CAP1 terminal of the clock distributor is grounded through parallel filter capacitors C1C and C1D; The VDD terminal of the clock distributor is grounded through the filter capacitor C1H, and the VDD terminal is connected to the power supply. The CLK terminal and reverse of the clock distributor The terminals are respectively connected to the output terminal of the clock fan-out buffer through DC blocking and AC blocking capacitor C1B and DC blocking and AC blocking capacitor C1A, and the terminals of capacitors C1B and C1A connected to the output terminal of the clock fan-out buffer are electrically connected through resistor R1. The IN_SEL terminal of the clock distributor is connected to the power supply via a pull-up resistor R1A; The output of the clock distributor leads out an extended multi-channel synchronous clock. The clock distributor end, The SCLK, SDIO, SDO, and CS / S2 terminals of the clock distributor are respectively connected to the control terminal of the controller, and the SCLK, SDIO, and SDO terminals of the clock distributor are interconnected with the SCLK, SDIO, and SDO terminals of other clock distributors besides itself.

7. The circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer according to claim 1, characterized in that: The transformer used is a transmission line transformer with a turns ratio of 1:1; The crystal oscillator module uses a SIT9121AI crystal oscillator. The clock fan-out buffer uses the ADCLK854 clock fan-out buffer; The clock distributor used is the AD9508 clock distributor; The controller is either an MCU controller or an FPGA controller.

8. The circuit for expanding a single clock into multiple synchronous clocks in a flow cytometer according to claim 1, characterized in that: The output terminal of the clock distributor leads to several second source clock paths, and the second source clock paths are also connected in series with several Nth level clock distributors, where N is a non-zero natural number, and the control terminal of the Nth level clock distributor is connected to the controller.

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