Mode switching circuit realized based on pulse signal and radar
By using a pulse signal-based mode switching circuit, and utilizing an NMOS transistor and a reset switch, flexible switching of radar modes is achieved. This solves the problems of complex and costly switching in existing technologies, and realizes low power consumption and stable mode switching, making it suitable for applications such as automotive radar.
Patent Information
- Application Number
- CN202422487293.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-14
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-10-14
AI Technical Summary
There is a lack of universal, standardized methods in existing radar circuits for switching between full-load operating mode and low quiescent current mode, and existing switching circuits are complex and costly.
A pulse signal-based mode switching circuit is adopted. Through an initial level output unit, a full-load operating mode unit, a low quiescent current mode unit, and a power output switching unit, the circuit achieves flexible mode switching using NMOS transistors and a reset switch. The pulse signal controls the conduction and cutoff of the NMOS transistors to realize the bistable function of the circuit.
It achieves a low static current mode when the radar is not in operation, saving power. When a signal is detected, it automatically switches to full-load operation. The circuit structure is simple and inexpensive, and it has memory function and stable mode switching capability.
Smart Images
Figure CN223501156U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of circuit design, and relates to a switching circuit, particularly to a mode switching circuit and radar based on pulse signals. Background Technology
[0002] Currently, many electronic devices operate in different modes. Taking radar as an example, its circuitry includes low quiescent current mode and full-load mode. These different modes are typically determined based on the radar's specific design, application scenario, and user requirements. However, there is no universal, standardized method for switching between these two modes, as it depends on factors such as the radar's power management, hardware design, software control, and external interfaces.
[0003] In addition, the existing switching circuits for different modes are often complex in structure, and some switching circuits are expensive to build. Summary of the Invention
[0004] This application provides a mode switching circuit and radar based on pulse signals, which solves the problem of how to flexibly switch between full-load operating mode and low quiescent current mode in electronic circuits at a lower cost.
[0005] In a first aspect, this application provides a mode switching circuit based on a pulse signal. The circuit includes: an initial level output unit that outputs an initial level of the circuit's initial state; a full-load operating mode unit connected to the initial level output unit; a low quiescent current mode unit connected to both the initial level output unit and the full-load operating mode unit, wherein the initial level causes the full-load operating mode unit to conduct preferentially over the low quiescent current mode unit; and a power output switching unit, including a first switching unit and a second switching unit. The first switching unit is connected to the full-load operating mode unit. After the first switching unit receives a first pulse signal and conducts, a level signal is applied to the full-load operating mode unit to conduct, and the circuit enters the full-load operating mode. The second switching unit is connected to the low quiescent current mode unit. After the second switching unit receives a second pulse signal and conducts, a level signal is applied to the low quiescent current mode unit to conduct, and the circuit enters the low quiescent current mode.
[0006] In one implementation of the first aspect, the initial level output unit includes a charging capacitor, one end of which is connected to a power supply and the other end of which is connected to the full-load operating mode unit.
[0007] In one implementation of the first aspect, the full-load operating mode unit includes a first NMOS (N-Metal-Oxide-Semiconductor) transistor; the other end of the charging capacitor is connected to the gate of the first NMOS transistor, and in the initial state of the circuit, after the charging capacitor is charged, it transmits a high-level signal to the gate of the first NMOS transistor, thereby turning on the gate of the first NMOS transistor.
[0008] In one implementation of the first aspect, the first switching unit is connected to the gate of the first NMOS transistor; when the circuit needs to be woken up again from the low quiescent current mode, after the first switching unit receives the first pulse signal and turns on, the generated high-level signal is transmitted to the gate of the first NMOS transistor, causing the gate of the first NMOS transistor to turn on.
[0009] In one implementation of the first aspect, the low quiescent current mode unit includes a second NMOS transistor; the second switching unit is connected to the gate of the second NMOS transistor; when the circuit needs to enter the low quiescent current mode, after the second switching unit receives the second pulse signal and turns on, the generated high-level signal is transmitted to the gate of the second NMOS transistor, causing the gate of the second NMOS transistor to turn on.
[0010] In one implementation of the first aspect, the first switching unit includes a first reset switch, and the second switching unit includes a second reset switch; one end of the first reset switch receives the first pulse signal, and the other end is connected to the full-load operating mode unit; one end of the second reset switch receives the second pulse signal, and the other end is connected to the low quiescent current mode unit.
[0011] In one implementation of the first aspect, the circuit further includes: a forward conduction unit; the forward conduction unit includes a first forward conduction device and a second forward conduction device; the first forward conduction device is connected to the full-load operating mode unit and the first switching unit respectively, and the second forward conduction device is connected to the low quiescent current mode unit and the second switching unit respectively.
[0012] In one implementation of the first aspect, the first forward conducting device includes a first diode, and the second forward conducting device includes a second diode; the anode of the first diode is connected to the first switching unit, and the cathode is connected to the full-load operating mode unit; the anode of the second diode is connected to the second switching unit, and the cathode is connected to the low quiescent current mode unit.
[0013] In one implementation of the first aspect, the circuit further includes a load driving unit; the load driving unit is connected to the full-load operating mode unit, and after the full-load operating mode unit is turned on, the circuit enters the full-load operating mode, and the load driving unit drives the subsequent load.
[0014] Secondly, this application provides a radar, which includes: the mode switching circuit based on pulse signals.
[0015] As described above, the mode switching circuit and radar based on pulse signals described in this application have the following beneficial effects:
[0016] This application utilizes two switching units to flexibly switch from full-load operation to a very low quiescent current mode when the radar is not in use, thus saving power. When a signal is detected, a CAN pulse can instantly return the radar to full-load operation. The circuit is simple to build and inexpensive. It is a bistable circuit with memory function; simply providing a pulse signal corresponding to a specific mode changes the circuit state, and the pulse can be removed after stabilization. It automatically latches the signal, allowing for seamless switching between low quiescent current and full-load operation modes. Attached Figure Description
[0017] Figure 1 The diagram shows the structural connection of the mode switching circuit based on pulse signals as described in the embodiments of this application.
[0018] Figure 2 The diagram shown is a circuit structure diagram of the mode switching circuit based on pulse signals described in an embodiment of this application.
[0019] Figure 3 The diagram shown is a schematic of mode switching of the pulse signal-based mode switching circuit described in an embodiment of this application.
[0020] Figure 4 The diagram shown is a simulation test circuit diagram of the mode switching circuit based on pulse signals described in the embodiments of this application.
[0021] Figure 5 The diagram shown is a simulation result of the mode switching circuit based on pulse signals described in the embodiments of this application.
[0022] Figure 6 The diagram shown is a structural schematic of the radar described in an embodiment of this application.
[0023] Component designation explanation
[0024] 1 Mode switching circuit based on pulse signal
[0025] 11 Initial Level Output Unit
[0026] 12 Full-load operating mode units
[0027] 13 Low quiescent current mode units
[0028] 14 Power Output Switching Unit
[0029] 141 First Switching Unit
[0030] 142 Second Switching Unit Detailed Implementation
[0031] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.
[0032] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0033] The technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0034] Please see Figure 1 The diagram shows the structural connection of the mode switching circuit based on pulse signals described in an embodiment of this application. Figure 1 As shown, this application embodiment provides a mode switching circuit 1 based on pulse signals, specifically including: an initial level output unit 11, a full-load operating mode unit 12, a low quiescent current mode unit 13, and a power output switching unit 14.
[0035] The initial level output unit 11 outputs the initial level of the initial state of the output circuit.
[0036] The full-load operating mode unit 12 is connected to the initial level output unit 11.
[0037] The low quiescent current mode unit 13 is connected to the initial level output unit 11 and the full load operating mode unit 12, respectively. The initial level causes the full load operating mode unit 12 to be turned on before the low quiescent current mode unit 13.
[0038] The power output switching unit 14 includes a first switching unit 141 and a second switching unit 142. The first switching unit 141 is connected to the full-load operating mode unit 12. After the first switching unit 141 receives a first pulse signal and turns on, a level signal is applied to the full-load operating mode unit 12 to turn it on, and the circuit 1 enters the full-load operating mode. The second switching unit 142 is connected to the low quiescent current mode unit 13. After the second switching unit 142 receives a second pulse signal and turns on, a level signal is applied to the low quiescent current mode unit 13 to turn it on, and the circuit 1 enters the low quiescent current mode.
[0039] In one embodiment, the initial level output unit includes a charging capacitor, one end of which is connected to a power supply and the other end of which is connected to the full-load operating mode unit.
[0040] Please see Figure 2 The diagram shows the circuit structure of the mode switching circuit based on pulse signals described in the embodiments of this application. Figure 2 As shown, the initial level output unit 11 includes a charging capacitor C4, one end of which is connected to the power supply VCC, and the other end is connected to the full-load operating mode unit 12.
[0041] In one embodiment, the full-load operating mode unit includes a first NMOS transistor.
[0042] The other end of the charging capacitor is connected to the gate of the first NMOS transistor. In the initial state of the circuit, after the charging capacitor is charged, it transmits a high-level signal to the gate of the first NMOS transistor, causing the gate of the first NMOS transistor to conduct.
[0043] like Figure 2 As shown, the full-load operating mode unit 12 includes a first NMOS transistor Q17. The other end of the charging capacitor C4 is connected to the gate of the first NMOS transistor Q17. In the initial state of the circuit, after the charging capacitor C4 is charged, it transmits a high-level signal to the gate of the first NMOS transistor Q17, turning on the gate of the first NMOS transistor Q17.
[0044] In one embodiment, the first switching unit is connected to the gate of the first NMOS transistor.
[0045] When the circuit needs to be woken up again from the low static current mode, after the first switching unit receives the first pulse signal and turns on, the high-level signal generated is transmitted to the gate of the first NMOS transistor, causing the gate of the first NMOS transistor to turn on.
[0046] like Figure 2As shown, the first switching unit 141 is connected to the gate of the first NMOS transistor Q17. When the circuit 1 needs to be woken up from the low quiescent current mode, after the first switching unit 141 receives the first pulse signal CANINH and turns on, the generated high-level signal is transmitted to the gate of the first NMOS transistor Q17, causing the gate of the first NMOS transistor Q17 to turn on.
[0047] In one embodiment, the low quiescent current mode unit includes a second NMOS transistor; the second switching unit is connected to the gate of the second NMOS transistor.
[0048] When the circuit needs to enter the low static current mode, after the second switching unit receives the second pulse signal and turns on, the high-level signal generated is transmitted to the gate of the second NMOS transistor, causing the gate of the second NMOS transistor to turn on.
[0049] like Figure 2 As shown, the low quiescent current mode unit 13 includes a second NMOS transistor Q18; the second switching unit 142 is connected to the gate of the second NMOS transistor Q18. When the circuit 1 needs to enter the low quiescent current mode, after the second switching unit 142 receives the second pulse signal WAKE and turns on, the generated high-level signal is transmitted to the gate of the second NMOS transistor Q18, turning on the gate of the second NMOS transistor Q18.
[0050] Please see Figure 3 The diagram shows a mode switching schematic of the pulse signal-based mode switching circuit described in an embodiment of this application. Figure 3 As shown, after power-on, the circuit operates normally under full load, and the corresponding mode is activated by a pulse signal corresponding to different modes. Specifically, the full-load operating mode corresponding to Q17 is activated according to the first pulse signal CANINH; the full-load operating mode corresponding to Q17 is activated according to the second pulse signal WAKE.
[0051] In one embodiment, the first switching unit includes a first reset switch, and the second switching unit includes a second reset switch.
[0052] One end of the first reset switch receives the first pulse signal, and the other end is connected to the full-load operating mode unit; one end of the second reset switch receives the second pulse signal, and the other end is connected to the low quiescent current mode unit.
[0053] like Figure 2As shown, the first switching unit includes a first reset switch S4, and the second switching unit includes a second reset switch S3. One end of the first reset switch S4 receives the first pulse signal CANINH, and the other end is connected to the full-load operating mode unit 12; one end of the second reset switch S3 receives the second pulse signal WAKE, and the other end is connected to the low quiescent current mode unit 13.
[0054] In one embodiment, the circuit further includes a forward conduction unit; the forward conduction unit includes a first forward conduction device and a second forward conduction device.
[0055] The first forward conducting device is connected to the full-load operating mode unit and the first switching unit, respectively, and the second forward conducting device is connected to the low quiescent current mode unit and the second switching unit, respectively.
[0056] like Figure 2 As shown, the circuit further includes a forward conduction unit; the forward conduction unit includes a first forward conduction device and a second forward conduction device. The first forward conduction device is connected to the full-load operating mode unit 12 and the first switching unit 141, respectively, and the second forward conduction device is connected to the low quiescent current mode unit 13 and the second switching unit 142, respectively.
[0057] Furthermore, the first forward conducting device includes a first diode, and the second forward conducting device includes a second diode.
[0058] The anode of the first diode is connected to the first switching unit, and the cathode is connected to the full-load operating mode unit; the anode of the second diode is connected to the second switching unit, and the cathode is connected to the low quiescent current mode unit.
[0059] like Figure 2 As shown, the first forward conducting device includes a first diode D8, and the second forward conducting device includes a second diode D7. The anode of the first diode D8 is connected to the first switching unit 141, and the cathode is connected to the full-load operating mode unit 12; the anode of the second diode D7 is connected to the second switching unit 142, and the cathode is connected to the low quiescent current mode unit 13.
[0060] In one embodiment, the circuit further includes a load driving unit.
[0061] The load driving unit is connected to the full-load working mode unit. After the full-load working mode unit is turned on, the circuit enters the full-load working mode, and the load driving unit drives the subsequent load.
[0062] like Figure 2As shown, the circuit also includes a load driving unit, which includes a driving MOSFET Q1. The load driving unit is connected to the full-load operating mode unit 12. After the full-load operating mode unit 12 is turned on, the circuit enters the full-load operating mode, and the load driving unit drives the subsequent load.
[0063] against Figure 2 The functions of each major component are as follows:
[0064] The charging capacitor C4 ensures a predetermined initial output level, guaranteeing that Q17 conducts before Q18, resulting in a high initial output level. D7 and D8 ensure the circuit's forward conduction. Q17 and Q18 are N-channel MOSFETs; their drain (D) and source (S) conduct when the gate voltage VG > source voltage VS and VGS > threshold voltage (Vth). Q1 is a P-channel power MOSFET, driving the subsequent load. S3 and S4 are switches, which can be reset buttons; a single pulse is sufficient, and they do not need to be continuously high. When a pulse is input to WAKE, the power output is turned off; when a pulse is input to CANINH, the power output is turned on.
[0065] Combination Figure 2 Taking the application of the pulse signal-based mode switching circuit 1 in radar as an example, its operating principle is as follows:
[0066] 1. When the power is first applied:
[0067] (1) There are no CANINH and WAKE signals, only 12V. In order to output 12V power, a charging capacitor C4 is added. After power-on, C4 starts charging. At this time, the voltage of line 30 is high level 12V.
[0068] (2) When line 30 is high, the G terminal (line 35) of Q17 is high, and the VG of the MOS transistor is greater than VS = 0. At this time, Q17 is turned on.
[0069] (3) When Q17 is turned on, line 34 is 0V. At this time, Q1 is turned on and outputs 12V power, and the radar is fully loaded.
[0070] Second, the radar does not need to operate at full load and enters a low static current mode:
[0071] (1) The MCU (Microcontroller Unit) sends a pulse signal to WAKE. At this time, switch S3 is closed, and the pulse passes through D7 and reaches G (line 36) of Q18. At this time, G is high level.
[0072] (2) When VG of Q18 > VS, Q18 is turned on. At this time, G (line 30) of Q18 is 0V.
[0073] (3) At this time, the G of Q17 is 0V, Q17 is turned off, and the D (line 34) of Q17 is high.
[0074] (4) At this time, Q1 does not satisfy G>S, Q1 is turned off, and line 17 outputs a low level of 0V.
[0075] III. Radar Reawakening
[0076] (1) When the radar circuit needs to be woken up, a high-level pulse signal appears in CANINH. At this time, S4 is closed, D8 is turned on, and the G of Q17 is high. At this time, Q17 is turned on again, and the D terminal (line 34) of Q17 is low.
[0077] (2) When line 34 outputs a low level, Q1 is turned on and line 17 outputs a high level.
[0078] Please see Figure 4 The diagram shown is a simulation test circuit diagram of the mode switching circuit based on pulse signals described in the embodiments of this application. Figure 4 As shown, the changes in the gate signal of Q17 in the load drive unit and the full load operating mode unit are illustrated. The A channel of the simulation oscilloscope is connected to the output terminal of Q1 in the load drive unit (line 17), and the B channel of the simulation oscilloscope is connected to the gate of Q17 in the full load operating mode unit (line 30). Thus, the simulation oscilloscope will display two sets of electrical signal waveforms.
[0079] Please see Figure 5 The image shown is a schematic diagram illustrating the simulation results of the mode switching circuit based on pulse signals described in the embodiments of this application. Figure 5 As shown, the circuit initially powers on with a 12V high level. The WAKE input pulse signal is low by default. When WAKE is high, it achieves voltage switching to disable the circuit. The CANINH input pulse signal is also high. In this embodiment, the WAKE signal provided by the MCU is set to high to achieve voltage switching to disable the circuit. If WAKE is set to low to achieve voltage switching to disable the circuit, the WAKE pin output will be low when the MCU is not working. In this case, the circuit to be implemented should be a CAN interrupt wake-up circuit, not a continued power-down circuit. Furthermore, while a low WAKE signal can be achieved when the MCU is powered, it is also low when the MCU is de-powered. This could lead to erroneous operation.
[0080] Please see Figure 6 The diagram shows a schematic representation of the radar structure described in an embodiment of this application. Figure 6 As shown in the figure, this application embodiment also provides a radar, which includes: the above-mentioned mode switching circuit 1 based on pulse signals.
[0081] The pulse signal-based mode switching circuit 1 includes: an initial level output unit that outputs an initial level of the circuit's initial state; a full-load operating mode unit connected to the initial level output unit; a low quiescent current mode unit connected to both the initial level output unit and the full-load operating mode unit, wherein the initial level causes the full-load operating mode unit to conduct before the low quiescent current mode unit; and a power output switching unit, including a first switching unit and a second switching unit. The first switching unit is connected to the full-load operating mode unit. After receiving a first pulse signal and turning on, the first switching unit applies a level signal to the full-load operating mode unit, causing it to conduct, and the circuit enters the full-load operating mode. The second switching unit is connected to the low quiescent current mode unit. After receiving a second pulse signal and turning on, the second switching unit applies a level signal to the low quiescent current mode unit, causing it to conduct, and the circuit enters the low quiescent current mode.
[0082] In a practical application, taking an automotive radar as an example, when the power supply is first powered on with a 12V input, the link operates normally, outputting 12V. When a pulse is input to the WAKE, the power output is turned off; when a pulse is input to the CAN, the power output is turned on. When the person leaves the vehicle, the radar does not need to operate at full load. At this time, the MCU sends a pulse to power off the power supply. When an abnormal situation occurs, the CAN wakes up the power supply to achieve low quiescent current when not in operation.
[0083] Therefore, this application provides a low-power, high-level wake-up circuit. It uses a transistor analog circuit to achieve pulse input and steady-state output, and the power supply flips again when the next pulse arrives. In automotive radar applications, this solves the power loss problem caused by the inability to disconnect power when the radar is constantly powered. When the radar does not need to detect, it can achieve very low quiescent current. When normal operation is required, it can be woken up via the CAN interrupt interface. This circuit can achieve efficient and stable wake-up control and has broad application prospects.
[0084] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.
[0085] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.
Claims
1. A mode switching circuit based on pulse signals, characterized in that, The circuit includes: Initial level output unit, outputs the initial level of the circuit in its initial state; A full-load operating mode unit is connected to the initial level output unit; A low quiescent current mode unit is connected to the initial level output unit and the full-load operating mode unit respectively, wherein the initial level causes the full-load operating mode unit to be turned on before the low quiescent current mode unit. The power output switching unit includes a first switching unit and a second switching unit. The first switching unit is connected to the full-load operating mode unit. After the first switching unit receives a first pulse signal and turns on, a level signal is applied to the full-load operating mode unit to turn it on, and the circuit enters the full-load operating mode. The second switching unit is connected to the low quiescent current mode unit. After the second switching unit receives a second pulse signal and turns on, a level signal is applied to the low quiescent current mode unit to turn it on, and the circuit enters the low quiescent current mode.
2. The circuit according to claim 1, characterized in that: The initial level output unit includes a charging capacitor, one end of which is connected to a power supply and the other end of which is connected to the full-load operating mode unit.
3. The circuit according to claim 2, characterized in that, The full-load operating mode unit includes a first NMOS transistor; The other end of the charging capacitor is connected to the gate of the first NMOS transistor. In the initial state of the circuit, after the charging capacitor is charged, it transmits a high-level signal to the gate of the first NMOS transistor, causing the gate of the first NMOS transistor to conduct.
4. The circuit according to claim 3, characterized in that, The first switching unit is connected to the gate of the first NMOS transistor; When the circuit needs to be woken up again from the low static current mode, after the first switching unit receives the first pulse signal and turns on, the high-level signal generated is transmitted to the gate of the first NMOS transistor, causing the gate of the first NMOS transistor to turn on.
5. The circuit according to claim 1, characterized in that, The low static current mode unit includes a second NMOS transistor; The second switching unit is connected to the gate of the second NMOS transistor; When the circuit needs to enter the low static current mode, after the second switching unit receives the second pulse signal and turns on, the high-level signal generated is transmitted to the gate of the second NMOS transistor, causing the gate of the second NMOS transistor to turn on.
6. The circuit according to claim 1, characterized in that, The first switching unit includes a first reset switch, and the second switching unit includes a second reset switch; One end of the first reset switch receives the first pulse signal, and the other end is connected to the full-load operating mode unit; one end of the second reset switch receives the second pulse signal, and the other end is connected to the low quiescent current mode unit.
7. The circuit according to claim 1, characterized in that, The circuit further includes: a forward conduction unit; the forward conduction unit includes a first forward conduction device and a second forward conduction device; The first forward conducting device is connected to the full-load operating mode unit and the first switching unit, respectively, and the second forward conducting device is connected to the low quiescent current mode unit and the second switching unit, respectively.
8. The circuit according to claim 7, characterized in that: The first forward conducting device includes a first diode, and the second forward conducting device includes a second diode; The anode of the first diode is connected to the first switching unit, and the cathode is connected to the full-load operating mode unit; the anode of the second diode is connected to the second switching unit, and the cathode is connected to the low quiescent current mode unit.
9. The circuit according to claim 1, characterized in that, The circuit also includes a load driving unit; The load driving unit is connected to the full-load working mode unit. After the full-load working mode unit is turned on, the circuit enters the full-load working mode, and the load driving unit drives the subsequent load.
10. A radar, characterized in that, The radar includes: a mode switching circuit based on pulse signals as described in any one of claims 1 to 9.