Arm for improving edge pollution and damage in silicon wafer polycrystalline silicon deposition process
By optimizing the structure and materials of the silicon wafer transfer arm, and by adopting a silicon wafer carrier platform with inclined surfaces and roughened treatment, as well as a polytetrafluoroethylene coating, the problems of silicon wafer contamination and damage during polycrystalline silicon deposition were solved, thereby improving the yield of silicon wafers.
Patent Information
- Application Number
- CN202422889249.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-11-26
AI Technical Summary
During the polysilicon deposition process, existing equipment arms have difficulty effectively addressing the contamination and damage to silicon wafers, especially the edges of 300mm silicon wafers, which are easily damaged and contaminated, leading to wafer scrap.
A V-shaped arm body was designed, including an inclined surface and a roughened silicon wafer carrying platform. Combined with a polytetrafluoroethylene coating, the direct contact area and friction between the silicon wafer and the arm are reduced. A limiting block is used for effective clamping, which improves the damage and contamination during the silicon wafer transfer process.
It effectively reduces contamination and scratches on silicon wafers during the polycrystalline silicon deposition process, improves the yield of silicon wafers, and reduces the scrap rate of wafers.
Smart Images
Figure CN223501838U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of semiconductor manufacturing technology, specifically relating to an arm for improving edge contamination and damage during the polycrystalline silicon deposition process of silicon wafers. Background Technology
[0002] With the development of the global semiconductor industry, the continuous reduction in device feature sizes and the continuous increase in substrate sizes have placed increasingly stringent requirements on the quality of silicon substrates. For nanoscale integrated circuits, some harmful impurities are still unintentionally introduced during the actual device manufacturing process, severely affecting device performance. Forming a clean surface region on the silicon substrate surface, free from defects such as oxygen deposits and metallic impurities, is crucial. The getter effect of silicon wafers is essential for obtaining a sufficiently wide clean region on the wafer surface. Polysilicon getter, as an external getter technique, plays a role from the very beginning of the device manufacturing process. Polysilicon gettering, as an external gettering technique, utilizes the grain boundaries of polysilicon as absorption centers for impurities. Simultaneously, the deposition temperature during polysilicon deposition coincides with the oxygen nucleation process in silicon. Therefore, using polysilicon gettering wafers as substrates for integrated circuit fabrication enhances oxygen deposition within the wafer as the processing technology progresses, resulting in an internal gettering effect. In this sense, it combines the functions of external and internal gettering, which can be termed enhanced gettering. This achieves a sufficiently wide clean area on the wafer surface, significantly improving the surface quality of the substrate. Polysilicon gettering has become the primary method for gettering substrates in Ultra Large Scale Integration (ULSI) and Very Large Scale Integration (VLSI) circuits.
[0003] In the semiconductor manufacturing industry, low-pressure chemical vapor deposition (LPCVD) is a crucial method for preparing polycrystalline silicon thin films. LPCVD typically uses pure silane gas, with deposition temperatures of 600℃–680℃ and reaction pressures of 100–400 mTorr. The low pressure increases the mean free path and diffusion constant of the reactant gas, reducing gas consumption and improving film thickness on the substrate. Furthermore, its temperature control method is simple, and the substrate can be heated more uniformly, significantly improving reliability.
[0004] Polycrystalline silicon deposition equipment is mainly a vertical furnace. The silicon wafers are placed horizontally in the furnace tube and placed in a vertical quartz boat. The quartz boat can hold more than 100 silicon wafers. The production process is as follows: (1) The equipment arm takes the silicon wafer out of the wafer box and puts it into the quartz boat; (2) The quartz boat enters the reaction chamber for film formation; (3) After film formation is completed, the quartz boat exits the reaction chamber and is cooled; (4) The equipment arm takes the silicon wafer out of the quartz boat and puts it back into the wafer box. The equipment arm is made of ceramic material, but for 300mm silicon wafers, which are double-sided polished wafers, the arm is prone to damage / contamination of the silicon wafers during the transfer process, resulting in wafer scrap. Therefore, how to reduce the damage / contamination of the silicon wafers by the arm has become an urgent problem to be solved. Utility Model Content
[0005] The purpose of this invention is to provide an arm for improving edge contamination and damage during the polycrystalline silicon deposition process of silicon wafers, in order to overcome the shortcomings of the existing technology.
[0006] The objective of this utility model is achieved through the following technical solution:
[0007] An arm for improving edge contamination and damage during polycrystalline silicon deposition on silicon wafers includes a V-shaped arm body, wherein the head of the V-shaped arm body is provided with at least one first silicon wafer support platform, and each of the two tips at the tail end is provided with at least one second silicon wafer support platform.
[0008] The upper surfaces of the first silicon wafer support platform and the second silicon wafer support platform are inclined surfaces, and their height gradually decreases from the outside to the inside;
[0009] The upper surface edge of the second silicon wafer support platform is provided with a protruding limiting block;
[0010] The upper surfaces of the first silicon wafer support platform and the second silicon wafer support platform are roughened surfaces.
[0011] Preferably, the exposed surface of the arm is coated with a material with a hardness less than that of silicon wafers.
[0012] Preferably, the material is polytetrafluoroethylene.
[0013] Preferably, the roughness Ra of the upper surfaces of the first silicon wafer support platform and the second silicon wafer support platform is 2 to 5 μm.
[0014] Preferably, the inclination of the upper surfaces of the first silicon wafer support platform and the second silicon wafer support platform is 5 to 10°.
[0015] Preferably, the first silicon wafer support platform is U-shaped.
[0016] Preferably, the second silicon wafer carrier platform is positioned near the two sharp corners of the tail end of the V-shaped arm body.
[0017] Preferably, the second silicon wafer support platform is rectangular.
[0018] Preferably, the limiting block is a right-angled triangle;
[0019] The two limiting blocks on the second silicon wafer support platform are symmetrically arranged above and below the horizontal center line of the V-shaped arm body;
[0020] The right angle of the right triangle coincides with the outer vertex of the second silicon wafer carrier platform; the interior angle α is 20-40°.
[0021] Preferably, the thickness of the arm body is greater than the maximum thickness of the second silicon wafer support platform, and the minimum thickness of the second silicon wafer support platform is greater than the thickness of the limiting block.
[0022] This application effectively improves the pollution and scratches caused to the front side of a 300mm heavily doped silicon wafer by optimizing the structure of the silicon wafer transfer arm during polycrystalline silicon deposition. Attached Figure Description
[0023] Figure 1 This is a top-view diagram of a typical arm structure;
[0024] Figure 2 yes Figure 1 The provided diagram shows the structure after the arm supports the silicon wafer.
[0025] Figure 3 yes Figure 1 Enlarged diagram of section A in the middle;
[0026] Figure 4 yes Figure 3 LL cross-section view;
[0027] Figure 5 yes Figure 1 Enlarged schematic diagram of section B in the middle;
[0028] Figure 6 yes Figure 5 MM cross-section;
[0029] Figure 7 This is the improved cross-sectional view of part A in this application;
[0030] Figure 8 This is the improved cross-sectional view of part B in this application;
[0031] Figures 9-10 This image shows the contamination and scratches on the silicon wafer after polycrystalline silicon thin film deposition using an improved forearm conveyor.
[0032] Figure 11Image showing the contamination and scratches on a silicon wafer after polycrystalline silicon thin film deposition using an improved forearm conveyor.
[0033] Explanation of reference numerals in the attached figures:
[0034] 1-Arm body; 2-Second silicon wafer support platform; 3-Limiting block; 4-First silicon wafer support platform; 5-Limiting post; 6-Silicon wafer. Detailed Implementation
[0035] Figures 1-6 This is a schematic diagram of an arm structure provided in related technologies, including a V-shaped arm body 1. The head of the V-shaped arm body 1 is provided with at least one first silicon wafer support platform 4, and each of the two tips at the tail is provided with at least one second silicon wafer support platform 2, that is, the V-shaped arm body has at least three support platforms to support the silicon wafer. The arm body is generally made of ceramic, quartz, etc., which have high hardness and are easily scratched by the silicon wafer.
[0036] To prevent the silicon wafer from shifting, a protruding limiting block 3 is provided on the upper surface edge of the second silicon wafer carrying platform 2. In addition, when the silicon wafer is placed on the arm, the device extends two limiting posts 5 to press against the silicon wafer at the head of the arm to further limit the silicon wafer. Together with the limiting blocks, they effectively clamp the silicon wafer 6 to prevent the silicon wafer from shifting during the picking and placing process.
[0037] The above-mentioned arrangement involves the bottom of the silicon wafer contacting the silicon wafer carrier platform, and the side of the silicon wafer contacting the limiting block and limiting post. The large contact area makes it easy for the arm to damage or contaminate the silicon wafer during the transfer process, resulting in wafer scrap.
[0038] Based on this, this application has optimized and improved the arm, specifically as follows: Figures 7-8 As shown, the upper surfaces of the first silicon wafer support platform 4 and the second silicon wafer support platform 2 are inclined, with the height gradually decreasing from the outside to the inside. This arrangement improves the contact between the arm and the silicon wafer from surface contact to line contact, minimizing damage to the silicon wafer caused by the arm. The inclination angle is preferably 5-10°. Furthermore, the upper surfaces of the first and second silicon wafer support platforms are roughened, such as with a frosted finish, to increase the friction between the silicon wafer and the support platform, ensuring no relative slippage occurs during transport, reducing collisions between the arm and the silicon wafer, and further reducing silicon wafer damage and contamination. The roughness Ra is preferably 2-5 μm.
[0039] Because ceramic materials are relatively hard, in order to further reduce the damage caused to the silicon wafer by the arm, the exposed surface of the arm is coated with a material with a lower hardness than the silicon wafer, such as polytetrafluoroethylene.
[0040] Preferably, the first silicon wafer support platform 4 is U-shaped. The second silicon wafer support platform 2 is rectangular, and the width of the second silicon wafer support platform 2 is preferably smaller than the width of the tip of the arm body.
[0041] The second silicon wafer carrier platform 2 is positioned at the two corners of the two tips near the tail of the V-shaped arm body, which maximizes the use of the arm body's area.
[0042] Preferably, the limiting block 3 is a right triangle; the two limiting blocks are symmetrically arranged above and below the horizontal center line of the V-shaped arm body; the right angle of the right triangle coincides with the outer vertex of the second silicon wafer support platform; the interior angle α is preferably 20 to 40°; with this arrangement, the oblique side of the limiting block can better limit the side of the silicon wafer compared to the right angle side.
[0043] Preferably, the height of the improved limiting block 3 is less than the height before the improvement, reducing the risk of the arm scraping against the existing silicon wafers on the wafer boat during wafer transfer, thus preventing scratches. Furthermore, the thickness of the arm body is greater than the maximum thickness of the second silicon wafer carrying platform, and the minimum thickness of the second silicon wafer carrying platform is greater than the thickness of the limiting block.
[0044] As verified by production practice, such as Figures 9-11 As shown, Figure 9 The surface of the silicon wafer has scratches, and the size is 0.24 mm [1]. Figure 10 The surface of the silicon wafer was contaminated, with a contamination size[1] of 1.63 mm and a contamination size[2] of 1.38 mm. Figure 11 The silicon wafer surface was free of any scratches or contamination. This demonstrates that using the improved arm for silicon wafer transfer during polycrystalline silicon thin film deposition significantly reduces wafer contamination and scratches compared to using the original arm.
[0045] Therefore, this application effectively improves the pollution and scratches caused to the front side of the silicon wafer by the arm during the polycrystalline silicon deposition process by optimizing the structure and materials of the silicon wafer transfer arm.
[0046] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the present invention. Clearly, those skilled in the art can make various alterations and modifications to the present invention without departing from its spirit and scope. Thus, if such modifications and modifications fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include such modifications and modifications.
Claims
1. An arm for improving edge contamination and damage during polycrystalline silicon deposition on silicon wafers, comprising a V-shaped arm body, wherein the head of the V-shaped arm body is provided with at least one first silicon wafer support platform, and each of the two tips at the tail end is provided with at least one second silicon wafer support platform; characterized in that, The upper surfaces of the first silicon wafer support platform and the second silicon wafer support platform are inclined surfaces, and their height gradually decreases from the outside to the inside; The upper surface edge of the second silicon wafer support platform is provided with a protruding limiting block; The upper surfaces of the first silicon wafer support platform and the second silicon wafer support platform are roughened surfaces.
2. The arm for improving edge contamination and damage during the polycrystalline silicon deposition process of silicon wafers as described in claim 1, characterized in that, The exposed surface of the arm is coated with a material with a hardness less than that of silicon wafers.
3. The arm for improving edge contamination and damage during the polycrystalline silicon deposition process of silicon wafers as described in claim 2, characterized in that, The material is polytetrafluoroethylene.
4. The arm for improving edge contamination and damage during the polycrystalline silicon deposition process of silicon wafers as described in claim 1, characterized in that, The surface roughness Ra of the upper surfaces of the first silicon wafer support platform and the second silicon wafer support platform is 2 to 5 μm.
5. The arm for improving edge contamination and damage during polycrystalline silicon deposition of silicon wafers as described in claim 1, characterized in that, The inclination of the upper surfaces of the first silicon wafer support platform and the second silicon wafer support platform is 5 to 10°.
6. The arm for improving edge contamination and damage during polycrystalline silicon deposition of silicon wafers as described in claim 1, characterized in that, The first silicon wafer support platform is U-shaped.
7. The arm for improving edge contamination and damage during polycrystalline silicon deposition of silicon wafers as described in claim 1, characterized in that, The second silicon wafer carrier platform is positioned at the corners of the two tips near the tail of the V-shaped arm body.
8. The arm for improving edge contamination and damage during polycrystalline silicon deposition of silicon wafers as described in claim 1, characterized in that, The second silicon wafer support platform is rectangular.
9. The arm for improving edge contamination and damage during polycrystalline silicon deposition of silicon wafers as described in claim 8, characterized in that, The limiting block is a right-angled triangle; The two limiting blocks on the second silicon wafer support platform are symmetrically arranged above and below the horizontal center line of the V-shaped arm body; The right angle of the right triangle coincides with the outer vertex of the second silicon wafer carrier platform; the interior angle α is 20-40°.
10. The arm for improving edge contamination and damage during polycrystalline silicon deposition of silicon wafers as described in claim 1, characterized in that, The thickness of the arm body is greater than the maximum thickness of the second silicon wafer support platform, and the minimum thickness of the second silicon wafer support platform is greater than the thickness of the limiting block.