Four-channel PCIe controller chip packaging structure

Abstract

The utility model discloses a four-channel PCIe (Peripheral Component Interconnect Express) controller chip packaging structure which comprises a circuit board, a controller chip packaging assembly, a first flash memory chip, a second flash memory chip, a third flash memory chip and a fourth flash memory chip, the controller chip packaging assembly, the first flash memory chip, the second flash memory chip, the third flash memory chip and the fourth flash memory chip are all welded on the circuit board; and the controller chip packaging assembly comprises 247 groups of pins, and the 247 groups of pins are uniformly arranged at the bottom of the BGA substrate in a 13 * 19 array. According to the utility model, the layout of the controller chip packaging assembly and the four flash memory chips is adjusted, and the layout of each pin of the controller chip packaging assembly is adjusted again, so that the circuit wiring quantity is reduced, the design difficulty and cost of an application end are reduced, the wiring is smoother due to the reasonable pin layout, the crossover probability is reduced, and the product quality is improved. And meanwhile, due to the small-size high-density pins, the welding firmness and the balanced heat dissipation are effectively improved.

Description

Technical Field

[0001] This utility model relates to the field of electronic equipment technology, and in particular to a four-channel PCIe controller chip packaging structure. Background Technology

[0002] PCIe Gen4 x4 SSDs are currently the mainstream high-speed storage products, with a single-channel x1 bandwidth of up to 16GT / s. The next-generation PCIe Gen5 x4 SSDs can achieve a single-channel x1 bandwidth of 32GT / s, while the PCIe Gen6 x4 SSDs boast a single-channel x1 bandwidth of up to 64GT / s.

[0003] Starting with PCIe Gen4, we officially entered the era of ultra-high speed. Mainstream ultra-high-speed PCIe controller chips feature a four-channel architecture and more advanced manufacturing processes, employing 12nm or even 10nm technology. Package sizes have also shrunk significantly; for example, a PCIe Gen4 x4 four-channel controller chip has a 40% smaller surface area than a PCIe Gen3 x4 four-channel controller chip. Therefore, pin density is higher, significantly increasing the difficulty of circuit board design for applications.

[0004] Secondly, traditional PCIe Gen3 x4 quad-channel controller chips often adopt an I-type layout in applications (such as...). Figure 9 (See reference). The controller chip is located near the M.2 interface, and the flash memory chips are arranged sequentially at the rear. If the circuit traces for the four channels must be of equal length—that is, AC (channel 1), AD (channel 2), BE (channel 3), and BF (channel 3) must be of equal length—the circuit density at the locations of the first and second flash memory chips is extremely high, resulting in poor electrical signals. Furthermore, the long trace lengths make them susceptible to attenuation and interference. Therefore, this conventional layout is unsuitable for PCIe Gen4 and higher read / write speeds such as PCIe Gen5 and PCIe Gen6. The limitations and drawbacks of traditional pin definitions and layouts restrict technological development and the application of ultra-high-speed storage products.

[0005] Therefore, there is an urgent need for a new four-channel PCIe controller chip packaging structure. Utility Model Content

[0006] In view of the above problems, this utility model is proposed to provide a four-channel PCIe controller chip packaging structure that overcomes or at least partially solves the above problems.

[0007] This invention provides a four-channel PCIe controller chip package structure, comprising: a circuit board, a controller chip package assembly, a first flash memory chip, a second flash memory chip, a third flash memory chip, and a fourth flash memory chip. The controller chip package assembly, the first flash memory chip, the second flash memory chip, the third flash memory chip, and the fourth flash memory chip are all soldered onto the circuit board, and the controller chip package assembly is electrically connected to the first flash memory chip, the second flash memory chip, the third flash memory chip, and the fourth flash memory chip, respectively. The third flash memory chip, the fourth flash memory chip, the first flash memory chip, and the second flash memory chip are arranged side-by-side in sequence. The controller chip package assembly is located below the area between the first flash memory chip and the fourth flash memory chip, and the trace distances between the controller chip package assembly and the first flash memory chip, the second flash memory chip, the third flash memory chip, and the fourth flash memory chip are all the same.

[0008] The controller chip package includes 247 pins, which are evenly arranged in a 13*19 array on the bottom of the BGA substrate. The 247 pins of the controller chip package are electrically connected to the circuit board.

[0009] Optionally, among the 247 groups of pins in the controller chip package assembly, pin A1 is defined as GND, pin A2 is defined as GND, pin A3 is defined as CRY_VDD, pin A4 is defined as VCCAH, pin A5 is defined as VCCAH, pin A6 is defined as GND, pin A7 is defined as P3TXN, pin A8 is defined as P3TXN, pin A9 is defined as GND, pin A10 is defined as P2TXN, pin A11 is defined as P2TXN, pin A12 is defined as GND, pin A13 is defined as P1TXN, pin A14 is defined as P1TXN, pin A15 is defined as GND, pin A16 is defined as P0TXN, pin A17 is defined as P0TXN, pin A18 is defined as GND, and pin A19 is defined as GND.

[0010] Pin B1 is defined as GND, pin B2 is defined as XIN, pin B3 is defined as GND, pin B4 is defined as VCCAH, pin B5 is defined as GND, pin B6 is defined as GND, pin B7 is defined as GND, pin B8 is defined as GND, pin B9 is defined as GND, pin B10 is defined as GND, pin B11 is defined as GND, pin B12 is defined as GND, pin B13 is defined as GND, pin B14 is defined as GND, pin B15 is defined as GND, pin B16 is defined as GND, pin B17 is defined as GND, pin B18 is defined as GND, and pin B19 is defined as GND.

[0011] Pin C1 is defined as XOUT, pin C2 as GND, pin C3 as VCCAH, pin C4 as VCCAH, pin C5 as PLP_INT#, pin C6 as CLKREQN, pin C7 as GND, pin C8 as P3RXN, pin C9 as P3RXN, pin C10 as GND, pin C11 as P2RXN, pin C12 as P2RXN, pin C13 as GND, pin C14 as P1RXN, pin C15 as P1RXN, pin C16 as GND, pin C17 as P0RXN, pin C18 as P0RXN, and pin C19 as REFCLKN.

[0012] Pin D1 is defined as GND, pin D2 as T0, pin D3 as T2, pin D4 as PERSTN, pin D5 as SMB_SCL, pin D6 as SMB_SDA, pin D7 as SMBALERT#, pin D8 as GND, pin D9 as GND, pin D10 as GND, pin D11 as GND, pin D12 as GND, pin D13 as GND, pin D14 as GND, pin D15 as GND, pin D16 as GND, pin D17 as GND, pin D18 as GND, and pin D19 as REFCLKP.

[0013] Pin E1 is defined as VCCGQ3, pin E2 as GP22, pin E3 as T3, pin E4 as T4, pin E5 as GP14, pin E6 as GP15, pin E7 as GP16, pin E8 as NC, pin E9 as NC, pin E10 as NC, pin E11 as NC, pin E12 as GP05, pin E13 as GP06, pin E14 as EX_PWD_N, pin E15 as UART_TX, pin E16 as EXRST_N, pin E17 as VPTX, pin E18 as VPTX, and pin E19 as RREF;

[0014] Pin F1 is defined as VCCFQ, pin F2 as GP21, pin F3 as NC, pin F4 as NC, pin F5 as NC, pin F6 as NC, pin F7 as NC, pin F8 as NC, pin F9 as GND, pin F10 as GND, pin F11 as GND, pin F12 as GP03, pin F13 as GP04, pin F14 as UART_RX, pin F15 as I2C_SCL, pin F16 as I2C_SDA, pin F17 as VCCF, pin F18 as VCCAH, and pin F19 as VCCAH.

[0015] Pin G1 is defined as VCCGQ2, pin G2 as VCCFQ, pin G3 as VCCFQ, pin G4 as VCCFQ, pin G5 as GP32, pin G6 as GP30, pin G7 as GP13, pin G8 as GP12, pin G9 as GND, pin G10 as GND, pin G11 as GND, pin G12 as GP11, pin G13 as GP00, pin G14 as JTD0, pin G15 as JTMS, pin G16 as JRST, pin G17 as JTD1, pin G18 as JTCK, and pin G19 as VCCGQ1.

[0016] Pin H1 is defined as F0RE, pin H2 as F0D6, pin H3 as F0D7, pin H4 as F0CLE, pin H5 as F0CE3, pin H6 as GND, pin H7 as GND, pin H8 as GND, pin H9 as GND, pin H10 as GND, pin H11 as GND, pin H12 as GND, pin H13 as GND, pin H14 as VCPY, pin H15 as F3CE0, pin H16 as F3WP, pin H17 as F3D1, pin H18 as F3D0, and pin H19 as F3DQS.

[0017] Pin J1 is defined as F0REn, pin J2 as F0D4, pin J3 as F0D5, pin J4 as F0ALE, pin J5 as F0CE2, pin J6 as VCCK, pin J7 as VCCK, pin J8 as VCCK, pin J9 as VCCK, pin J10 as VCCK, pin J11 as VCCK, pin J12 as VCPY, pin J13 as VCPY, pin J14 as VCPY, pin J15 as F3CE1, pin J16 as F3WEN, pin J17 as F3D3, pin J18 as F3D2, and pin J19 as F3DQSn;

[0018] Pin K1 is defined as F0DQS, pin K2 as F0D2, pin K3 as F0D3, pin K4 as F0WEN, pin K5 as F0CE1, pin K6 as F1CE3, pin K7 as F1CE2, pin K8 as F1CE1, pin K9 as F1CE0, pin K10 as VCCK, pin K11 as F2CE3, pin K12 as F2CE2, pin K13 as F2CE1, pin K14 as F2CE0, pin K15 as F3CE2, pin K16 as F3ALE, pin K17 as F3D5, pin K18 as F3D4, and pin K19 as F3REn;

[0019] The pin L1 is defined as F0DQS, the pin L2 as F0D0, the pin L3 as F1D1, the pin L4 as F0WP, the pin L5 as F0CE0, the pin L6 as F1CLE, the pin L7 as F1ALE, the pin L8 as F1WEN, the pin L9 as F1WP, the pin L10 as ZQCL, the pin L11 as F2CLE, the pin L12 as F2ALE, the pin L13 as F2WEN, the pin L14 as F2WP, the pin L15 as F3CE3, the pin L16 as F3CLE, the pin L17 as F3D7, the pin L18 as F3D6, and the pin L19 as F3RE.

[0020] Pin M1 is defined as GND, pin M2 as F1D7, pin M3 as F1D6, pin M4 as F1D5, pin M5 as F1D4, pin M6 as F1D3, pin M7 as F1D2, pin M8 as F1D1, pin M9 as VCCK, pin M10 as FRB, pin M11 as VCCPY, pin M12 as F2D6, pin M13 as F2D5, pin M14 as F2D4, pin M15 as F2D3, pin M16 as F2D2, pin M17 as F2D1, pin M18 as F2D0, and pin M19 as GND.

[0021] Pin N1 is defined as GND, pin N2 is defined as GND, pin N3 is defined as F1RE, pin N4 is defined as F1REn, pin N5 is defined as F1DQSn, pin N6 is defined as F1DQS, pin N7 is defined as F1D0, pin N8 is defined as VCCK, pin N9 is defined as GND, pin N10 is defined as VREF_F, pin N11 is defined as GND, pin N12 is defined as VCCPY, pin N13 is defined as F2D7, pin N14 is defined as F2RE, pin N15 is defined as F2REn, pin N16 is defined as F2DQSn, pin N17 is defined as F2DQS, pin N18 is defined as GND, and pin N19 is defined as GND.

[0022] Optionally, the circuit board is provided with multiple positioning holes.

[0023] Optionally, the circuit board is provided with multiple screw holes.

[0024] The technical solution provided in this embodiment of the utility model has at least the following technical effects or advantages:

[0025] The four-channel PCIe controller chip packaging structure described in this embodiment adjusts the layout of the controller chip packaging component and the four flash memory chips, and also readjusts the layout of each pin of the controller chip packaging component. This not only reduces the amount of circuit traces, but also lowers the design difficulty and cost of the application end. The reasonable pin layout also makes the traces smoother, reduces the probability of crossover, and improves the signal quality. At the same time, the small size and high density of pins effectively improve the soldering firmness and balanced heat dissipation.

[0026] The above description is merely an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this utility model more obvious and understandable, specific embodiments of this utility model are given below. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the four-channel PCIe controller chip packaging structure described in this utility model;

[0029] Figure 2 This is a schematic diagram of another embodiment of the four-channel PCIe controller chip packaging structure described in this utility model;

[0030] Figure 3 This is a reference schematic diagram of the pin distribution of the controller chip package assembly;

[0031] Figure 4 for Figure 3 A schematic diagram showing the pin distribution related to grounding;

[0032] Figure 5 for Figure 3 A schematic diagram showing the pinout of the PCIe interface signals;

[0033] Figure 6 for Figure 3 A schematic diagram showing the pinout of the flash memory interface;

[0034] Figure 7 for Figure 3A schematic diagram showing the pin distribution related to the crystal oscillator clock signal;

[0035] Figure 8 for Figure 3 A schematic diagram showing the pinout of the power supply.

[0036] Figure 9 This is a schematic diagram of the I-type layout controller chip packaging structure in the prior art.

[0037] Explanation of reference numerals in the attached figures:

[0038] 1. Circuit board; 2. Controller chip packaging assembly; 3. First flash memory chip; 4. Second flash memory chip; 5. Third flash memory chip; 6. Fourth flash memory chip; 7. Positioning hole; 8. Screw hole. Detailed Implementation

[0039] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings.

[0040] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The accompanying drawings show preferred embodiments of the present invention. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present invention more thorough and complete.

[0041] Unless otherwise specified, all raw materials, instruments and equipment used in this invention can be purchased from the market or prepared by existing methods.

[0042] Figure 1 This is a schematic diagram of a four-channel PCIe controller chip package structure provided in an embodiment of this utility model. (See attached diagram.) Figure 1As shown, the four-channel PCIe controller chip package structure includes a circuit board 1, a controller chip package assembly 2, a first flash memory chip 3, a second flash memory chip 4, a third flash memory chip 5, and a fourth flash memory chip 6. The controller chip package assembly 2, the first flash memory chip 3, the second flash memory chip 4, the third flash memory chip 5, and the fourth flash memory chip 6 are all soldered onto the circuit board 1, and the controller chip package assembly 2 is electrically connected to the first flash memory chip 3, the second flash memory chip 4, the third flash memory chip 5, and the fourth flash memory chip 6, respectively. The third flash memory chip 5, the fourth flash memory chip 6, the first flash memory chip 3, and the second flash memory chip 4 are arranged side-by-side in sequence. The controller chip package assembly 2 is located below the area between the first flash memory chip 3 and the fourth flash memory chip 6, and the trace distances between the controller chip package assembly 2 and the first flash memory chip 3, the second flash memory chip 4, the third flash memory chip 5, and the fourth flash memory chip 6 are all the same.

[0043] The controller chip packaging component 2, the first flash memory chip 3, the second flash memory chip 4, the third flash memory chip 5, and the fourth flash memory chip 6 form a Y-shaped layout, which can shorten the trace length.

[0044] In another embodiment of this utility model, combined with Figure 2 As shown, the third flash memory chip 5, the fourth flash memory chip 6, the controller chip package 2, the first flash memory chip 3, and the second flash memory chip 4 are arranged side by side in sequence. The controller chip package 2 is located in the middle area between the first flash memory chip 3 and the fourth flash memory chip 6. The trace distance between the controller chip package 2 and the first flash memory chip 3, the second flash memory chip 4, the third flash memory chip 5, and the fourth flash memory chip 6 is the same, thus forming a butterfly layout.

[0045] The butterfly layout places the controller chip package component 2 in the center, with the flash memory chips positioned at both ends of the controller chip, resembling butterfly wings. This layout reduces the amount of traces by more than 45%, freeing up the trace space for long and narrow hard drives (such as M.2 2280 SSDs), reducing the number of circuit board layers and lowering costs. The trace length of the butterfly layout is 57% shorter than the traditional I-type layout, and even exceeds 60% considering actual lengths due to routing difficulties.

[0046] Y-type layout is used for short and wide storage hard drives (such as extended compressed storage hard drive modules). The circuit traces are arranged in a Y-shaped, dispersed layout. This type of layout has advantages due to the short and wide board size. For controller chip package component 2 that supports butterfly layout, if it is compatible with Y-type layout, the key is that controller chip package component 2 needs to be horizontal in Y-type layout to avoid insufficient space on the short and wide board. In butterfly layout, the controller chip needs to be rotated 90°.

[0047] The appropriate method can be selected according to the actual application requirements, and this utility model does not limit this.

[0048] The first flash memory chip 3, the second flash memory chip 4, the third flash memory chip 5, and the fourth flash memory chip 6 are conventional flash memory chips of the same specifications. The controller chip packaging component 2 is connected to the four flash memory chips respectively to form a four-channel.

[0049] The controller chip package assembly 2 includes 247 pins, combined with Figure 3 As shown, this is a reference schematic diagram of the pin distribution of the controller chip package assembly 2. The 247 sets of pins are evenly arranged in a 13*19 array on the bottom of the BGA substrate, and the 247 sets of pins of the controller chip package assembly 2 are electrically connected to the circuit board 1.

[0050] In this embodiment of the utility model, the circuit board 1 is provided with a plurality of positioning holes 7, which are used to provide positioning guidance function when installed on an external structure to correct the upper and lower contact accuracy.

[0051] The circuit board 1 is provided with a plurality of screw holes 8, and the circuit board 1 can be fixedly connected to an external structure through the screw holes 8.

[0052] In this embodiment of the present invention, among the 247 groups of pins in the controller chip package assembly 2, pin A1 is defined as GND, pin A2 is defined as GND, pin A3 is defined as CRY_VDD, pin A4 is defined as VCCAH, pin A5 is defined as VCCAH, pin A6 is defined as GND, pin A7 is defined as P3TXN, pin A8 is defined as P3TXN, pin A9 is defined as GND, pin A10 is defined as P2TXN, pin A11 is defined as P2TXN, pin A12 is defined as GND, pin A13 is defined as P1TXN, pin A14 is defined as P1TXN, pin A15 is defined as GND, pin A16 is defined as P0TXN, pin A17 is defined as P0TXN, pin A18 is defined as GND, and pin A19 is defined as GND.

[0053] Pin B1 is defined as GND, pin B2 is defined as XIN, pin B3 is defined as GND, pin B4 is defined as VCCAH, pin B5 is defined as GND, pin B6 is defined as GND, pin B7 is defined as GND, pin B8 is defined as GND, pin B9 is defined as GND, pin B10 is defined as GND, pin B11 is defined as GND, pin B12 is defined as GND, pin B13 is defined as GND, pin B14 is defined as GND, pin B15 is defined as GND, pin B16 is defined as GND, pin B17 is defined as GND, pin B18 is defined as GND, and pin B19 is defined as GND.

[0054] Pin C1 is defined as XOUT, pin C2 as GND, pin C3 as VCCAH, pin C4 as VCCAH, pin C5 as PLP_INT#, pin C6 as CLKREQN, pin C7 as GND, pin C8 as P3RXN, pin C9 as P3RXN, pin C10 as GND, pin C11 as P2RXN, pin C12 as P2RXN, pin C13 as GND, pin C14 as P1RXN, pin C15 as P1RXN, pin C16 as GND, pin C17 as P0RXN, pin C18 as P0RXN, and pin C19 as REFCLKN.

[0055] Pin D1 is defined as GND, pin D2 as T0, pin D3 as T2, pin D4 as PERSTN, pin D5 as SMB_SCL, pin D6 as SMB_SDA, pin D7 as SMBALERT#, pin D8 as GND, pin D9 as GND, pin D10 as GND, pin D11 as GND, pin D12 as GND, pin D13 as GND, pin D14 as GND, pin D15 as GND, pin D16 as GND, pin D17 as GND, pin D18 as GND, and pin D19 as REFCLKP.

[0056] Pin E1 is defined as VCCGQ3, pin E2 as GP22, pin E3 as T3, pin E4 as T4, pin E5 as GP14, pin E6 as GP15, pin E7 as GP16, pin E8 as NC, pin E9 as NC, pin E10 as NC, pin E11 as NC, pin E12 as GP05, pin E13 as GP06, pin E14 as EX_PWD_N, pin E15 as UART_TX, pin E16 as EXRST_N, pin E17 as VPTX, pin E18 as VPTX, and pin E19 as RREF;

[0057] Pin F1 is defined as VCCFQ, pin F2 as GP21, pin F3 as NC, pin F4 as NC, pin F5 as NC, pin F6 as NC, pin F7 as NC, pin F8 as NC, pin F9 as GND, pin F10 as GND, pin F11 as GND, pin F12 as GP03, pin F13 as GP04, pin F14 as UART_RX, pin F15 as I2C_SCL, pin F16 as I2C_SDA, pin F17 as VCCF, pin F18 as VCCAH, and pin F19 as VCCAH.

[0058] Pin G1 is defined as VCCGQ2, pin G2 as VCCFQ, pin G3 as VCCFQ, pin G4 as VCCFQ, pin G5 as GP32, pin G6 as GP30, pin G7 as GP13, pin G8 as GP12, pin G9 as GND, pin G10 as GND, pin G11 as GND, pin G12 as GP11, pin G13 as GP00, pin G14 as JTD0, pin G15 as JTMS, pin G16 as JRST, pin G17 as JTD1, pin G18 as JTCK, and pin G19 as VCCGQ1.

[0059] Pin H1 is defined as F0RE, pin H2 as F0D6, pin H3 as F0D7, pin H4 as F0CLE, pin H5 as F0CE3, pin H6 as GND, pin H7 as GND, pin H8 as GND, pin H9 as GND, pin H10 as GND, pin H11 as GND, pin H12 as GND, pin H13 as GND, pin H14 as VCPY, pin H15 as F3CE0, pin H16 as F3WP, pin H17 as F3D1, pin H18 as F3D0, and pin H19 as F3DQS.

[0060] Pin J1 is defined as F0REn, pin J2 as F0D4, pin J3 as F0D5, pin J4 as F0ALE, pin J5 as F0CE2, pin J6 as VCCK, pin J7 as VCCK, pin J8 as VCCK, pin J9 as VCCK, pin J10 as VCCK, pin J11 as VCCK, pin J12 as VCPY, pin J13 as VCPY, pin J14 as VCPY, pin J15 as F3CE1, pin J16 as F3WEN, pin J17 as F3D3, pin J18 as F3D2, and pin J19 as F3DQSn;

[0061] Pin K1 is defined as F0DQS, pin K2 as F0D2, pin K3 as F0D3, pin K4 as F0WEN, pin K5 as F0CE1, pin K6 as F1CE3, pin K7 as F1CE2, pin K8 as F1CE1, pin K9 as F1CE0, pin K10 as VCCK, pin K11 as F2CE3, pin K12 as F2CE2, pin K13 as F2CE1, pin K14 as F2CE0, pin K15 as F3CE2, pin K16 as F3ALE, pin K17 as F3D5, pin K18 as F3D4, and pin K19 as F3REn;

[0062] The pin L1 is defined as F0DQS, the pin L2 as F0D0, the pin L3 as F1D1, the pin L4 as F0WP, the pin L5 as F0CE0, the pin L6 as F1CLE, the pin L7 as F1ALE, the pin L8 as F1WEN, the pin L9 as F1WP, the pin L10 as ZQCL, the pin L11 as F2CLE, the pin L12 as F2ALE, the pin L13 as F2WEN, the pin L14 as F2WP, the pin L15 as F3CE3, the pin L16 as F3CLE, the pin L17 as F3D7, the pin L18 as F3D6, and the pin L19 as F3RE.

[0063] Pin M1 is defined as GND, pin M2 as F1D7, pin M3 as F1D6, pin M4 as F1D5, pin M5 as F1D4, pin M6 as F1D3, pin M7 as F1D2, pin M8 as F1D1, pin M9 as VCCK, pin M10 as FRB, pin M11 as VCCPY, pin M12 as F2D6, pin M13 as F2D5, pin M14 as F2D4, pin M15 as F2D3, pin M16 as F2D2, pin M17 as F2D1, pin M18 as F2D0, and pin M19 as GND.

[0064] Pin N1 is defined as GND, pin N2 is defined as GND, pin N3 is defined as F1RE, pin N4 is defined as F1REn, pin N5 is defined as F1DQSn, pin N6 is defined as F1DQS, pin N7 is defined as F1D0, pin N8 is defined as VCCK, pin N9 is defined as GND, pin N10 is defined as VREF_F, pin N11 is defined as GND, pin N12 is defined as VCCPY, pin N13 is defined as F2D7, pin N14 is defined as F2RE, pin N15 is defined as F2REn, pin N16 is defined as F2DQSn, pin N17 is defined as F2DQS, pin N18 is defined as GND, and pin N19 is defined as GND.

[0065] In this embodiment of the utility model, Figure 4 for Figure 3 A schematic diagram showing the pin distribution related to grounding, combined with... Figure 4As shown, the GND pin is grounded and connected to the copper plating. Its adhesion is stronger than that of other pins, so GND pins are placed at the four corners of the chip (such as pins A1, A2, B1, A18, A19, B19, M1, N1, N2, M19, N18, and N19). Secondly, because the GND pin is connected to the copper plating for grounding, its heat conduction capability is also better than that of other pins. Therefore, GND pins (such as pins F9, F10, F11, G9, G10, G11, H9, H10, and H11) are placed in the middle of the chip to dissipate the heat of the controller chip to circuit board 1 for heat dissipation through the copper plating.

[0066] Figure 5 for Figure 3 A schematic diagram showing the pinout of the PCIe interface signals, combined with... Figure 5 As shown, the PCIe interface signals mainly consist of differential clock signal lines (such as pins C19 and D19), differential pair data signals (such as pins A7, A8, A10, A11, A13, A14, A16, A17, C8, C9, C11, C12, C14, C15, C17, and C18), and control signals (such as pins C5, C6, D4, D5, D6, and D7). The differential pairs are isolated by grounding the GND pins to improve anti-interference and shield against electromagnetic interference.

[0067] Figure 6 for Figure 3 A schematic diagram showing the pin distribution of the flash memory interface, combined with... Figure 6As shown, the flash memory interface pins corresponding to the four channels include: Channel 1 (e.g., pins H1, H2, H3, H4, H5, J1, J2, J3, J4, J5, K1, K2, K3, K4, K5, L1, L2, L3, L4, L5), Channel 2 (e.g., pins K9, K10, K11, K12, L9, L10, L11, L12, M2, M3, M4, M5, M6, M7, M8, N3, N4, N5, N6, N7), and Channel 3 (e.g., pins...). K11, K12, K13, K14, L11, L12, L13, L14, M12, M13, M14, M15, M16, M17, M18, N13, N14, N15, N16, N17), and channel 4 (e.g., pins H15, H16, H17, H18, H19, J15, J16, J17, J18, J19, K15, K16, K17, K18, K19, L15, L16, L17, L18, L19). Arranged sequentially and symmetrically, each channel has 20 pins. The common pins VREF_F (N10), FRB (M10), and ZQCL (L10) are placed in the middle for easy routing. DQS\DQSn (Double Data Rate pins, K1 to L1, N5 to N6, N16 to N17, H19 to J19) and RE\REn (Read Enable, enabling NV-DDR high-speed mode, H1 to J1, N3 to N4, N14 to N15, K19 to L19) are differential signals. The signal quality directly affects the read and write speed. The two pairs of differential pins are close to the edge for easy routing design. D0-D7 (L2, L3, K2, K3, J2, J3, H2, H3, M2, M3, M4, M5, M6, M7, M8, N7, M12, M13, M14, M15, M16, M17, M18, N13, H17, H18, J17, J18, K17, K18, L17, L18) are data signal lines, with signal requirements second only to the differential pairs, in the following order: WP (L4, L9, L14, H16)\WE N(K4, L8, L13, J16)\ALE(J4, L7, L12, K16)\CLE(H4, L6, L11, L16)\CE(L5, K5, J5, H5, K9, K8, K7, K6, K14, K13, K14, K11, H15, J15, K15, L15) are arranged in order, with pins requiring higher signal requirements placed closer to the edge. This reduces via routing and interference, allowing for more precise impedance control.

[0068] Figure 7 for Figure 3 A schematic diagram showing the pin distribution of the crystal oscillator clock signal, combined with... Figure 7As shown, pins XIN (B2) and XOUT (C1) are the crystal oscillator clock signals, isolated by GND pins (A1, A2, B1, B3, C2) to reduce interference. The logic analysis sampling interface (G14, G15, G16, G17, G18) is used for analyzing sample reads, and the I2C programming interface (E14, E15, E16, F14, F15, F16) is used for programmable power management chips or external encryption, and supports SPI firmware programming, etc.

[0069] Figure 8 for Figure 3 A schematic diagram showing the pinout of the power supply, combined with... Figure 8 As shown, VCCK (J6, J7, J8, J9, J10, J11, K10, M9, N7) and VCCP (H14, J12, J13, J14, M11, N12) are the core analog and digital power supplies for the controller. VCCAH (A4, A5, B4, C3, C4, F18, F19) are the power supplies for the PHY and clock circuits. VCCF (F17) is the flash memory voltage sampling pin, and VCCFQ (F1, G2, G3, G4) are the flash memory I / O power supplies. Other pins, including the built-in LDO power pins VCCGQ1 (each 9), VCCGQ2 (G1), and VCCGQ3 (E1), are arranged near the edge to facilitate the placement of filter capacitors and support single-sided component layout design (all components on the top surface).

[0070] It should be noted that, in this embodiment of the present invention, the pins A1-N19 of the controller chip package 2 are only used to indicate the location of each pin and the corresponding pin function definition. According to the actual application requirements, in other embodiments, the serial number or name of each pin can also be adaptively adjusted.

[0071] The four-channel PCIe controller chip packaging structure described in this embodiment of the present invention, by adjusting the layout of the controller chip packaging component 2 and the four flash memory chips, and at the same time readjusting the layout of each pin of the controller chip packaging component 2, not only reduces the amount of circuit traces, reduces the design difficulty and cost of the application end, but also makes the traces smoother, reduces the probability of crossover, and improves the signal quality. At the same time, the small size and high density of pins effectively improve the soldering firmness and balanced heat dissipation.

[0072] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0073] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed invention requires more features than expressly recited in each claim. Rather, as reflected in the claims, the inventive aspect lies in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0074] It should be noted that the above embodiments are illustrative of the present invention and not restrictive of the present invention, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A four-channel PCIe controller chip package structure, characterized in that, The four-channel PCIe controller chip package structure includes: a circuit board, a controller chip package assembly, a first flash memory chip, a second flash memory chip, a third flash memory chip, and a fourth flash memory chip. The controller chip package assembly, the first flash memory chip, the second flash memory chip, the third flash memory chip, and the fourth flash memory chip are all soldered onto the circuit board, and the controller chip package assembly is electrically connected to the first flash memory chip, the second flash memory chip, the third flash memory chip, and the fourth flash memory chip, respectively. The third flash memory chip, the fourth flash memory chip, the first flash memory chip, and the second flash memory chip are arranged side-by-side in sequence. The controller chip package assembly is located below the area between the first flash memory chip and the fourth flash memory chip, and the trace distances between the controller chip package assembly and the first flash memory chip, the second flash memory chip, the third flash memory chip, and the fourth flash memory chip are all the same. The controller chip package includes 247 pins, which are evenly arranged in a 13*19 array on the bottom of the BGA substrate. The 247 pins of the controller chip package are electrically connected to the circuit board.

2. The four-channel PCIe controller chip packaging structure according to claim 1, characterized in that: Of the 247 pin groups in the controller chip package, pin A1 is defined as GND, pin A2 is defined as GND, pin A3 is defined as CRY_VDD, pin A4 is defined as VCCAH, pin A5 is defined as VCCAH, pin A6 is defined as GND, pin A7 is defined as P3TXN, pin A8 is defined as P3TXN, pin A9 is defined as GND, pin A10 is defined as P2TXN, pin A11 is defined as P2TXN, pin A12 is defined as GND, pin A13 is defined as P1TXN, pin A14 is defined as P1TXN, pin A15 is defined as GND, pin A16 is defined as P0TXN, pin A17 is defined as P0TXN, pin A18 is defined as GND, and pin A19 is defined as GND. Pin B1 is defined as GND, pin B2 is defined as XIN, pin B3 is defined as GND, pin B4 is defined as VCCAH, pin B5 is defined as GND, pin B6 is defined as GND, pin B7 is defined as GND, pin B8 is defined as GND, pin B9 is defined as GND, pin B10 is defined as GND, pin B11 is defined as GND, pin B12 is defined as GND, pin B13 is defined as GND, pin B14 is defined as GND, pin B15 is defined as GND, pin B16 is defined as GND, pin B17 is defined as GND, pin B18 is defined as GND, and pin B19 is defined as GND. Pin C1 is defined as XOUT, pin C2 as GND, pin C3 as VCCAH, pin C4 as VCCAH, pin C5 as PLP_INT#, pin C6 as CLKREQN, pin C7 as GND, pin C8 as P3RXN, pin C9 as P3RXN, pin C10 as GND, pin C11 as P2RXN, pin C12 as P2RXN, pin C13 as GND, pin C14 as P1RXN, pin C15 as P1RXN, pin C16 as GND, pin C17 as P0RXN, pin C18 as P0RXN, and pin C19 as REFCLKN. Pin D1 is defined as GND, pin D2 as T0, pin D3 as T2, pin D4 as PERSTN, pin D5 as SMB_SCL, pin D6 as SMB_SDA, pin D7 as SMBALERT#, pin D8 as GND, pin D9 as GND, pin D10 as GND, pin D11 as GND, pin D12 as GND, pin D13 as GND, pin D14 as GND, pin D15 as GND, pin D16 as GND, pin D17 as GND, pin D18 as GND, and pin D19 as REFCLKP. Pin E1 is defined as VCCGQ3, pin E2 as GP22, pin E3 as T3, pin E4 as T4, pin E5 as GP14, pin E6 as GP15, pin E7 as GP16, pin E8 as NC, pin E9 as NC, pin E10 as NC, pin E11 as NC, pin E12 as GP05, pin E13 as GP06, pin E14 as EX_PWD_N, pin E15 as UART_TX, pin E16 as EXRST_N, pin E17 as VPTX, pin E18 as VPTX, and pin E19 as RREF; Pin F1 is defined as VCCFQ, pin F2 as GP21, pin F3 as NC, pin F4 as NC, pin F5 as NC, pin F6 as NC, pin F7 as NC, pin F8 as NC, pin F9 as GND, pin F10 as GND, pin F11 as GND, pin F12 as GP03, pin F13 as GP04, pin F14 as UART_RX, pin F15 as I2C_SCL, pin F16 as I2C_SDA, pin F17 as VCCF, pin F18 as VCCAH, and pin F19 as VCCAH. Pin G1 is defined as VCCGQ2, pin G2 as VCCFQ, pin G3 as VCCFQ, pin G4 as VCCFQ, pin G5 as GP32, pin G6 as GP30, pin G7 as GP13, pin G8 as GP12, pin G9 as GND, pin G10 as GND, pin G11 as GND, pin G12 as GP11, pin G13 as GP00, pin G14 as JTD0, pin G15 as JTMS, pin G16 as JRST, pin G17 as JTD1, pin G18 as JTCK, and pin G19 as VCCGQ1. Pin H1 is defined as F0RE, pin H2 as F0D6, pin H3 as F0D7, pin H4 as F0CLE, pin H5 as F0CE3, pin H6 as GND, pin H7 as GND, pin H8 as GND, pin H9 as GND, pin H10 as GND, pin H11 as GND, pin H12 as GND, pin H13 as GND, pin H14 as VCPY, pin H15 as F3CE0, pin H16 as F3WP, pin H17 as F3D1, pin H18 as F3D0, and pin H19 as F3DQS. Pin J1 is defined as F0REn, pin J2 as F0D4, pin J3 as F0D5, pin J4 as F0ALE, pin J5 as F0CE2, pin J6 as VCCK, pin J7 as VCCK, pin J8 as VCCK, pin J9 as VCCK, pin J10 as VCCK, pin J11 as VCCK, pin J12 as VCPY, pin J13 as VCPY, pin J14 as VCPY, pin J15 as F3CE1, pin J16 as F3WEN, pin J17 as F3D3, pin J18 as F3D2, and pin J19 as F3DQSn; Pin K1 is defined as F0DQS, pin K2 as F0D2, pin K3 as F0D3, pin K4 as F0WEN, pin K5 as F0CE1, pin K6 as F1CE3, pin K7 as F1CE2, pin K8 as F1CE1, pin K9 as F1CE0, pin K10 as VCCK, pin K11 as F2CE3, pin K12 as F2CE2, pin K13 as F2CE1, pin K14 as F2CE0, pin K15 as F3CE2, pin K16 as F3ALE, pin K17 as F3D5, pin K18 as F3D4, and pin K19 as F3REn; The pin L1 is defined as F0DQS, the pin L2 as F0D0, the pin L3 as F1D1, the pin L4 as F0WP, the pin L5 as F0CE0, the pin L6 as F1CLE, the pin L7 as F1ALE, the pin L8 as F1WEN, the pin L9 as F1WP, the pin L10 as ZQCL, the pin L11 as F2CLE, the pin L12 as F2ALE, the pin L13 as F2WEN, the pin L14 as F2WP, the pin L15 as F3CE3, the pin L16 as F3CLE, the pin L17 as F3D7, the pin L18 as F3D6, and the pin L19 as F3RE. Pin M1 is defined as GND, pin M2 as F1D7, pin M3 as F1D6, pin M4 as F1D5, pin M5 as F1D4, pin M6 as F1D3, pin M7 as F1D2, pin M8 as F1D1, pin M9 as VCCK, pin M10 as FRB, pin M11 as VCCPY, pin M12 as F2D6, pin M13 as F2D5, pin M14 as F2D4, pin M15 as F2D3, pin M16 as F2D2, pin M17 as F2D1, pin M18 as F2D0, and pin M19 as GND. Pin N1 is defined as GND, pin N2 is defined as GND, pin N3 is defined as F1RE, pin N4 is defined as F1REn, pin N5 is defined as F1DQSn, pin N6 is defined as F1DQS, pin N7 is defined as F1D0, pin N8 is defined as VCCK, pin N9 is defined as GND, pin N10 is defined as VREF_F, pin N11 is defined as GND, pin N12 is defined as VCCPY, pin N13 is defined as F2D7, pin N14 is defined as F2RE, pin N15 is defined as F2REn, pin N16 is defined as F2DQSn, pin N17 is defined as F2DQS, pin N18 is defined as GND, and pin N19 is defined as GND.

3. The four-channel PCIe controller chip packaging structure according to claim 1, characterized in that: The circuit board has multiple positioning holes.

4. The four-channel PCIe controller chip packaging structure according to claim 1, characterized in that: The circuit board has multiple screw holes.

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