Computing system, network equipment, distributed network cluster system and PCB (Printed Circuit Board) computing board card

Abstract

The utility model provides a computing system, network equipment, a distributed network cluster system and a PCB computing board card, and the computing system comprises a mainboard which comprises a first expansion bus interface; the DPU waste chip acceleration card is connected to the first expansion bus interface, the DPU waste chip acceleration card comprises an independent CPU subsystem and an acceleration engine, the CPU subsystem is normal, the acceleration engine has a fault, so that the DPU waste chip acceleration card is used as a CPU daughter card of a single board, and the DPU waste chip acceleration card is connected to the first expansion bus interface. The CPU subsystem and the acceleration engine have power supply and clock systems that are independent of each other. According to the technical scheme provided by the invention, the inherent CPU subsystem in the DPU waste piece can be reused as a computing node of other equipment, so that the waste is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a computing system, a network device, a distributed network cluster system and a PCB computing board card. BACKGROUND

[0002] DPU (Data Processing Unit) is a special processor constructed with data as the main structure, which supports infrastructure layer resource virtualization service by using software definition technology route. The core problem to be solved by DPU is to reduce the cost and increase the efficiency of infrastructure, and to offload the load that cannot be processed by CPU and GPU to special DPU, so as to improve the efficiency of the whole computing system and reduce the total cost of ownership of the whole system. The most direct role of DPU is to act as an offload engine of CPU, to take over network virtualization, hardware resource pooling and other infrastructure layer services, and to release the computing power of CPU to the upper layer application.

[0003] DPU is composed of CPU subsystem and self-developed acceleration engine subsystem. The CPU subsystem is mainly composed of commercial IP. Since the commercial IP has been used and iterated in the market for a long time, the various abnormal scene defects of the IP have been exposed and solved in the long-term application, and the probability of problems is relatively low. Since the self-developed engine is completely designed and produced initially, although it has undergone a strict test process of a sample, various defects will still be exposed in the SLT screening test after mass production, resulting in a decrease in the usability of the chip in the original designed application scene. Some chips with small defects can still be used as low-end products, and for the products with large defects, which cannot be used in the original scene, such chips with large defects are often forced to be abandoned, resulting in great waste.

[0004] Therefore, a technical solution is needed to solve the waste problem of DPU scrap chips. SUMMARY

[0005] The present application aims to provide a computing system, a network device, a distributed network cluster system and a PCB computing board card. For the unique architecture composition of DPU chip, after the defect of DPU self-developed engine subsystem causes the chip to be scrapped, a new recycling method is proposed to recycle the scrapped chip and use the inherent CPU subsystem of the DPU chip as a computing node of other devices for reuse.

[0006] According to an aspect of the present application, a computing system is provided, characterized in that it comprises:

[0007] a mainboard, wherein the mainboard comprises a first expansion bus interface;

[0008] The DPU waste chip accelerator card is connected to the first expansion bus interface.

[0009] The DPU waste chip accelerator card includes an independent CPU subsystem and an acceleration engine. The CPU subsystem is normal, but the acceleration engine is faulty. Therefore, the DPU waste chip accelerator card is used as a CPU daughter card on a single board. The CPU subsystem and the acceleration engine have independent power supply and clock systems.

[0010] According to some embodiments, the first extended bus interface includes a PCIe bus interface.

[0011] According to some embodiments, the DPU waste accelerator card also includes a USB interface and / or an I2C interface.

[0012] According to one aspect of this application, a network device is provided, the network device comprising:

[0013] Board-level switching chips;

[0014] The motherboard, the spare board, and multiple line cards are interconnected through the board-level switching chip. The motherboard, the spare board, and the multiple line cards each include a DPU waste chip acceleration card inserted as a CPU daughter card on a single board.

[0015] The DPU waste chip accelerator card includes an independent CPU subsystem and an acceleration engine. The CPU subsystem is normal, while the acceleration engine is faulty. The CPU subsystem and the acceleration engine have independent power supply and clock systems.

[0016] According to some embodiments, the DPU waste chip accelerator card is connected to the motherboard, the spare board, or the plurality of line cards via a PCIe bus interface.

[0017] According to some embodiments, the DPU waste accelerator card also includes a USB interface and / or an I2C interface.

[0018] According to one aspect of this application, a distributed network cluster system is proposed, the distributed network cluster system comprising a plurality of the aforementioned network devices.

[0019] According to some embodiments, multiple network devices are interconnected via switches.

[0020] According to one aspect of this application, a PCB computing board is provided, characterized in that it comprises:

[0021] PCB board;

[0022] A CPU unit, comprising multiple DPU bare chips linked together as computing units.

[0023] The DPU bare die includes an independent CPU subsystem and an acceleration engine, the CPU subsystem is normal, the acceleration engine has a fault, and the CPU subsystem and the acceleration engine have independent power supply and clock systems from each other.

[0024] According to some embodiments, the DPU bare die has a USB interface and / or an I2C interface.

[0025] According to some embodiments, the DPU chip abandoned due to the fault of the acceleration engine but with a normal CPU subsystem function is reused by the computing system, which significantly reduces hardware waste and manufacturing cost. The DPU bare die card is connected to the existing system as a computing resource by using a standard expansion interface (such as PCIe) without the need for customized mainboards, and is deployed flexibly.

[0026] According to some embodiments, the design of the network device uses the chip with a normal CPU subsystem function but a fault acceleration engine in the DPU bare die acceleration card as a CPU daughter card inserted into the mainboard, standby board and multiple line boards, and realizes interconnection through the board-level exchange chip. The mainboard and the standby board are connected through the exchange chip, which ensures that the standby board can seamlessly take over the task when the main control board fails, and improves the fault tolerance and reliability of the system. The CPU subsystem and the acceleration engine on each DPU bare die acceleration card have independent power supply and clock systems, which not only helps to isolate the fault area, but also ensures the stable operation of other components when a local problem occurs.

[0027] It should be understood that the above general description and the following detailed description are only exemplary and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced.

[0029] Figure 1 A schematic diagram of the DPU architecture according to the present example embodiment is shown.

[0030] Figure 2 A schematic diagram of the DPU bare die for a computing system according to an example embodiment is shown.

[0031] Figure 3 A schematic diagram of the DPU bare die for a network device according to an example embodiment is shown.

[0032] Figure 4 A schematic diagram of the DPU bare die for a distributed network cluster system according to an example embodiment is shown. DETAILED DESCRIPTION

[0033] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views and, thus, description of the same elements will not be repeated.

[0034] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the subject matter. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods.

[0035] The block diagrams in the drawings show functions and functionality rather than the structure of their implementations. Implementations of the functions and functionality can be implemented in software, hardware, firmware, or a combination thereof. In one example, the functions and functionality can be implemented in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0036] The flow diagrams in the drawings show example sequences of operations, but not all of the operations and / or steps can be required in other implementations. For example, some operations and / or steps can be combined or omitted, and other operations and / or steps can be added. The order in which the operations and / or steps are presented can be changed.

[0037] It should be understood that, although terms such as first, second, third, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Thus, a first component discussed below can be called a second component without departing from the teachings of the present disclosure. As used herein, the term "and / or" includes all combinations of associated items in the associated list.

[0038] DPU is a special processor constructed based on data, which supports infrastructure layer resource virtualization service by using software definition technology route. The core problem to be solved by DPU is to reduce the cost and increase the efficiency of infrastructure, that is, to offload the load that cannot be processed by CPU and GPU to special DPU, so as to improve the efficiency of the whole computing system and reduce the total cost of ownership of the whole system. The most direct role of DPU is to act as an offload engine of CPU, to take over the infrastructure layer services such as network virtualization and hardware resource pooling, and to release the computing power of CPU to the upper layer application.

[0039] To achieve the above object, it can be seen that two important components of the DPU, one is the CPU subsystem part mainly composed of CPU cores, and the other is the self-developed engine part for realizing acceleration processing of data resources; wherein, each core in the CPU subsystem, the interconnection bus and various IPs are mature products purchased from manufacturers. The acceleration engine part of the data is mainly self-developed, and the design of the self-developed acceleration engine is completed on the basis of close combination of software and hardware.

[0040] Since the CPU subsystem is mainly composed of commercial IPs purchased, and the various abnormal scene defects of the IPs have been exposed and solved in the long-term application, the probability of problems is relatively low. Compared with the commercial IPs, the self-developed engine is completely designed and produced initially, although the wafer has undergone a strict test process, but since it has not undergone large-scale application iteration, defects will be exposed in the SLT screening test after large-scale production, resulting in reduced usability of the chip in the original designed application scene. Some chips with small defects can continue to be used as low-end products, but there are still some chips with large defects that cannot be used in the original scene, and these chips with large defects are often forced to be discarded because they cannot be used as DPU, resulting in great waste.

[0041] Therefore, the application provides a computing system, a network device, a distributed network cluster system and a PCB computing board. For the specific architecture of the DPU chip, after the DPU self-developed engine subsystem produces defects to cause the chip to be discarded, a new recycling method is proposed to recycle the discarded chip and use the inherent CPU subsystem of the DPU chip as a computing node of other devices for reuse.

[0042] Before describing the embodiments of the application, some terms or concepts related to the embodiments of the application are explained and described.

[0043] DPU (Data Processing Unit, data processing unit) is a special processor in the field of data centers and high-performance computing, which aims to solve the problems of modern data centers in processing network, storage and security. The DPU improves efficiency and performance by offloading the workload of the main CPU, allowing the CPU of the server to focus on running application programs.

[0044] SLT (System Level Test, system level test) is a high-level test method for the chip to be tested, which simulates the working state of the chip in its final use environment.

[0045] The example embodiments of the application will be described below with reference to the accompanying drawings.

[0046] Figure 1A schematic diagram of the DPU architecture composition according to this example embodiment is shown.

[0047] According to some embodiments, see Figure 1 The DPU comprises a central processing unit (CPU) subsystem and an acceleration engine subsystem. The CPU subsystem is primarily procured, while the acceleration engine subsystem is mainly self-developed. The CPU subsystem consists of a central processing unit and multiple functional modules (commercial IP modules). It is responsible for performing general-purpose computing tasks and managing data exchange with external memory.

[0048] The acceleration engine subsystem includes a routing engine (RPE), a virtualization engine (VPE), and a data processing engine (DPE). RPE is used to accelerate the forwarding and processing of network packets. VPE is used to support various virtualization technologies, improve resource utilization and security, and DPE is optimized for specific types of data processing tasks, such as compression and encryption. The acceleration engine subsystem is composed of three self-developed processing units, which focus on improving the performance of specific application areas.

[0049] The central processing unit subsystem and the acceleration engine subsystem each have their own independent circuit power supply system. The two subsystems are powered separately and use different phase-locked loops (PLLs) to ensure the stability of their respective operations and to ensure that they do not interfere with each other.

[0050] This design, which separates the computing subsystem and the acceleration subsystem, not only improves the flexibility and scalability of the DPU architecture but also allows for the optimization of these two subsystems according to the needs of different application scenarios. Simultaneously, through reasonable hardware configuration and interconnection mechanisms, it ensures the stable and efficient operation of the entire system.

[0051] The separate design of the computing subsystem and acceleration subsystem in the DPU allows for more flexible customization and optimization of the acceleration engine subsystem to meet the needs of specific application scenarios without affecting the general computing component. Because the two subsystems are relatively independent, they can be upgraded and expanded separately according to actual needs, thereby improving the overall system performance. It also effectively reduces mutual interference between the two subsystems, improving the overall system stability and reliability.

[0052] During the single-chip testing (SLT) screening process after actual mass production, defects are often found in the self-developed engine subsystem of some DPU chips, while their CPU subsystem remains intact. Since these chips cannot fully utilize the intended functions of the DPU, they are usually discarded. However, considering the characteristics of this special architecture, this technical solution proposes a method for reusing these "discarded" DPU chips.

[0053] The DPU chips with defects in the self-developed engine subsystem but intact CPU subsystems are identified and reused as independent CPU computing units. A novel computing system is designed that allows the aforementioned recycled DPU chips to be installed in this system and can be smoothly inserted into the motherboards of various servers or computing devices for use as independent computing nodes.

[0054] According to the example implementation, based on the architecture of DPU, discarded DPU chips are reused. The recycled DPU chips are used as CPU subsystems, DPU cards are inserted into single boards as computing nodes, and these computing nodes are applied in various cluster devices, such as using them as computing nodes in a manner similar to GPUs, or as CPU computing processing nodes for each single board in network cluster devices. In these ways, discarded DPU chips are reused.

[0055] Figure 2 This diagram illustrates the architecture of a computing system based on an example embodiment of a DPU waste chip.

[0056] See Figure 2 According to an example embodiment, the computing system includes a motherboard, which includes a first expansion bus interface and a DPU (Discarded Processing Unit) accelerator card. The DPU accelerator card is connected to the first expansion bus interface. The DPU accelerator card includes an independent CPU subsystem and an acceleration engine. The CPU subsystem is functioning normally, but the acceleration engine is malfunctioning. Therefore, the DPU accelerator card is used as a CPU daughter card on a single board. The CPU subsystem and the acceleration engine have independent power supply and clock systems. The first expansion bus interface includes a PCIe bus interface. The DPU accelerator card also includes a USB interface and / or an I2C interface.

[0057] In some embodiments, the DPU card is designed as a CPU daughter card for a compute node. The DPU card connects to the motherboard via a standard PCIe slot. PCIe is used to connect various expansion cards and devices within the computer. In this way, the DPU card can be easily integrated into existing hardware platforms and exchange data efficiently with other devices. Because the DPU card is inserted through a PCIe slot, the number of DPU cards can be flexibly increased or decreased according to actual needs to meet different computing requirements. For example, in scenarios requiring higher computing power, multiple DPU cards can be inserted to improve overall performance.

[0058] The CPU subsystem of the DPU card has independent power supply and PLL. The CPU subsystem on the DPU card has its own independent power supply circuitry, allowing it to operate stably without relying on other parts of the motherboard. The CPU subsystem on the DPU card uses its own PLL to generate the necessary clock signals, ensuring the stability and accuracy of the CPU subsystem under high load conditions and avoiding clock synchronization issues with other system components. This design helps reduce power supply interference and ensures the performance and stability of the CPU subsystem.

[0059] The CPU subsystem on the DPU card is used as the CPU daughter card on the board, undertaking the main computing tasks. Although the self-developed engine subsystem may have defects, a fully functional CPU subsystem can still provide powerful general-purpose computing capabilities.

[0060] The architecture of this embodiment, which uses the DPU card as the CPU daughter card of the system computing node, allows multiple DPU cards to communicate and coordinate their work through the PCI bus on the motherboard, jointly completing complex computing tasks. This not only improves the system's computing power but also enhances its flexibility and scalability.

[0061] In some implementations, a single host can achieve parallel computing using multiple DPU cards. Each DPU card acts as an independent computing node, exchanging data and collaborating with the host and other DPU cards via the PCIe bus. This design is particularly suitable for applications requiring significant computing resources, such as big data analytics, machine learning, and high-performance computing.

[0062] This embodiment reuses discarded DPU chips as CPU daughter cards for computing nodes, effectively reducing resource waste and providing additional computing power to existing systems. This design fully utilizes the intact CPU subsystem within the DPU chip, achieving efficient computing node expansion through independent power supply and PLL, as well as a flexible PCI interface. With continuous technological development and improvement, this innovative reuse method is expected to be widely applied in more fields, promoting the advancement and sustainable development of computing technology.

[0063] Figure 3 This diagram illustrates the architecture of a network device using a DPU waste chip according to an example embodiment.

[0064] For DPUs with defects in their self-developed engine subsystems but intact CPU subsystems, these reused DPU chips can be deployed in a cluster environment as GPU computing nodes to execute tasks requiring significant CPU resources. They can also be used as CPU processing nodes in network cluster devices to enhance network service performance, such as packet processing speed and traffic management.

[0065] See Figure 3 According to an example embodiment, the network device includes a board-level switching chip, a motherboard, a backup board, and multiple line cards interconnected through the board-level switching chip. The motherboard, the backup board, and the multiple line cards each include a DPU (Dead Processing Unit) accelerator card inserted as a CPU daughter card on a single board. The DPU accelerator card includes an independent CPU subsystem and an acceleration engine. The CPU subsystem is functioning normally, while the acceleration engine is faulty. The CPU subsystem and the acceleration engine have independent power supply and clock systems.

[0066] According to some embodiments, the DPU waste chip accelerator card is connected to the motherboard, the spare board, or the plurality of line cards via a PCIe bus interface. The DPU waste chip accelerator card also includes a USB interface and / or an I2C interface.

[0067] Figure 4 This diagram illustrates the architecture of a distributed network cluster system using discarded DPU chips according to an example embodiment.

[0068] According to some embodiments, see Figure 4 This paper illustrates a distributed network cluster system architecture that reuses discarded DPU chips as CPU daughter cards for various network device boards. The distributed network cluster system includes multiple... Figure 3 The network devices in the system are interconnected via switches.

[0069] The network cluster equipment cluster architecture includes racks, primary and backup boards, and line cards. Within the rack, interconnection between boards is achieved through switching chips to ensure efficient data transmission within the rack. Multiple racks are interconnected through switches to form a large distributed cluster system, enabling cross-rack data transmission and collaborative work.

[0070] Within each rack, the primary and backup boards are used for control plane configuration management and management plane data synchronization. The DPU card's CPU subsystem is used as a CPU daughter card inserted into the board, acting as a central node to handle large data volume synchronization and manage the entire cluster rack.

[0071] Each rack also contains multiple line cards, primarily responsible for data plane processing and forwarding. On the line card side, the CPU subsystem of the DPU card can function as a CPU daughter card, mainly handling data plane processing and forwarding tasks. As a distributed management sub-node, the line card plays a crucial role in bridging the gap between the motherboard and the data plane, ensuring efficient data transmission within the cluster system by synchronizing with the motherboard to manage data forwarding. For example, a 128-port switch might contain multiple daughter cards inserted into the switch to provide external services. These daughter cards are removable; for instance, a 16x8-port switch could consist of eight line cards, each providing 16 ports.

[0072] As shown in the diagram, each rack contains multiple line cards, and each line card is equipped with a CPU subsystem of a DPU card as its CPU daughter card. These line cards are interconnected through switches within the rack and work in conjunction with the primary and backup boards. Multiple racks are also interconnected through switches to form a large distributed cluster system.

[0073] According to some embodiments, data enters the line card from the external network and is initially processed and forwarded by the DPU card CPU subsystem on the line card. The processed data is then transmitted to the primary and backup boards via the rack switch, where the DPU card CPU subsystems on the primary and backup boards perform further management and synchronization. If cross-rack transmission is required, the data is transmitted to the target rack via the inter-rack switch, and then finally processed and forwarded by the line card within the target rack.

[0074] This embodiment reuses discarded DPU chips as CPU daughter cards for various network device boards, effectively improving the computing power and processing efficiency of network devices while reducing resource waste and enhancing overall system performance and stability. This innovative design fully utilizes the intact CPU subsystem within the DPU chip, playing a crucial role in the cluster structure of backbone router devices and driving the advancement and sustainable development of network technology.

[0075] In addition, discarded DPU chips are used as dies to form multi-chip modules. In particular, for chips with defects in the self-developed engine subsystem but intact CPU subsystem, they are directly packaged into PCB boards containing multiple CPUs to form computing power.

[0076] According to some embodiments, a PCB computing board includes a PCB board and a CPU unit, wherein the CPU unit includes multiple DPU bare chips linked together as computing units. Each DPU bare chip includes an independent CPU subsystem and an acceleration engine. The CPU subsystem is functioning normally, while the acceleration engine is faulty. The CPU subsystem and the acceleration engine have independent power supply and clock systems. Each DPU bare chip has a USB interface and / or an I2C interface.

[0077] This solution aims to reuse the intact parts of a defective DPU chip—the CPU subsystem—and integrate them as a separate computing unit into a new hardware platform, thereby creating a PCB board with powerful computing capabilities. Different functional modules (such as CPU cores, GPU cores, accelerators, etc.) are designed as independent chiplets, and then these chiplets are integrated into a single package using high-speed interconnect technology to form a complete system.

[0078] This approach not only effectively recycles and reuses DPU chip resources that would otherwise be discarded, but also creates a more powerful and flexible computing platform than traditional monolithic designs. This not only helps reduce production costs and improve resource utilization, achieving higher performance and efficiency through modular design and packaging technologies, but also demonstrates how to address the ever-increasing computing demands through innovative modifications to existing technologies.

[0079] Based on this technical solution, it can be further expanded by considering compatibility scenarios for the independent application of the CPU subsystem after the chip is completed during the initial design phase of the DPU chip design. This will facilitate more convenient application scenarios for the subsequent compatible use of the CPU subsystem. That is, when designing the DPU, there may not be many peripheral interfaces reserved. However, if the design considers that the CPU subsystem will be sold as a separate computing unit in the future, more interfaces will be reserved, such as USB ports and I2C.

[0080] Those skilled in the art will clearly understand that the terms "unit" and "module" in this specification refer to hardware capable of performing a specific function independently or in conjunction with other components.

[0081] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0082] In the several embodiments provided by this utility model, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0083] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0084] Exemplary embodiments of the present invention have been specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, arrangements, or implementation methods described herein; rather, the present invention is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended provisions.

Claims

1. A computing system, characterized in that, include: Motherboard, the motherboard including a first expansion bus interface; The DPU scrap accelerator card is connected to the first expansion bus interface. The DPU waste chip accelerator card includes an independent CPU subsystem and an acceleration engine. The CPU subsystem is normal, but the acceleration engine is faulty. Therefore, the DPU waste chip accelerator card is used as a CPU daughter card on a single board. The CPU subsystem and the acceleration engine have independent power supply and clock systems.

2. The computing system according to claim 1, characterized in that, The first expansion bus interface includes a PCIe bus interface.

3. The computing system according to claim 1, characterized in that, The DPU waste chip accelerator card also includes a USB interface and / or an I2C interface.

4. A network device, characterized in that, include: Board-level switching chips; The motherboard, the spare board, and multiple line cards are interconnected through the board-level switching chip. The motherboard, the spare board, and the multiple line cards each include a DPU waste chip acceleration card inserted as a CPU daughter card on a single board. The DPU waste chip accelerator card includes an independent CPU subsystem and an acceleration engine. The CPU subsystem is normal, while the acceleration engine is faulty. The CPU subsystem and the acceleration engine have independent power supply and clock systems.

5. The network device according to claim 4, characterized in that, The DPU waste chip accelerator card is connected to the motherboard, the spare board, or the multiple line cards via a PCIe bus interface.

6. The network device according to claim 4, characterized in that, The DPU waste chip accelerator card also includes a USB interface and / or an I2C interface.

7. A distributed network cluster system, characterized in that, It includes multiple network devices according to any one of claims 4-6.

8. The distributed network cluster system according to claim 7, characterized in that, Multiple network devices are interconnected via a switch.

9. A PCB computing board, characterized in that, include: PCB board; A CPU unit, comprising multiple DPU bare chips linked together as computing units. The DPU bare die includes an independent CPU subsystem and an acceleration engine. The CPU subsystem is normal, while the acceleration engine is faulty. The CPU subsystem and the acceleration engine have independent power supply and clock systems.

10. The PCB computing board according to claim 9, characterized in that, The DPU bare chip has a USB interface and / or an I2C interface.

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