Carrier for chip annealing

Abstract

The utility model relates to the technical field of chip annealing, in particular to a carrier for chip annealing. Comprising a carrier body, the carrier body is provided with a material box-shaped bare chip groove, and the bare chip groove comprises a plurality of concave grids used for placing chips; the wafer slot is arranged on the carrier body in an opening shape. According to the utility model, through providing a material box-shaped structure with a plurality of concave grids, an annealing space is provided for a large number of bare chips, and at the same time, the carrier is provided with the wafer grooves, so that the carrier can simultaneously complete the annealing process of annealing the whole wafer and the scribed bare chips.

Description

Technical Field

[0001] This utility model relates to the field of chip annealing technology, specifically to a carrier for chip annealing. Background Technology

[0002] Annealing involves heating the chip to a specific temperature, holding it for a period of time, and then slowly cooling it. After the chip's lifespan is controlled, high-temperature annealing is used to repair defects and improve its performance and stability. It also effectively eliminates internal stresses generated during the chip's manufacturing process due to various factors such as high temperature, high pressure, and chemical corrosion, thereby reducing the impact of these stresses on the chip's performance, stability, and lifespan. Temperature control and timing throughout the annealing process are crucial and directly affect the quality of the finished chip. Excessively high temperatures or excessively long annealing times may damage the chip, while excessively low temperatures or insufficient annealing times will not adequately eliminate stress.

[0003] Currently used annealing equipment often results in uneven heat distribution across different areas of the wafer during the heating phase. When packaging modules, where high chip performance consistency is required, this issue sometimes necessitates dicing the wafer before annealing to minimize its impact.

[0004] Currently, the carriers used in chip annealing equipment can only anneal entire wafers, and cannot anneal bare chips after dicing. To anneal bare chips, they must be manually removed and placed on the inner wall of a quartz paddle, which carries the risk of chip scratches and uneven heating of the bare chips during annealing. Utility Model Content

[0005] The purpose of this utility model is to provide a carrier for chip annealing, thereby solving the above-mentioned technical problems;

[0006] The technical problem solved by this utility model can be achieved by the following technical solution:

[0007] A carrier for chip annealing, comprising,

[0008] The carrier body has a raw chip recess in the shape of a material box, and the raw chip recess includes a plurality of recessed compartments for placing chips;

[0009] The wafer slot is provided in an open shape on the carrier body.

[0010] Preferably, the bare chip recesses and the wafer slots are evenly distributed along the length of the carrier body, and there is at least one bare chip recess between adjacent wafer slots.

[0011] Preferably, the vehicle body includes an upper platform for setting the recessed compartment and baffles located on both sides of the upper platform, at least a portion of the baffles being at a horizontal height higher than the upper platform.

[0012] Preferably, the wafer slot includes a through slot extending through the upper platform and a first groove embedded in the stop bar.

[0013] Preferably, the front and rear sides of the vehicle body are respectively provided with support frames, and at least a portion of the support frames are at a horizontal height higher than the horizontal height of the upper platform.

[0014] Preferably, each of the bare chip recesses has a single row of recessed grids, the recessed grids are distributed along the width direction of the carrier body, and the setting direction of the wafer slot is consistent with the distribution direction of the recessed grids.

[0015] Preferably, the bare die recesses and the wafer slots are distributed sequentially at intervals, with one bare die recess between adjacent wafer slots and one wafer slot between adjacent bare die recesses.

[0016] Preferably, it also includes a connecting rod, which connects the support frame on the front side of the vehicle body to the support frame on the rear side.

[0017] Preferably, the wafer slot further includes a second groove into which the connecting rod is embedded.

[0018] Preferably, the projection of the second groove toward the upper platform is located within the area of ​​the through groove.

[0019] The beneficial effects of this utility model are as follows: By adopting the above technical solution, this utility model provides an annealing space for a large number of bare chips by providing a box-like structure with multiple recessed grids, and at the same time, it is provided with a wafer groove, so that the carrier can simultaneously complete the annealing process of the whole wafer and the diced bare chips. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the chip annealing carrier in an embodiment of this utility model.

[0021] In the attached diagram: 1. Carrier body; 11. Stop bar; 12. Support frame; 13. Connecting rod; 2. Bare chip recess; 3. Wafer slot; 31. Through slot; 32. First slot; 33. Second slot. Detailed Implementation

[0022] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0023] It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0024] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.

[0025] A carrier for chip annealing, comprising,

[0026] The carrier body 1 has a raw chip recess 2 in the shape of a material box, and the raw chip recess 2 includes a plurality of recessed compartments for placing chips.

[0027] The wafer slot 3 is provided in an open shape on the carrier body 1.

[0028] Specifically, the chip annealing carrier provided by this utility model allows for the placement of bare chips for annealing processes.

[0029] The existing wafer-placement carrier is modified by replacing the original wafer-placement recesses with a box-like structure with multiple recessed compartments, providing annealing space for a large number of bare chips. At the same time, some wafer recesses are retained, allowing the carrier to complete the annealing process for both wafers and bare chips simultaneously.

[0030] This utility model mainly includes a bare chip groove 2 and a wafer slot 3 provided on the carrier body 1. The bare chip groove 2 has a material box-like structure, which can be used to place a single bare chip after dicing. The size of each material box hole can be customized according to actual production needs.

[0031] Wafer slot 3 can accommodate an entire wafer. In this embodiment, the size of wafer slot 3 is matched to a 6-inch wafer.

[0032] The annealing process of this utility model is as follows: the operator transfers the bare chip in the pre-prepared material box to the recessed compartment of the carrier platform using tools such as a suction pen, and then completes the annealing operation according to the standard annealing process.

[0033] More specifically, the vehicle body 1 is made of quartz material.

[0034] In a preferred embodiment, the bare chip recess 2 and the wafer slot 3 are evenly distributed along the length direction of the carrier body 1, and there is at least one bare chip recess 2 between adjacent wafer slots 3.

[0035] This utility model can provide bare chips after dicing as carriers for annealing processes, reducing the risk of material damage during manual loading and unloading, improving process efficiency, and enhancing the heating uniformity of each bare chip during annealing. It also retains some of the original wafer slots 3, allowing for the simultaneous annealing of a certain number of wafers.

[0036] This invention can provide an annealing carrier for diced chips, making the heating of each bare chip more uniform during the entire annealing process, reducing the risk of scratches caused by loading and unloading, and optimizing the efficiency of the process.

[0037] In a preferred embodiment, the vehicle body 1 includes an upper platform for setting recessed compartments and baffles 11 located on both sides of the upper platform, at least a portion of the baffles 11 being at a horizontal height higher than the upper platform.

[0038] Specifically, a recessed grid is set on the upper platform to hold the bare chip, and the baffles 11 on both sides are higher than the upper platform to prevent the bare chip from accidentally slipping or shifting during operation, movement or annealing. This provides physical protection for the bare chip and ensures that the chip is always in the predetermined annealing position, reducing uneven heating or process failure caused by positional deviation.

[0039] In a preferred embodiment, the wafer slot 3 includes a through slot 31 extending through the upper surface and a first groove 32 embedded in the stop bar 11.

[0040] Specifically, it consists of a through slot 31 that runs through the upper platform and a first groove 32 embedded in the baffle 11. The through slot 31 facilitates the smooth placement of the wafer into the upper platform from above, while the part embedded in the baffle 11 can enhance the stability of the wafer placement, provide support and limit the edge of the wafer, prevent the wafer from tilting or lifting during the annealing process, ensure the relative position of the wafer plane and the heating source is stable, and facilitate uniform heating and annealing.

[0041] In a preferred embodiment, the front and rear sides of the vehicle body 1 are respectively provided with support frames 12, and at least a portion of the support frame 12 is at a horizontal height higher than the horizontal height of the upper platform.

[0042] Specifically, the carrier body 1 is provided with support frames 12 on the front and rear sides, which are higher than the upper platform. On the one hand, this makes it convenient for operators to pick up and move the carrier, provides a point of leverage, and reduces the difficulty of operation. On the other hand, in the environment inside the annealing furnace, it can protect the upper platform and the chip from collisions and friction interference from other components inside the furnace, maintain the stability of the chip annealing environment, and improve process safety.

[0043] In a preferred embodiment, each bare chip recess 2 is provided with a single row of recessed grids, the recessed grids are distributed along the width direction of the carrier body 1, and the setting direction of the wafer slot 3 is consistent with the distribution direction of the recessed grids.

[0044] In a preferred embodiment, the bare die recess 2 and the wafer slot 3 are distributed sequentially at intervals, with a bare die recess 2 spaced apart between adjacent wafer slots 3, and a wafer slot 3 spaced apart between adjacent bare die recesses 2.

[0045] Specifically, the arrangement of the bare chip groove 2 and the wafer slot 3 in this invention, which are distributed alternately, can optimize the use of carrier space, avoid the chip placement being too crowded and affecting the annealing effect, and also make it easier for operators to distinguish and operate different types of chip placement. This ensures that the wafer and bare chip annealing processes do not interfere with each other on the same carrier and can be carried out in an orderly and efficient manner. At the same time, it is conducive to the uniform distribution and conduction of heat on the carrier, ensuring the stability of the overall annealing process.

[0046] In a preferred embodiment, a connecting rod 13 is also included, which connects the support frame 12 on the front side of the vehicle body 1 and the support frame 12 on the rear side.

[0047] Specifically, the connecting rod 13 connecting the front and rear support frames 12 enhances the overall structural strength and stability of the carrier, reduces the risk of deformation caused by frequent handling and thermal expansion and contraction in high-temperature environments, ensures that the chip is always in the precisely designed placement position and angle, and maintains long-term stable annealing process precision.

[0048] In a preferred embodiment, the wafer slot 3 further includes a second groove 33 into which the connecting rod 13 is embedded.

[0049] Specifically, the wafer slot 3 includes a second slot 33 with embedded connecting rod 13, which further optimizes the wafer support structure, stabilizes the wafer from multiple directions (upper table, stop bar 11, connecting rod 13), distributes the wafer weight, avoids excessive local stress causing wafer damage or instability, enhances the reliability of the carrier for wafer bearing, and adapts to long-term and multiple annealing operations.

[0050] In a preferred embodiment, the projection of the second groove 33 toward the upper platform is located within the area of ​​the through groove 31.

[0051] The above description is only a preferred embodiment of the present utility model and does not limit the implementation method and protection scope of the present utility model. Those skilled in the art should realize that all solutions obtained by equivalent substitutions and obvious changes made based on the description and illustrations of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A carrier for chip annealing, characterized in that, include, The carrier body (1) is provided with a raw chip groove (2) in the shape of a material box, and the raw chip groove (2) includes a plurality of recessed grids for placing chips; The wafer slot (3) is provided in an open shape on the carrier body (1).

2. The carrier for chip annealing according to claim 1, characterized in that, The bare chip recess (2) and the wafer slot (3) are evenly distributed along the length direction of the carrier body (1), and there is at least one bare chip recess (2) between adjacent wafer slots (3).

3. The carrier for chip annealing according to claim 1, characterized in that, The vehicle body (1) includes an upper platform for setting the recessed grid and baffles (11) located on both sides of the upper platform, at least a portion of the baffles (11) being at a horizontal height higher than the horizontal height of the upper platform.

4. The chip annealing carrier according to claim 3, characterized in that, The wafer slot (3) includes a through slot (31) that extends through the upper platform and a first slot (32) that is embedded in the stop bar (11).

5. The chip annealing carrier according to claim 4, characterized in that, The front and rear sides of the vehicle body (1) are respectively provided with support frames (12), and at least a portion of the support frame (12) is higher than the horizontal height of the upper platform.

6. The carrier for chip annealing according to claim 1, characterized in that, Each of the bare chip recesses (2) is provided with a single row of recessed grids, which are distributed along the width direction of the carrier body (1), and the wafer slot (3) is arranged in the same direction as the distribution direction of the recessed grids.

7. The chip annealing carrier according to claim 6, characterized in that, The bare chip recess (2) and the wafer slot (3) are distributed sequentially at intervals, with a bare chip recess (2) between adjacent wafer slots (3) and a wafer slot (3) between adjacent bare chip recesses (2).

8. The carrier for chip annealing according to claim 5, characterized in that, It also includes a connecting rod (13) that connects the support frame (12) on the front side and the support frame (12) on the rear side of the vehicle body (1).

9. The carrier for chip annealing according to claim 8, characterized in that, The wafer slot (3) also includes a second slot (33) into which the connecting rod (13) is embedded.

10. The carrier for chip annealing according to claim 9, characterized in that, The projection of the second groove (33) toward the upper platform is located within the area of ​​the through groove (31).

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