Wafer memory

Abstract

The utility model relates to the field of semiconductor manufacturing, and provides a wafer memory for solving the problems of low space utilization rate and low carrying efficiency of a conventional wafer memory. The wafer storage device comprises a storage bin wall, a plurality of carrying tables and a carrying device. A storage bin is arranged in the storage bin wall. The plurality of carrying tables are arranged in the storage bin and are configured to carry wafer boxes. The carrying device is arranged in the storage bin so as to move the wafer box among the carrying tables. The conveyance device has a main axis extending in a height direction. The carrying tables are divided into N carrying table groups, each carrying table group comprises M carrying tables, N is larger than or equal to 2, and M is larger than or equal to 2. The N carrying table groups are stacked at intervals in the height direction, and the M carrying tables of each carrying table group are arranged at intervals in the direction around the main axis, so that the distances from the carrying tables to the main axis are basically equal. Moving lines of the carrying device are reduced, control over the carrying device is simpler, and the carrying efficiency is improved while the space utilization rate of the wafer storage device is increased.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more specifically, to a chip memory. Background Technology

[0002] In the semiconductor industry, wafer memory, as an automated storage device, enables the transfer of wafers between different processes through collaboration with automated material handling systems. The storage compartment of a wafer memory contains multiple stages and transport devices. The stages hold wafer cassettes, while the transport devices move the cassettes between these stages. In previous wafer memory designs, the arrangement of these stages was inefficient, resulting in low space utilization and low handling efficiency. Utility Model Content

[0003] In view of this, the present disclosure provides a chip memory to improve the problems of low space utilization and low handling efficiency of conventional chip memories.

[0004] The chip memory includes a storage compartment wall, multiple stages, and a transport device. A storage compartment is located within the storage compartment wall. Multiple stages are disposed within the storage compartment and configured to hold chip cassettes. The transport device is located within the storage compartment to move the chip cassettes between the multiple stages. The transport device has a main axis extending along the height direction. The multiple stages are divided into N stage groups, each stage group comprising M stages, where N≥2 and M≥2. The N stage groups are stacked at intervals along the height direction, and the M stages of each stage group are spaced apart along the direction surrounding the main axis, such that the distances from the multiple stages to the main axis are substantially equal.

[0005] As one possible implementation, the chip memory also includes N carrier plates, which are stacked at intervals in the height direction, and N stage groups are respectively disposed on the N carrier plates.

[0006] As one possible implementation, each bearing plate has a side edge on the side facing the main axis, and the side edge is recessed in a direction away from the main axis.

[0007] As one possible implementation, the side edge includes M straight edge portions, which are directly opposite the main axis and have equal shortest distances to the main axis.

[0008] As one possible implementation, each bearing plate has a side edge on the side facing the main axis, and the N side edges of the N bearing plates 5 coincide in the orthographic projection on the projection plane perpendicular to the main axis.

[0009] As one possible implementation, the wafer cassette includes a joint that can be releasably coupled to a transport device, each carrier plate having a side edge on the side facing the main axis, and each stage being partially located outside the side edge, such that the joint of the wafer cassette placed on the stage is located outside the side edge.

[0010] In one possible implementation, the storage compartment wall includes a front sidewall with an interaction window. A wafer cassette is fed into or out of the storage compartment via the interaction window. Multiple stages are supported on the front sidewall and positioned above the interaction window.

[0011] As one possible implementation, the front sidewall also includes an observation window located above the interaction window. The storage compartment wall also includes a door panel that closes the observation window but can be opened by operation. The orthographic projections of multiple platforms on the front sidewall fall into the observation window.

[0012] As one possible implementation, each stage is equipped with a positioning unit. The positioning unit, in conjunction with the wafer cassette, restricts the orientation of the wafer cassette on the stage, ensuring that the wafer cassette is aligned with the main axis.

[0013] As one possible implementation, the M platforms in each platform group are located on the same height plane.

[0014] As one possible implementation, the orthographic projections of the Pth stage in the N stage groups coincide on the projection plane perpendicular to the principal axis, where 1≤P≤M.

[0015] This disclosure effectively utilizes the space around the transport device by arranging multiple platforms at intervals around the transport device, making the distances from the multiple platforms to the transport device substantially equal. This reduces the spacing between the platforms and the transport device, shortens the movement path of the transport device, simplifies the control of the transport device, and improves the space utilization of the wafer memory while increasing transport efficiency. Attached Figure Description

[0016] It should be understood that the following figures only illustrate certain embodiments of this disclosure and should not be construed as limiting the scope.

[0017] It should be understood that the same or similar reference numerals are used in the accompanying drawings to denote the same or similar elements.

[0018] It should be understood that the accompanying drawings are only schematic, and the dimensions and scales of the elements in the drawings are not necessarily precise.

[0019] Figure 1 This is a schematic diagram of the structure of a chip memory according to an embodiment of the present disclosure.

[0020] Figure 2 for Figure 1 A schematic diagram of a portion of the chip memory.

[0021] Figure 3 To show the view from above Figure 1 A schematic diagram of the internal structure of the chip memory.

[0022] Figure 4 for Figure 1 A schematic diagram of the structure of a transport device carrying a wafer cassette for a wafer memory.

[0023] Figure 5 To show Figure 1 A schematic diagram of the carrier board for the chip memory.

[0024] Figure 6 for Figure 1 A schematic diagram of the structure of the carrier plate, stage, sidewalls and conveying device of the chip memory.

[0025] Figure 7 To show the view from above Figure 1 A schematic diagram of the structure of multiple platforms and transport devices for the chip memory.

[0026] Figure 8 for Figure 1 A schematic diagram of the structure of a transport device carrying a wafer cassette for a wafer memory.

[0027] Figure 9 for Figure 1 A schematic diagram of the structure of the stage that carries the wafer cassette in the wafer memory.

[0028] Figure 10 To show Figure 1 A schematic diagram of the structure inside the front sidewall of the chip memory.

[0029] Figure 11 To show Figure 10 A schematic diagram of the structure on the outer side of the front sidewall, with the observation window closed.

[0030] Figure 12 To show Figure 10 A schematic diagram of the structure on the outer side of the front sidewall, with the observation window open.

[0031] Figures 1 to 12 Explanation of reference numerals in the attached figures:

[0032] 1-Storage compartment wall, 11-Side wall, 111-Front side wall, 12-Interaction window, 13-Observation window, 14-Door panel, 2-Platform, 21-Platform circumference circle, 22-First platform, 23-Second platform, 24-Protrusion, 25-First protrusion, 26-Second protrusion, 3-Wafer box, 31-First joint, 32-Front end face, 4-Transfer device, 41-Main axis, 42-Transfer device working range, 43-Main body, 44-Robotic arm, 45-Actuator, 46-Second joint, d-Distance from platform to main axis, 5-Bearing plate, 51-Right-angle aluminum profile, 52-First side edge, 53-Strip aluminum profile, 54-Second side edge, 55-Third side edge, 551-Straight edge, 6-Moving device. Detailed Implementation

[0033] Numerous specific details are set forth below to provide an understanding of the structure, function, and purpose of the embodiments illustrated in the specification and figures. It is to be understood that this document and the illustrated embodiments are non-limiting examples, and thus it can be appreciated that the particular structural and functional details disclosed herein are representative and exemplary. Variations and changes may be made to these embodiments without departing from the scope of the claims.

[0034] In the semiconductor industry, wafer memory, as an automated storage device, enables the transfer of wafers between different processes through collaboration with automated material handling systems. The wafer memory's storage compartment contains multiple stages and transport devices. The stages hold wafer cassettes, while the transport devices move the wafer cassettes between these stages.

[0035] However, the inventors discovered that the arrangement of multiple platforms in previous chip memories was not ideal, as the platforms typically had large spans, resulting in significant distances between them. Consequently, the working range of the handling device had to be increased, leading to low space utilization and low handling efficiency. A traditional solution was to enable the entire handling device to move laterally, with the range of movement defining the working range. However, handling devices are usually large, requiring considerable space during movement and increasing the overall size of the chip memory. Another approach was to keep the main body of the handling device stationary and increase the working range by extending the length of the robotic arm. However, this method increased the structural complexity of the robotic arm and placed higher demands on its strength. Furthermore, both methods required the main body or the robotic arm to travel considerable distances when grasping distant chip cassettes, resulting in very low handling efficiency.

[0036] To address the aforementioned issues of low space utilization and low handling efficiency of wafer memory, this disclosure proposes a solution. By arranging multiple stages at intervals around a handling device, the distances from the stages to the handling device are made substantially equal. This effectively utilizes the space around the handling device, reduces the distance between the stages and the handling device, simplifies the movement path of the handling device, simplifies control of the handling device, and improves both the space utilization and handling efficiency of the wafer memory.

[0037] The chip memory provided in this disclosure will be described in more detail below.

[0038] like Figures 1-4 As shown, the wafer memory disclosed herein includes a storage compartment wall 1, multiple stages 2, and a transport device 4. A storage compartment is provided within the storage compartment wall 1. The multiple stages 2 are disposed within the storage compartment and configured to carry wafer cassettes 3. The transport device 4 is disposed within the storage compartment to move the wafer cassettes 3 between the multiple stages 2. The transport device 4 has a main axis 41 extending along the height direction. The multiple stages 2 are divided into N stage groups, each stage group including M stages 2, where N≥2 and M≥2. The N stage groups are stacked at intervals in the height direction. The M stages 2 of each stage group are arranged at intervals along the direction surrounding the main axis 41, such that the distances from the multiple stages 2 to the main axis 41 are substantially equal. The main axis 41 can be the center of the working range 42 of the transport device or the body center of the transport device 4 projected onto a horizontal plane. The distance d from stage 2 to main axis 41 can be: the vertical distance from the center of the circumcircle 21 of stage 2 projected onto the horizontal plane to main axis 41; or it can be the vertical distance from the center of the wafer on stage 2 to main axis 41.

[0039] In this disclosure, the storage compartment wall 1 includes multiple side walls 11, and the number of side walls 11 is not limited. Multiple side walls 11 can be joined together to form a storage compartment within them. The joining side walls 11 may or may not be joined together. The storage compartment serves as a receiving space for accommodating multiple support platforms 2 and conveying devices 4. Figure 4As shown, the handling device 4 may include a main body 43, a robotic arm 44, and an actuator 45. The main body 43 can support and drive the robotic arm 44. The robotic arm 44 can move under the support and drive of the main body 43. The actuator 45 is mounted on the robotic arm 44 and, supported by the robotic arm 44, reaches a designated position to grasp and place the wafer cassette 3. The handling device 4 as a whole or some of its components can be driven to rise and fall to handle the wafer cassette 3 between platforms 2 at different heights. Multiple platforms 2 within the storage compartment are divided into N platform groups, and the N platform groups are stacked at intervals in the height direction. This disclosure does not limit the interval height between adjacent platform groups in the N platform groups; the interval height can be uniform or non-uniform. Each platform group includes M platforms 2. This disclosure does not limit the height difference between the M platforms 2; the M platforms 2 can be at the same height or at different heights. The M platforms 2 of each platform group are arranged at intervals along the direction surrounding the main axis 41. This disclosure does not limit the spacing between adjacent platforms 2 in the M platforms 2, and the spacing can be uniform or non-uniform.

[0040] Specifically, such as Figures 1-4 As shown, in the above embodiment, the sidewall 11 of the wafer memory forms a hollow rectangle, and the space inside the rectangle serves as a storage compartment. The transport device 4 within the storage compartment includes a main body 43, a robotic arm 44 above the main body 43, and the robotic arm 44 is connected to the main body 43 via a connecting shaft. The actuator 45 at the end of the robotic arm 44 is a gripper. The transport device 4 can move up and down with the moving device 6. When the transport device 4 reaches a designated height, the main body 43 drives the robotic arm 44 to move, allowing the gripper at the end of the robotic arm 44 to reach any position in the workspace horizontally. After the gripper reaches the designated position, it can grasp or place the wafer cassette 3. With the cooperation of the moving device 6, the transport device 4 can transport the wafer cassette 3 between platforms 2 at different heights and positions. At this time, the main axis 41 of the transport device 4 is the axis of the connecting shaft between the main body 43 and the robotic arm 44. Nine platforms 2 are arranged horizontally and vertically on the sidewall 11. Three horizontally arranged platforms 2 form a platform group, for a total of three platform groups. The spacing between adjacent platform groups in the three platform groups is consistent. The three platforms 2 in each platform group are at the same height, arranged at intervals around the main axis 41, and the spacing between adjacent platforms 2 is equal. Simultaneously, the distances d from the nine platforms 2 to the main axis 41 are approximately equal.

[0041] In the above embodiments, the platforms 2 are arranged at intervals around the main axis 41 of the transport device 4, which makes effective use of the space around the transport device 4, resulting in a more compact internal structure of the wafer memory and a smaller wafer memory size. The multiple platforms 2 are approximately equidistant from the main axis 41, reducing the distance between platforms 2 that are far from the transport device 4 in traditional wafer memory and the transport device 4. This reduces the operating range of the transport device 4, eliminating the need to move the transport device 4 or use a long robotic arm 44, thus reducing the space occupied by the transport device 4. When the distances of the platforms 2 to the main axis 41 are consistent, it is easier to control the transport device 4 to reach platforms 2 at the same distance. Furthermore, the movement path of the transport device 4 is reduced during each transport process, improving transport efficiency.

[0042] In some embodiments, such as Figure 2 As shown, the wafer memory also includes N carrier plates 5, which are stacked at intervals in the height direction, and N stage groups are respectively disposed on the N carrier plates 5. The carrier plate 5 can be a planar plate with sufficient space to accommodate the stages 2 arranged in a specific manner on the carrier plate 5. This arrangement ensures that the distance d from the stages 2 on the carrier plate 5 to the main axis 41 is substantially equal. The N carrier plates 5 can be fixed to a frame and connected to each other through the frame. The carrier plates 5 can also be fixed to the side wall 11 and connected to each other through the side wall 11. This disclosure does not limit the fixing method of the carrier plates 5; it can be welding or bolting. When the stage 2 is disposed on the carrier plate 5, the carrier plate 5 bears the weight of the wafer cassette 3 on it. Since the area of ​​the carrier plate 5 is larger than that of the stage 2, fixing the carrier plate 5 to the frame or side wall 11 provides a larger fixing area, which can improve the connection strength of the structure. This disclosure does not limit the fixing method between the stage 2 and the carrier plate 5; it can be a snap-fit ​​of protrusions and grooves, or welding or bolting.

[0043] Specifically, such as Figure 2 , Figure 3 , Figure 5As shown, in some embodiments, the chip memory has three carrier plates 5. Each carrier plate 5 is fixedly connected to a sidewall 11. Two right-angled aluminum profiles 51 are disposed below the carrier plate 5, respectively near the first side edges 52 on both sides of the carrier plate 5. Each right-angled aluminum profile 51 includes two right-angled sides. One right-angled side is fixed to the bottom of the carrier plate 5, and the other right-angled side is fixed to the sidewall 11. The two right-angled aluminum profiles 51 are connected by a strip aluminum profile 53. The connection between the aluminum profiles, the carrier plate 5, and the sidewall 11 is by welding. The three carrier plates 5 are stacked at intervals in the height direction, and the interval between adjacent carrier plates 5 is equal. All three carrier plates 5 are arranged horizontally. Each carrier plate 5 is provided with three platforms 2, the middle platform 2 is the first platform 22, and the two platform 2 at the edges are the second platforms 23. The two second platforms 23 are symmetrically arranged relative to the first platform 22. The carrier plate 5 includes a second side edge 54 near the sidewall 11. The distance from the second platform 23 to the second side edge 54 is greater than the distance from the first platform 22 to the second side edge 54. This ensures that the distances d from the first platform 22 and the second platform 23 to the main axis 41 are equal. The platform 2 and the bearing plate 5 are connected by bolts.

[0044] In the above embodiment, the stage 2 is arranged on the support plate 5, which has sufficient space to allow the stage 2 to be arranged in a specific pattern, such that the distances from the stage 2 on the support plate 5 to the main axis 41 of the transport device 4 are substantially equal. Furthermore, the support plate 5 bears the weight of the wafer cassette 3 on it. Because the support plate 5 has a larger fixed area than the stage 2, the connection strength is greater and the structure is more stable.

[0045] In some embodiments, such as Figure 3 As shown, each carrier plate 5 has a side edge on the side facing the main axis 41, wherein the side edge can be a third side edge 55. The third side edge 55 is recessed in a direction away from the main axis 41. This disclosure does not limit the shape of the recess; it can be arc-shaped, rectangular, or irregular. Due to the recess on the third side edge 55, the third side edge 55 is close to the stage 2. When removing the wafer cassette 3 from the stage 2, the transport device 4 only needs to move the wafer cassette 3 a short distance toward the third side edge 55 to detach it from the carrier plate 5. The detachment of the wafer cassette 3 from the carrier plate 5 means that the orthographic projection of the wafer cassette 3 on the projection plane perpendicular to the main axis 41 does not coincide with the orthographic projection of the carrier plate 5 on the projection plane perpendicular to the main axis 41. At this time, the transport device 4 can move the wafer cassette 3 vertically in the height direction without interfering with the carrier plate 5. Specifically, as Figure 3As shown, the third side edge 55 is recessed away from the main axis 41, and at its deepest point, the third side edge 55 is in contact with the first stage 22. At this time, removing the wafer cassette 3 only requires moving it one stage 2 distance towards the third side edge 55, thus moving the wafer cassette 3 in the height direction. Conversely, placing the wafer cassette 3 also only requires moving it one stage 2 distance towards the second side edge 54. Therefore, in the above embodiment, shortening the distance between the third side edge 55 and the stage 2 reduces the distance the wafer cassette 3 needs to move when removing and placing it, further improving handling efficiency.

[0046] In some embodiments, such as Figure 3 As shown, the third side edge 55 includes M straight edge portions 551, which are directly opposite the main axis 41 and have equal shortest distances to it. Each straight edge portion 551 includes a perpendicular line passing through the main axis 41, and the distance from the foot p of this perpendicular line to the main axis 41 is the shortest distance from the straight edge portion 551 to the main axis 41. M stages 2 are correspondingly placed on the M straight edge portions 551. Since the shortest distances from the M straight edge portions 551 to the main axis 41 are equal, the distances from the M stages 2 to the main axis 41 are also equal. The straight edge portions 551 conform more closely to the contour of the wafer cassette 3 than the curved edge portions, and have a simpler structure and lower manufacturing cost.

[0047] In some embodiments, such as Figure 6 As shown, each carrier plate 5 has a third side edge 55 on the side facing the main axis 41. When the transport device 4 removes the wafer cassette 3 from the stage 2, it needs to move the wafer cassette 3 towards the third side edge 55 to detach the wafer cassette 3 from the carrier plate 5. The detachment of the wafer cassette 3 from the carrier plate 5 means that the orthographic projection of the wafer cassette 3 on the projection plane perpendicular to the main axis 41 does not coincide with the orthographic projection of the carrier plate 5 on the projection plane perpendicular to the main axis 41. Therefore, when the wafer cassette 3 detaches from the carrier plate 5, and as... Figure 7 As shown, when the orthographic projections of the N third side edges 55 of the N carrier plates 5 onto the projection plane perpendicular to the main axis 41 coincide, the wafer cassette 3 can vertically rise and fall among the N carrier plates 5 without interfering with them. Specifically, as... Figure 6 As shown, the chip memory is provided with three carrier plates 5. The third side edges 55 of the three carrier plates 5 coincide in the orthographic projection onto a projection plane perpendicular to the main axis 41. That is, in a top view, as... Figure 7As shown, the three third side edges 55 completely overlap. When the wafer cassette 3 detaches from any of the carrier plates 5, it can be vertically raised and lowered without colliding or interfering with other carrier plates 5 during descent. Therefore, in the above embodiment, the orthographic projections of the N third side edges 55 of the N carrier plates 5 onto the projection plane perpendicular to the main axis 41 overlap, allowing the wafer cassette 3 to be vertically raised and lowered after detaching from the carrier plate 5, without colliding or interfering with the carrier plate 5 during movement, and without needing to adjust the position of the wafer cassette 3 on the projection plane perpendicular to the main axis 41.

[0048] In some embodiments, such as Figure 3 , Figure 8 As shown, the wafer cassette 3 includes a coupling portion releasably coupled to the transport device 4, wherein the coupling portion may be a first coupling portion 31. The transport device 4 has a second coupling portion 46 that mates with the first coupling portion 31. The transport device 4 grips the wafer cassette 3 through the engagement of the first coupling portion 31 and the second coupling portion 46. Each carrier plate 5 has a third side edge 55 on the side facing the main axis 41, and each stage 2 is partially located outside the third side edge 55, such that the first coupling portion 31 of the wafer cassette 3 placed on the stage 2 is located outside the third side edge. Since the first coupling portion 31 is located outside the third side edge 55, the second coupling portion 46 does not need to extend onto the carrier plate 5 when the transport device 4 grips the wafer cassette 3. That is, when the transport device 4 grips the wafer cassette 3, the orthographic projection of the transport device 4 on the projection plane perpendicular to the main axis 41 does not coincide with the orthographic projection of the carrier plate 5 on the projection plane perpendicular to the main axis 41. Specifically, as Figure 3 , Figure 9 As shown, the portion of the stage 2 beyond the third side edge 55 is a protrusion 24, and the first connecting portion 31 of the wafer cassette 3 is located above the protrusion. The first connecting portion 31 is the vertical flange on both sides of the opening of the wafer cassette 3. Figure 8 As shown, the handling device 4 includes a robotic arm 44 and an actuator 45 located at the end of the robotic arm 44. The actuator 45 has a second engagement portion 46 that mates with the first engagement portion 31. The second engagement portion 46 consists of two vertical grooves. When the actuator 45 grips the wafer cassette 3, the flange located outside the third side edge 55 engages with the grooves on the actuator 45. Since the actuator 45 does not need to extend above the support platform 2, the actuator 45 can be lower than the support platform 2. Therefore, when the handling device 4 of the above embodiment grips the wafer cassette 3, even if the second engagement portion 46 is partially lower than the support plate 5, it will not collide with the support plate 5. This allows for greater flexibility in the height of the second engagement portion 46 when the handling device 4 grips the wafer cassette 3, without requiring the second engagement portion 46 to be higher than the support plate 5. Moreover, since the actuator 45 does not need to extend above the support plate 5, the risk of collision between the actuator 45 and the support plate 5 is reduced.

[0049] In some embodiments, such as Figure 10As shown, the storage compartment wall 1 includes a front sidewall 111, meaning that one of the multiple sidewalls 11 is the front sidewall 111. The front sidewall 111 is provided with an interaction window 12, through which the wafer cassette 3 is fed into or out of the storage compartment. Multiple platforms 2 are supported on the front sidewall 111 and located above the interaction window 12. The interaction window 12 is located below the platforms 2. By placing the interaction window 12 and the platforms 2 on the same sidewall 11, the movement path of the wafer cassette 3 is shortened, which can improve handling efficiency.

[0050] In some embodiments, such as Figure 11 and Figure 12 As shown, the front sidewall 111 also has an observation window 13 located above the interaction window 12. The observation window 13 is used to observe the internal condition of the wafer memory. The orthographic projection of the multiple stages 2 on the front sidewall 111 falls into the observation window 13, facilitating observation of the wafer cassette 3 on the stages 2. The memory compartment wall 1 also includes a door panel 14, which closes the observation window 13 but can be operated to open.

[0051] In some embodiments, each stage 2 is provided with a positioning part, which, by cooperating with the wafer cassette 3, restricts the orientation of the wafer cassette 3 on the stage 2, so that the wafer cassette 3 is aligned with the main axis 41. The positioning part can be a protrusion or a groove, which cooperates with a protrusion or groove on the wafer cassette 3. Specifically, as shown in... Figure 9 As shown, the positioning part consists of two protrusions on the surface of the carrier stage 2: a first protrusion 25 and a second protrusion 26. The first protrusion 25 and the second protrusion 26 are arranged parallel to each other, forming a groove between them. The bottom of the wafer cassette 3 is engaged in this groove. When the wafer cassette 3 is placed on the carrier stage 2, the perpendicular line between the centroid of the wafer inside and the main axis 41 is perpendicular to the front end face 32 of the wafer cassette 3, meaning the wafer cassette 3 is directly facing the main axis 41. If the orientation of the wafer cassette 3 is restricted to being directly facing the main axis 41, unnecessary adjustment and positioning time of the transport device 4 can be reduced when it grasps the wafer cassette 3. When transporting the wafer cassette 3 between two carrier stages 2 at different positions but with the same height, the transport device 4 only needs to be rotated on the horizontal plane. During transport, the wafer cassette 3 remains directly facing the main axis 41, eliminating the need to adjust the angle between the wafer cassette 3 and the transport device 4. Simultaneously, the risk of collision between the wafer cassette 3 and the transport device 4 due to incorrect orientation can also be reduced.

[0052] In some embodiments, the M stages 2 of each stage group are located on the same height plane; and / or, the orth projections of the Pth stage 2 of the N stage groups coincide on the projection plane perpendicular to the principal axis 41, 1≤P≤M. Figure 2As shown, the three platforms 2 in each platform group are located on the same height plane, and the orthographic projections of the three platforms 2 in the same column of the three platform groups coincide on the projection plane of the vertical main axis 41. When the transport device 4 transports the wafer cassette 3 between platforms 2 on the same layer, no lifting or lowering is required. When transporting the wafer cassette 3 between columns, no horizontal adjustment is required. This simplifies the control of the transport device 4.

[0053] The present disclosure is described in more detail below with specific examples. It should be noted that these examples are merely to assist those skilled in the art in understanding the present disclosure and are not intended to limit the disclosure to the specific numerical values ​​or scenarios illustrated. Those skilled in the art will obviously be able to make various equivalent modifications or variations based on the examples given below, and such modifications or variations also fall within the scope of this disclosure.

[0054] In some embodiments, such as Figures 1-12As shown, the sidewalls 11 of the wafer memory form a hollow rectangle, and the space inside the rectangle serves as a storage compartment. The transport device 4 within the storage compartment includes a main body 43 and a robotic arm 44 above the main body 43. The robotic arm 44 is connected to the main body 43 via a connecting shaft. The end of the robotic arm 44 is a gripper with grooves that releasably engage with the wafer cassette. The main axis 41 of the transport device 4 is the axis of the connecting shaft between the main body 43 and the robotic arm 44. With the assistance of the moving device 6, the transport device 4 can transport wafer cassettes 3 between platforms 2 at different heights. The sidewalls 11 include a front sidewall 111, on which three support plates 5 are mounted. Each support plate 5 is fixedly connected to the front sidewall 111 via a right-angle aluminum profile 51. Each support plate 5 has three platforms 2 mounted on it. The three platforms 2 arranged laterally form a platform group, for a total of three platform groups. The three stages 2 in each stage group are located at the same height plane, and the orthographic projections of the three stages 2 in the same column of the three stage groups coincide on the horizontal plane. Each carrier plate 5 has a third side edge 55 on the side facing the main axis 41, and the third side edge 55 is recessed in a direction away from the main axis 41. The orthographic projections of the three third side edges 55 of the three carrier plates 5 coincide on the horizontal plane. The third side edge 55 includes three straight edge portions 551, which are directly opposite the main axis 41 and have equal shortest distances to the main axis 41. The three wafer cassettes 3 are placed corresponding to the three straight edge portions 551, and the vertical distances from the centers of the circumcircle 21 of the nine stages 2 to the main axis 41 are all equal. It is easier for the control and handling device 4 to reach the stages 2 at the same distance. The stage 2 includes a protrusion 24 located outside the third side edge 55. The wafer cassette 3 includes vertical flanges on both sides of the cassette opening, which can be releasably engaged with the grooves on the grippers. The flange of the wafer cassette 3, mounted on the stage 2, is located outside the third side edge 55. This allows the grippers to not extend above the support plate 5 when grasping the wafer cassette. The surface of the stage 2 is provided with a first protrusion 25 and a second protrusion 26. The first protrusion 25 and the second protrusion 26 are arranged parallel to each other, forming a groove between them, in which the bottom of the wafer cassette 3 is engaged. This restricts the orientation of the wafer cassette 3 on the stage 2, ensuring that the wafer cassette 3 is directly facing the main axis 41. The wafer cassette 3 remains directly facing the main axis 41 during movement. The front sidewall 111 has an interaction window 12 through which the wafer cassette 3 is fed into or out of the storage compartment, with the stage 2 positioned above the interaction window 12. The front sidewall 111 also has an observation window 13 located above the interaction window 12. The door panel 14 can close the observation window 13 and can be opened by operation.

[0055] It should be noted that the elements described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0056] It should be understood that multiple components and / or parts can be provided by a single integrated component or part. Alternatively, a single integrated component or part can be divided into multiple separate components and / or parts. The use of the public designation "a" or "an" to describe a component or part does not imply the exclusion of other components or parts.

[0057] It should be understood that although terms such as “first” or “second” may be used in this disclosure to describe various elements (such as a first bump and a second bump), these elements are not defined by these terms, which are only used to distinguish one element from another.

[0058] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0059] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip memory, characterized in that, The chip memory includes: Storage compartment wall, wherein a storage compartment is provided within the storage compartment wall; Multiple platforms, disposed within the storage compartment and configured to carry wafer cassettes; and A transport device, disposed within the storage compartment, is used to move wafer cassettes between a plurality of platforms. The transport device has a main axis extending along the height direction. The plurality of platforms are divided into N platform groups, each platform group comprising M platforms, where N≥2 and M≥2. The N platform groups are stacked at intervals along the height direction. The M platforms of each platform group are spaced apart along the direction surrounding the main axis, such that the distances from the plurality of platforms to the main axis are substantially equal.

2. The chip memory according to claim 1, characterized in that, The wafer memory also includes N carrier plates, which are stacked at intervals in the height direction, and the N stage groups are respectively disposed on the N carrier plates.

3. The chip memory according to claim 2, characterized in that, Each support plate has a side edge on the side facing the main axis, and the side edge is recessed in a direction away from the main axis.

4. The chip memory according to claim 3, characterized in that, The side edge includes M straight edge portions, which are directly opposite the main axis and have the same shortest distance to the main axis.

5. The chip memory according to claim 2, characterized in that, Each support plate has a side edge on the side facing the main axis, and the N side edges of the N support plates coincide in the orthographic projection on the projection plane perpendicular to the main axis.

6. The chip memory according to claim 2, characterized in that, The wafer cassette includes a joint that can be releasably coupled to the transport device, each carrier plate having a side edge on one side facing the main axis, and each stage being partially located outside the side edge such that the joint of the wafer cassette placed on the stage is located outside the side edge.

7. The chip memory according to claim 1, characterized in that, The storage compartment wall includes a front sidewall, which is provided with an interaction window. The wafer cassette is fed into or out of the storage compartment through the interaction window. The plurality of platforms are supported on the front sidewall and located above the interaction window.

8. The chip memory according to claim 7, characterized in that, The front sidewall is also provided with an observation window located above the interactive window. The storage compartment wall also includes a door panel, which closes the observation window and can be operated to open. The orthographic projection of the plurality of platforms on the front sidewall falls into the observation window.

9. The chip memory according to any one of claims 1 to 8, characterized in that, Each stage is provided with a positioning part, which cooperates with the wafer cassette to restrict the orientation of the wafer cassette on the stage, so that the wafer cassette is facing the main axis.

10. The chip memory according to any one of claims 1 to 8, characterized in that, The M platforms of each platform group are located on the same height plane; and / or, the orth projections of the Pth platform of the N platform groups coincide on the projection plane perpendicular to the main axis, 1≤P≤M.

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