Semiconductor package
By removing the bonding pads and cover layers between photonic integrated circuits and electronic integrated circuits in semiconductor packaging, and filling the optical path with light-transmitting materials, the problem of optical signal transmission loss is solved, and more efficient optical performance is achieved.
Patent Information
- Application Number
- CN202422435036.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-10
- Filing Date
- 2024-10-09
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2034-10-09
AI Technical Summary
The existing interconnection process between photonic chips and electronic chips in semiconductor packaging is not robust, leading to optical signal transmission loss.
By removing the bonding pads and cover layers between photonic integrated circuits and electronic integrated circuits in semiconductor packaging, filling the optical path with light-transmitting materials, and setting protective films and light-transmitting material layers in the optical and peripheral areas, lossless transmission of optical signals is ensured.
It effectively reduces optical signal transmission loss and improves the optical performance of semiconductor packaging.
Smart Images
Figure CN223526528U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor package. BACKGROUND
[0002] Currently, semiconductor packages including a photonic die (referred to as a P-die) and an electronic die (referred to as an E-die) are becoming increasingly popular due to their compactness. In addition, optical signals and processing have gained more applications as fiber optic related applications have been widely used for signal transmission. While existing methods of manufacturing semiconductor packages are generally adequate for their intended purpose, they have not been entirely satisfactory in all respects. For example, developing robust processes for interconnections between the P-die, the E-die, and the optical fiber still faces challenges. SUMMARY
[0003] The present application provides a semiconductor package including an electronic integrated circuit die and a photonic integrated circuit die. The electronic integrated circuit die includes a semiconductor structure, an interconnect layer, a passivation layer, a protective film, a gap fill material, and a plurality of first bonding pads. The semiconductor structure includes a recess. The interconnect layer is disposed on the semiconductor structure, wherein the interconnect layer has an opening portion exposing the recess of the semiconductor structure. The passivation layer is disposed on the interconnect layer. The protective film is disposed on the passivation layer and above the interconnect layer, and on sidewalls of the opening portion, wherein the protective film is further disposed on the recess of the semiconductor structure. The gap fill material is disposed in the opening portion of the interconnect layer and is surrounded by the interconnect layer. The plurality of first bonding pads is disposed on the protective film. The photonic integrated circuit die is bonded to the electronic integrated circuit die and includes a photonic layer and a plurality of second bonding pads. The photonic layer overlaps the opening portion of the interconnect layer. The plurality of second bonding pads is disposed above the photonic layer, wherein the plurality of second bonding pads is bonded to the plurality of first bonding pads.
[0004] The present application provides a semiconductor package including a photonic integrated circuit die and an electronic integrated circuit die. The photonic integrated circuit die includes a photonic layer. The electronic integrated circuit die is bonded to the photonic integrated circuit die and includes an optical region overlapping the photonic layer and a peripheral region outside the optical region. The optical region includes a plurality of optical relief structures, a protective film, and a light transmissive material layer. The plurality of optical relief structures is formed by a semiconductor structure. The protective film is disposed above the plurality of optical relief structures, wherein the protective film extends to the peripheral region. The light transmissive material layer is disposed above the protective film and fills the optical region. The peripheral region includes a plurality of first bonding pads and a plurality of via structures. The plurality of first bonding pads is bonded to the photonic integrated circuit die. The plurality of via structures is connected to the plurality of first bonding pads, wherein the protective film laterally surrounds sidewalls of the plurality of via structures. BRIEF DESCRIPTION OF DRAWINGS
[0005] The various aspects of the present disclosure will be best understood with reference to the following detailed description read in light of the accompanying drawings. It should be noted that various features are not drawn to scale. In fact, the critical dimensions of the various features can be arbitrarily increased or decreased for the sake of clarity. The various features can be arbitrarily increased or decreased for the sake of clarity.
[0006] Figures 1 to 8 are schematic top and cross-sectional views of various stages in a method of fabricating a semiconductor package according to some example embodiments of the present disclosure.
[0007] Figures 9 to 13 are schematic top and cross-sectional views of various stages in a method of fabricating a semiconductor package according to some other embodiments of the present disclosure.
[0008] Figure 14 is a schematic cross-sectional view of a semiconductor package according to some other embodiments of the present disclosure.
[0009] Figure 15 is a schematic cross-sectional view of a semiconductor package according to some other embodiments of the present disclosure.
[0010] Figure 16 is a schematic cross-sectional view of a semiconductor package according to some other embodiments of the present disclosure.
[0011] BRIEF DESCRIPTION OF DRAWINGS
[0012] 102: semiconductor wafer / semiconductor structure
[0013] 102-CV: cavity
[0014] 104: interconnect layer
[0015] 104A: metallization pattern
[0016] 104B: dielectric layer
[0017] 106: passivation layer
[0018] 108: protective film
[0019] 110: gap fill material
[0020] 110-TS: top surface
[0021] 111: second gap fill material
[0022] 112: first dielectric layer
[0023] 114: cap layer
[0024] 114-OP: open portion
[0025] 116: first bonding film
[0026] 118: conductive pattern
[0027] 118A: first bonding pad
[0028] 118B: via structure
[0029] 118C: barrier layer
[0030] 200: photonic integrated circuit die
[0031] 202: semiconductor wafer
[0032] 204: photonic layer
[0033] 204A: grating coupler
[0034] 206: interconnect layer
[0035] 208: second bonding film
[0036] 210: second bonding pad
[0037] 302: optical fiber structure
[0038] 400: optical assembly
[0039] LX1: optical relief structure
[0040] OR1: opening
[0041] PH1: optical path
[0042] PKX1, PKX2, PKX3, PKX4, PKX5: semiconductor package
[0043] RG1: optical region
[0044] RG2: peripheral region
[0045] W1, W2: width DETAILED DESCRIPTION
[0046] The following disclosure provides many different embodiments, or examples, for implementing various characteristics of the provided subject matter. Specific examples of components and arrangements are set forth herein to provide a thorough description of the embodiments. It will be apparent, however, that these are only examples and are not intended to be limiting. For example, in the following description, a first feature over or on a second feature can include embodiments in which the second feature is directly on top of the first feature, and can also include embodiments in which additional features are between the first and second features, such that the second feature is not directly on top of the first feature. In addition, the disclosure can use repetition of the phrase "comprising" or "including" to describe various embodiments and / or configurations. This is done for clarity and is not meant to be limiting.
[0047] In addition, spatially relative terms, such as "beneath", "below", "lower", "on", "over", "overlying", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0048] Other features and processes can also be included. For example, test structures can be included to allow for verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. The test structures can include, for example, test pads formed in a redistribution layer or on a substrate that enable testing of the 3D package or 3DIC, enable use of probes and / or probe cards, and the like. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with testing methods that include intermediate verification of known good dies to improve yield and reduce costs.
[0049] In the fabrication of electronic integrated circuits (EICs) and photonic integrated circuits (PICs), bond pads for hybrid bonding between EIC and PIC wafers are typically formed by damascene, dual damascene, or other processes utilizing a capping layer. However, in optical paths between EIC and PIC wafers (or EIC and PIC dies) for optical signal transmission, the presence of these capping layers would result in loss of optical signals. According to some embodiments of the present disclosure, the problem of optical signal loss is addressed by removing the bond pads and capping layers present along the optical path between the EIC and PIC wafers.
[0050] Figures 1 to 8 are schematic top and cross-sectional views of various stages in a method of fabricating a semiconductor package according to some example embodiments of the present disclosure. Reference is made to Figures 1 to 6 , which depict steps of forming an electronic integrated circuit die 100. As shown in Figure 1 , a semiconductor wafer 102 (semiconductor structure) is provided. In some embodiments, the semiconductor wafer 102 is made of a light-transmissive material that allows optical signals to pass through. For example, in one embodiment, the semiconductor wafer 102 is a silicon wafer, which can be monolithically processed or diced to form the semiconductor structure or substrate of the electronic integrated circuit die 100 in subsequent stages.
[0051] In some embodiments, is to form an interconnect layer 104 on the semiconductor wafer 102. For example, forming the interconnect layer 104 includes forming a plurality of metallization patterns 104A embedded in a dielectric layer 104B. The metallization patterns 104A can include conductive vias, conductive lines, or a combination thereof. In some embodiments, the metallization patterns 104A are made of conductive materials such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), nickel (Ni), tantalum (Ta), alloys thereof, and the like, and can be formed by electroplating, deposition, and / or photolithography and etching.
[0052] In some embodiments, the dielectric layer 104B comprises a material of polyimide, epoxy, acrylic, phenol formaldehyde, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. In addition, the dielectric layer 104B can also be formed of an oxide or a nitride, such as silicon oxide, silicon nitride, etc. The dielectric layer 104B can be formed by a suitable process, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, the dielectric layer 104B is formed to laterally surround and cover the plurality of metallization patterns 104A. After the formation of the interconnect layer 104, a passivation layer 106 can be formed over the interconnect layer 104. For example, the passivation layer 106 can be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials. The passivation layer 106 can be formed by any suitable process, such as high-density plasma chemical vapor deposition (HDP-CVD), PECVD, etc.
[0053] Referring to Figure 2 In a subsequent step, the interconnect layer 104 and the passivation layer 106 are patterned to form an opening OR1. For example, portions of the interconnect layer 104 and portions of the passivation layer 106 are removed to form the opening OR1 that exposes the semiconductor wafer 102. In some embodiments, portions of the semiconductor wafer 102 are further removed to form a recess 102-CV in the semiconductor wafer 102. The shape of the opening OR1 is not particularly limited and can be adjusted as appropriate based on design requirements.
[0054] Referring to Figure 3 After the formation of the opening OR1, the semiconductor wafer 102 can be further patterned to form an optical relief structure LX1. Although Figure 3 Only one optical relief structure LX1 is shown in FIG. 1, it is noted that there can be multiple optical relief structures LX1 formed by the semiconductor wafer 102 in practice. In some embodiments, the optical relief structure LX1 in the semiconductor wafer 102 is formed by further removing portions of the semiconductor wafer 102 from the recess 102-CV.
[0055] After the optical relief structures LX1 are formed, a protective film 108 can be formed over the interconnect layer 104 on the passivation layer 106. In some embodiments, the protective film 108 is also formed on the sidewalls of the opening portion OR1 and conformally formed on the recessed portion 102-CV of the semiconductor chip 102. In certain embodiments, the material of the protective film 108 can be a silicon-containing material, an oxide material, a nitride material, or a combination thereof, etc. In other embodiments, the material of the protective film 108 is not particularly limited and can be an inorganic material, an organic material, a metallic material, a polymeric material, or a combination thereof, etc. In addition, the protective film 108 can be a single layer film made of the above-mentioned materials, or can include a plurality of stacked film layers made of the above-mentioned materials.
[0056] In some embodiments, after the protective film 108 is formed, an optical region RG1 and a peripheral region RG2 can be defined. In an exemplary embodiment, the optical region RG1 is a region in the electronic integrated circuit die 100 that allows the optical signal to pass through the optical region RG1 to other optical components. For example, as shown, the optical region RG1 includes the plurality of optical relief structures LX1 formed by the semiconductor wafer 102, and includes the protective film 108 formed on the optical relief structures LX1. In an exemplary embodiment, the optical region RG1 has a width W1, where the width W1 is defined by the distance between two opposite sidewalls of the protective film 108 in the opening portion OR1. Figure 3
[0057] As further shown, the optical region RG1 is free of the metallization pattern 104A and the dielectric layer 104B of the interconnect layer 104. In other words, the metallization pattern 104A and the dielectric layer 104B of the interconnect layer 104 are formed in the peripheral region RG2. In some embodiments, the protective film 108 also extends from the optical region RG1 to the peripheral region RG2. In some embodiments, the recessed portion 102-CV of the semiconductor wafer 102 is located in the optical region RG1, while other portions of the semiconductor wafer 102 are located in the peripheral region RG2. In addition, the top surface of the semiconductor wafer 102 in the peripheral region RG2 is located at a higher level than the top surface of the semiconductor wafer 102 in the optical region RG1 (e.g., the recessed portion 102-CV with the optical relief structures LX1). Figure 3 Referring to
[0058] Figure 4 In subsequent steps, gap filler 110 is formed in the opening OR1 of the interconnect layer 104 and in the optical region RG1. For example, gap filler 110 is formed on the protective film 108 and is laterally surrounded by the interconnect layer 104. In some embodiments, excess gap filler 110 formed above the interconnect layer 104 can be removed by a planarization process, for example, by mechanical polishing and / or chemical mechanical polishing (CMP). After the planarization process, the top surface 110-TS of the gap filler 110 and the top surface of the protective film 108 are coplanar and aligned with each other. In an exemplary embodiment, gap filler 110 is formed of a light-transmitting material (e.g., a light-transmitting material layer). In some embodiments, gap filler 110 is made of silicon oxide or polyimide.
[0059] refer to Figure 5 In subsequent steps, a first dielectric layer 112, a capping layer 114, and a first bonding film 116 are formed on the protective film 108 and the gap-filling material 110. In some embodiments, the first dielectric layer 112 is formed to extend from the optical region RG1 to the peripheral region RG2. In some embodiments, the first dielectric layer 112 is formed of a light-transmitting material (e.g., a light-transmitting material layer). In some embodiments, the first dielectric layer 112 is made of silicon oxide or polyimide. Furthermore, in some embodiments, the capping layer 114 is made of a material that can adjust or interfere with the transmission of optical signals, such as silicon nitride, silicon carbide, silicon oxynitride, etc.
[0060] refer to Figure 5 To prevent the presence of the cover layer 114 from interfering with optical signal transmission, the cover layer 114 has an opening 114-OP, which overlaps with the opening OR1 of the interconnect layer 104 (see Figure 104). Figures 2 to 3 The cover layer 114 with opening 114-OP overlaps with the optical region RG1. The method for forming the cover layer 114 with opening 114-OP is not particularly limited, and it can be formed by photolithography, etching, or using a mask layer. In some embodiments, the sidewalls of the cover layer 114 at opening 114-OP are aligned with the sidewalls of the protective film 108 disposed on opening RG1. In some embodiments, the width W2 of the opening 114-OP of the cover layer 114 is substantially equal to the width W1 of the optical region RG1.
[0061] like Figure 5Further shown, the first bonding film 116 is formed over the cap layer 114 and is located in the opening portion 114-OP. For example, in the optical region RG1, the first bonding film 116 is directly stacked on the top surface of the first dielectric layer 112. In addition, in the peripheral region RG2, the cap layer 114 is sandwiched between the first dielectric layer 112 and the first bonding film 116. In some embodiments, the first bonding film 116 is formed of a light-transmissive material (e.g., a light-transmissive material layer). In certain embodiments, the first bonding film 116 is made of silicon oxide or polyimide.
[0062] Referring to Figure 6 In subsequent steps, the passivation layer 106, the protection film 108, the first dielectric layer 112, the cap layer 114, and the first bonding film 116 are patterned by various photolithography and etching steps to form openings exposing the metallization pattern 104A of the interconnect layer 104. Next, a plurality of conductive patterns 118 are formed in the openings and are connected to the metallization pattern 104A. For example, the conductive patterns 118 are formed using suitable techniques such as damascene, dual damascene, electroplating, deposition, or a combination thereof.
[0063] In exemplary embodiments, forming the conductive patterns 118 includes forming a plurality of first bonding pads 118A, a plurality of via structures 118B connected to the first bonding pads 118A, and a barrier layer 118C surrounding the first bonding pads 118A and the via structures 118B. In some embodiments, the first bonding pads 118A are formed on the via structures 118B, where the first bonding pads 118A and the via structures 118B are formed of a conductive material such as copper. In certain embodiments, forming the barrier layer 118C is to prevent the conductive material from diffusing to adjacent layers (the first bonding film 116) and can also provide a function of increasing adhesion between the conductive material and the adjacent layers. In some embodiments, the barrier layer 118C is formed of a metal nitride, and for example, titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like. In some other embodiments, the barrier layer 118C can be omitted.
[0064] As Figure 6As shown, the conductive pattern 118 is formed in the peripheral region RG2 and not in the optical region RG1. In the illustrated embodiment, a first bonding pad 118A is disposed on the cap layer 114, and a top surface of the first bonding pad 118A is exposed from the first bonding film 116. In some embodiments, a via structure 118B and a barrier layer 118C are connected to the first bonding pad 118A, and are laterally surrounded by the passivation layer 106, the protection film 108, the first dielectric layer 112, and the cap layer 114. In other words, the passivation layer 106, the protection film 108, the first dielectric layer 112, and the cap layer 114 can be in physical contact with the barrier layer 118C surrounding the via structure 118B. After the conductive pattern 118 is formed, the electronic integrated circuit die 100 according to some embodiments of the present disclosure is completed.
[0065] Reference Figure 7 In a subsequent step, the photonic integrated circuit die 200 is bonded to the electronic integrated circuit die 100. In an exemplary embodiment, the photonic integrated circuit die 200 includes a semiconductor wafer 202 (semiconductor structure), a photonic layer 204, an interconnect layer 206, a second bonding film 208, and a plurality of second bonding pads 210. In some embodiments, the semiconductor wafer 202 is, for example, a silicon wafer or any other light-transmissive wafer, which can be singulated or diced at a later stage to form a semiconductor structure or substrate of the photonic integrated circuit die 200. The photonic layer 204 is disposed on the semiconductor wafer 202, and can include optical and optoelectronic components, such as grating couplers 204A, waveguides, photodetectors, directional couplers, and modulators (not shown). In some embodiments, the photonic layer 204 is disposed to overlap the opening OR1 or the optical region RG1 of the electronic integrated circuit die 100. In some embodiments, the interconnect layer 206 is disposed on the photonic layer 204, and includes a plurality of metallization patterns (not shown) embedded in the interconnect layer 206 for providing interconnects in the photonic integrated circuit die 200. In certain embodiments, a light-transmissive material is embedded in the interconnect layer 206 to allow optical signals to propagate through the electronic integrated circuit die 100. For example, portions of the interconnect layer 206 that overlap the opening OR1 or the optical region RG1 can be removed and filled with the light-transmissive material.
[0066] As Figure 7As shown, in some embodiments, the second bonding film 208 and the second bonding pads 210 are located on the interconnect layer 206. In some embodiments, the second bonding film 208 is formed of a light-transmissive material (e.g., a light-transmissive material layer). In certain embodiments, the material of the second bonding film 208 is silicon oxide or polyimide. Further, the second bonding pads 210 are embedded in the second bonding film 208, where the second bonding pads 210 are formed of a conductive material such as copper. In some embodiments, a barrier layer (not shown) can be selectively provided to surround the second bonding pads 210, where the barrier layer can be formed of a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like. In some embodiments, the second bonding film 208 and the second bonding pads 210 of the photonic integrated circuit die 200 are bonded to the first bonding film 116 and the first bonding pads 118A of the electronic integrated circuit die 100 by hybrid bonding. For example, the first bonding film 116 is directly bonded to the second bonding film 208, and the first bonding pads 118A are directly bonded to the second bonding pads 118A.
[0067] Referring to Figure 7 The optical fiber structure 302 can be disposed above the photonic integrated circuit die 200. For example, the optical fiber structure 302 can overlap the grating coupler 204A. In some embodiments, the optical fiber structure 302 is an optical input that transmits optical information / optical signals to the grating coupler 204A, and the optical information / optical signals can be further transmitted along the photonic layer 204 to other components. In certain embodiments, the light transmitted in the optical fiber structure 302 is projected onto the grating coupler 204A, and the grating coupler 204A has a function of receiving the light and transmitting the light to the photonic layer 204. After the photonic integrated circuit die 200 is bonded to the electronic integrated circuit die 100, the semiconductor chip 102 and the semiconductor chip 202 are diced or singulated to form the semiconductor structure 102 (or substrate) of the electronic integrated circuit die 100 and the semiconductor structure 202 (or substrate) of the photonic integrated circuit die 200, respectively.
[0068] Referring to Figure 8In some embodiments, the optical assembly 400 can also be disposed on the electronic integrated circuit die 100. In one embodiment, the optical signal is transmitted through an optical path PH1 between the photonic layer 204 of the photonic integrated circuit die 200 and the optical assembly 400. For example, the optical signal from the optical assembly 400 is transmitted along the optical path PH1 through the recess 102-CV and the optical relief structure LX1 of the semiconductor structure 102, through the protective film 108, the gap fill material 110, the first bonding film 116, and the second bonding film 208, and towards the photonic layer 204 of the photonic integrated circuit die 200. After providing the optical assembly 400, the semiconductor package PKX1 according to some embodiments of the present disclosure can be completed.
[0069] In exemplary embodiments, in the semiconductor package PKX1, the vertical distance along the optical path PH1 from the top surface of the protective film 108 (thus, not including the protective film 108 itself) on the recess 102-CV to the photonic layer 204 is free of materials selected from silicon nitride, silicon carbide, and silicon oxynitride. In some embodiments, the material disposed directly on the optical relief structure LX1 in the recess 102-CV of the semiconductor structure 102 (e.g., the protective film 108) can be made of silicon nitride or silicon oxynitride, while the material not disposed directly on the optical relief structure can further interfere with the transmission of the optical signal. Thus, in addition to being used in the protective film 108 to adjust the optical signal, these materials would be excluded from use along the optical path PH1. With the above configuration, the problem of optical signal loss during optical transmission in the semiconductor package PKX1 can be prevented, and the optical performance of the semiconductor package PKX1 can be improved.
[0070] Figures 9 to 13 are schematic top and cross-sectional views of various stages in a method of manufacturing a semiconductor package according to some other embodiments of the present disclosure. Figures 9 to 13 The method shown is similar to Figures 1 to 8 The method shown is similar to the method shown in FIG. 1. Thus, the same reference numerals will be used to denote the same or similar parts, and detailed descriptions thereof will be omitted here. Reference is made to Figure 9 After providing Figure 1 The structure shown is similar to the structure shown in FIG. 1. Thus, the same reference numerals will be used to denote the same or similar parts, and detailed descriptions thereof will be omitted here. Reference is made to
[0071] Reference is made to Figure 10In some embodiments, the interconnect layer 104, the passivation layer 106, and the first dielectric layer 112 are patterned to form an opening portion OR1. For example, portions of the interconnect layer 104, portions of the passivation layer 106, and portions of the first dielectric layer 112 are removed to form the opening portion OR1 that exposes the semiconductor wafer 102. In some embodiments, portions of the semiconductor wafer 102 are further removed to form a recess 102-CV in the semiconductor wafer 102.
[0072] Referring to Figure 11 In a subsequent step, the semiconductor wafer 102 is further patterned to form the optical relief structure LX1. Subsequently, a protective film 108 can be formed on the first dielectric layer 112 and in the opening portion OR1. For example, the protective film 108 is formed on sidewalls of the opening portion OR1 and conformally formed on the recess 102-CV of the semiconductor wafer 102. In exemplary embodiments, the protective film 108 can be used as a level for stopping etching when forming the conductive pattern 118 subsequently, and thus the capping layer 114 (as shown in the first embodiment) can be removed in the present embodiment. In some embodiments, the material of the protective film 108 can be a silicon-containing material, an oxide material, a nitride material, or a combination thereof, etc. In other embodiments, the material of the protective film 108 is not particularly limited, and can be an inorganic material, an organic material, a metallic material, a polymeric material, or a combination thereof, etc.
[0073] Referring to Figure 12 After forming the protective film 108, a gap-filling material 110 is formed in the opening portion OR1 of the interconnect layer 104 and in the optical region RG1. Subsequently, a first bonding film 116 is formed over the protective film 108, and a conductive pattern 118 including a plurality of first bonding pads 118A, a plurality of via structures 118B, and a barrier layer 118C is formed over the protective film 108 and surrounded by the first bonding film 116. For example, the conductive pattern 118 is electrically connected to the metallization pattern 104A of the interconnect layer 104. In addition, the protective film 108, the first dielectric layer 112, and the passivation layer 106 laterally surround the via structures 118B of the conductive pattern 118. After forming the conductive pattern 118, the electronic integrated circuit die 100 according to some embodiments of the present disclosure is completed.
[0074] Referring to Figure 13 The electronic integrated circuit die 100 is formed by the following steps. In a first step, a semiconductor wafer 102 is provided. In a second step, an interconnect layer 104 is formed on the semiconductor wafer 102. In a third step, a passivation layer 106 is formed on the interconnect layer 104. In a fourth step, a first dielectric layer 112 is formed on the passivation layer 106. In a fifth step, the interconnect layer 104, the passivation layer 106, and the first dielectric layer 112 are patterned to form an opening portion OR1. In a sixth step, a protective film 108 is formed on the first dielectric layer 112 and in the opening portion OR1. In a seventh step, a first bonding film 116 is formed over the protective film 108, and a conductive pattern 118 including a plurality of first bonding pads 118A, a plurality of via structures 118B, and a barrier layer 118C is formed over the protective film 108 and surrounded by the first bonding film 116. Figures 7 to 8The photonic integrated circuit die 200 is bonded to the electronic integrated circuit die 100 in the same manner as shown. Subsequently, the fiber structure 302 is disposed over the photonic integrated circuit die 200, and the optical assembly 400 can be further disposed on the electronic integrated circuit die 100. After the optical assembly 400 is provided, the semiconductor package PKX2 according to some embodiments of the present disclosure is completed. In the exemplary embodiment, in the semiconductor package PKX2, the vertical distance from the top surface of the protective film 108 on the recess 102-CV to the photonic layer 204 along the optical path PH1 (see the position in Figure 8
[0075] Figure 14 is a schematic cross-sectional view of a semiconductor package according to some other embodiments of the present disclosure. Figure 14 The semiconductor package PKX3 shown is similar to the semiconductor package PKX1 shown. Figure 8 Therefore, the same reference numerals are used to denote the same or similar parts, and detailed descriptions thereof will be omitted herein. The difference between the embodiments is the width W2 of the opening portion 114-OP of the cover layer 114.
[0076] As shown, the width W2 of the opening portion 114-OP of the cover layer 114 is less than the width W1 of the optical region RG1. In other words, the sidewall of the cover layer 114 is not aligned with the sidewall of the protective film 108 disposed on the opening portion OR1. In the exemplary embodiment, the opening portion 114-OP of the cover layer 114 still overlaps with the opening portion OR1 or the optical region RG1 of the electronic integrated circuit die 100, and the cover layer 114 does not overlap with the central portion of the optical relief structure LX1 or exposes the central portion of the optical relief structure LX1. In this way, this can enable the optical signal from the optical assembly 400 to be transmitted along the optical path PH1 to the photonic layer 204 with minimal optical loss. Figure 14 In the exemplary embodiment, in the semiconductor package PKX3, the vertical distance from the top surface of the protective film 108 on the optical relief structure LX1 of the recess 102-CV to the photonic layer 204 along the optical path PH1 (see the position in
[0077] Figure 8 In this way, the problem of optical signal loss during optical transmission in the semiconductor package PKX3 can be prevented, and the optical performance of the semiconductor package PKX3 can be improved.
[0078] Figure 15 This is a schematic cross-sectional view of a semiconductor package according to some other embodiments of this disclosure. Figure 15 The semiconductor package PKX4 shown is Figure 8 The semiconductor package PKX1 shown is similar. Therefore, the same reference numerals will be used to denote the same or similar parts, and their detailed descriptions will be omitted here. The difference between the embodiments lies in the width W2 of the opening 114-OP of the cover layer 114.
[0079] like Figure 15 As shown, the width W2 of the opening 114-OP of the cover layer 114 is greater than the width W1 of the optical region RG1. In other words, the sidewalls of the cover layer 114 are not aligned with the sidewalls of the protective film 108 disposed on the opening OR1. In an exemplary embodiment, the opening 114-OP of the cover layer 114 overlaps with the opening OR1 or the optical region RG1 of the electronic integrated circuit die 100, and the cover layer 114 does not overlap with the central portion of the optical convex-concave structure LX1, or exposes the central portion of the optical convex-concave structure LX1. In this way, the optical signal from the optical component 400 can be transmitted to the photonic layer 204 along the optical path PH1 with minimal optical loss. In some embodiments, the conductive pattern 118 is formed on top of the cover layer 114. Therefore, during the formation of the opening 114-OP, portions of the cover layer 114 over which the conductive pattern 118 is not disposed can be further removed to increase the width of the opening 114-OP. For example, in some embodiments, the sidewalls of the cover layer 114 are aligned with the sidewalls of the first bonding pad 118A.
[0080] In an exemplary embodiment, within the semiconductor package PKX4, along the optical path PH1 (see... Figure 8 The vertical distance from the top surface of the protective film 108 on the recess 102-CV to the photonic layer 204 is not selected from materials composed of silicon nitride, silicon carbide, and silicon oxynitride. In this way, the problem of optical signal loss during optical transmission in the semiconductor package PKX4 can be prevented, and the optical performance of the semiconductor package PKX4 can be improved.
[0081] Figure 16 This is a schematic cross-sectional view of a semiconductor package according to some other embodiments of this disclosure. Figure 16 The semiconductor package PKX5 shown is Figure 8 The semiconductor package PKX1 shown is similar. Therefore, the same reference numerals will be used to indicate the same or similar parts, and their detailed descriptions will be omitted here. The difference between the embodiments is that the first dielectric layer 112 and the first bonding film 116 are further removed from the optical region RG1 of the semiconductor package PKX5.
[0082] refer to Figure 16The semiconductor package PX5 shown, in some embodiments, the first dielectric layer 112 and the first bonding film 116 can be formed of any dielectric material, which can be light-transmissive or non-light-transmissive. In the present exemplary embodiment, the first dielectric layer 112 and the first bonding film 116 are further removed from the optical region RG1 by a patterning process to expose the underlying gap filling material 110. Then, a second gap filling material 111 can be formed over the gap filling material 110 to fill the optical region RG1. For example, the second gap filling material 111 is formed of a light-transmissive material (e.g., a light-transmissive material layer) and can be made of silicon oxide or polyimide.
[0083] In some embodiments, there is an interface between the gap filling material 110 and the second gap filling material 111. In addition, the light-transmissive material used in the gap filling material 110 can be the same or different from the light-transmissive material used in the second gap filling material 111. In the exemplary embodiment, since the second gap filling material 111 is used to replace the first dielectric layer 112 and the first bonding film 116 in the optical region RG1, the first dielectric layer 112 and the first bonding film 116 can be formed of a non-light-transmissive material without interfering with the transmission of light.
[0084] Similarly, in the semiconductor package PKX5 of the present disclosure, the vertical distance along the optical path PH1 from the top surface of the protective film 108 on the recess 102-CV to the photonic layer 204 (see the position in Figure 8 In this way, the problem of loss of optical signal during light transmission in the semiconductor package PKX5 can be prevented, and the optical performance of the semiconductor package PKX5 can be improved.
[0085] In the above embodiments, the electronic integrated circuit die (EIC die) and the photonic integrated circuit die (PIC die) are integrated or bonded together to form a semiconductor package, in which the presence of a cladding layer in the optical path between the EIC die and the PIC die is omitted. In addition, the bonding pads or metal wiring along the optical path are also removed. In this way, the problem of loss of optical signal during light transmission in the semiconductor package can be avoided, and the optical performance of the semiconductor package can be improved.
[0086] According to some embodiments of the present disclosure, a semiconductor package includes an electronic integrated circuit die and a photonic integrated circuit die. The electronic integrated circuit die includes a semiconductor structure, an interconnect layer, a passivation layer, a protection film, a gap fill material, and a plurality of first bonding pads. The semiconductor structure includes a recess. The interconnect layer is disposed on the semiconductor structure, wherein the interconnect layer has an opening exposing the recess of the semiconductor structure. The passivation layer is disposed on the interconnect layer. The protection film is disposed on the interconnect layer above the passivation layer and on sidewalls of the opening, wherein the protection film is further disposed on the recess of the semiconductor structure. The gap fill material is disposed in the opening of the interconnect layer and surrounded by the interconnect layer. The first bonding pads are disposed on the protection film. The photonic integrated circuit die is bonded to the electronic integrated circuit die and includes a photonic layer and a plurality of second bonding pads. The photonic layer overlaps the opening of the interconnect layer, wherein optical signals are transmitted through an optical path between the photonic layer and the recess of the semiconductor chip. The second bonding pads are disposed above the photonic layer, wherein the second bonding pads are directly bonded to the first bonding pads.
[0087] In some embodiments, sidewalls of the cap layer at the opening portion are misaligned with sidewalls of the protection film disposed on the opening. In some embodiments, the semiconductor package further includes via structures electrically connecting the plurality of first bonding pads to the interconnect layer, wherein the via structures are laterally surrounded by the passivation layer and the protection film. In some embodiments, the electronic integrated circuit die further includes a first bonding film surrounding the plurality of first bonding pads, and the first bonding film is disposed on the protection film and above the gap fill material, and the photonic integrated circuit die further includes a second bonding film surrounding the plurality of second bonding pads, and wherein the first bonding film is attached to the second bonding film.
[0088] According to some other embodiments of the present disclosure, a semiconductor package includes a photonic integrated circuit die having a photonic layer and an electronic integrated circuit die bonded to the photonic integrated circuit die. The electronic integrated circuit die includes an optical region allowing optical signals to be transmitted to the photonic layer through the optical region and a peripheral region outside the optical region. The optical region includes a plurality of optical relief structures, a protection film, and a light-transmissive material layer. The optical relief structures are formed by a semiconductor structure. The protection film is conformally disposed above the optical relief structures, wherein the protection film extends to the peripheral region. The light-transmissive material layer is disposed above the protection film and fills the optical region. The peripheral region includes a plurality of first bonding pads bonded to the photonic integrated circuit die and a plurality of via structures connected to the plurality of first bonding pads, wherein the protection film laterally surrounds sidewalls of the plurality of via structures.
[0089] In some embodiments, the light-transmissive material layer includes a gap-fill material layer disposed on the protective film and at least one first dielectric layer disposed on the gap-fill material layer, wherein a top surface of the gap-fill material layer is aligned with a top surface of the protective film. In some embodiments, the semiconductor package further includes a cap layer disposed on the protective film, wherein the cap layer includes an open portion overlapping the optical region. In some embodiments, a width of the open portion is less than a width of the optical region. In some embodiments, the width of the open portion is equal to the width of the optical region.
[0090] According to another embodiment of the disclosure, a method of fabricating a semiconductor package is described. The method includes forming an electronic integrated circuit die by the following steps. A semiconductor structure is provided, and an interconnect layer is formed on the semiconductor structure. A passivation layer is formed on the interconnect layer. The interconnect layer is patterned to form an opening exposing the semiconductor structure, and a portion of the semiconductor structure is removed to form a recess in the semiconductor structure. A protective film is formed on the interconnect layer above the passivation layer and on sidewalls of the opening, wherein the protective film is further formed on the recess of the semiconductor structure. A gap-fill material is formed in the opening of the interconnect layer and surrounded by the interconnect layer. A plurality of first bonding pads are formed on the protective film. The method further includes bonding a photonic integrated circuit die to the electronic integrated circuit die, wherein the photonic integrated circuit die includes a photonic layer and a plurality of second bonding pads. The photonic layer overlaps the opening of the interconnect layer, wherein an optical signal is transmitted through an optical path between the photonic layer and the recess of the semiconductor die. The second bonding pads are disposed above the photonic layer, wherein the second bonding pads are directly bonded to the first bonding pads.
[0091] In some embodiments, forming the recess in the semiconductor structure includes forming a plurality of optical relief structures in the semiconductor structure. In some embodiments, the method further includes forming a cap layer on the protective film, and patterning the cap layer to form an open portion overlapping the opening of the interconnect layer. In some embodiments, after the cap layer is patterned to form the open portion, sidewalls of the cap layer at the open portion are aligned with sidewalls of the protective film disposed on the opening. In some embodiments, the method further includes forming a via structure disposed on and electrically connected to the interconnect layer, wherein the via structure is laterally surrounded by the passivation layer and the protective film, and forming a plurality of first bonding pads on the via structure.
[0092] The foregoing summary has outlined several features of the embodiments so that those skilled in the art can better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.
Claims
1. A semiconductor package, characterized by, Comprising: an electronic integrated circuit die comprising; a semiconductor structure comprising a recess; an interconnect layer disposed on the semiconductor structure, wherein the interconnect layer has an opening portion exposing the recess of the semiconductor structure; a passivation layer disposed on the interconnect layer; a protective film disposed on the passivation layer and above the interconnect layer and on sidewalls of the opening portion, wherein the protective film is further disposed on the recess of the semiconductor structure; a gap fill material disposed in the opening portion of the interconnect layer and surrounded by the interconnect layer; a plurality of first bonding pads disposed on the protective film; a photonic integrated circuit die bonded to the electronic integrated circuit die and comprising: a photonic layer overlapping the opening portion of the interconnect layer; and a plurality of second bonding pads disposed above the photonic layer, wherein the plurality of second bonding pads are bonded to the plurality of first bonding pads. The recess of the semiconductor structure further comprises a plurality of optical relief structures formed by the semiconductor structure.
2. The semiconductor package of claim 1, wherein, A vertical distance from a top surface of the protective film on the recess to the photonic layer does not contain a material selected from silicon nitride, silicon carbide, and silicon oxynitride.
3. The semiconductor package of claim 1, wherein, The semiconductor package further comprises a cap layer disposed below the plurality of first bonding pads, wherein the cap layer has an opening portion overlapping the opening portion of the interconnect layer.
4. The semiconductor package of claim 1, wherein, Sidewalls of the cap layer at the opening portion are aligned with sidewalls of the protective film disposed on the opening portion.
5. The semiconductor package of claim 4, wherein, Comprising:
6. A semiconductor package, characterized by, a photonic integrated circuit die comprising a photonic layer; an electronic integrated circuit die bonded to the photonic integrated circuit die and comprising an optical region overlapping the photonic layer and a peripheral region outside the optical region, wherein the optical region comprises: a plurality of optical relief structures formed by a semiconductor structure; a protective film disposed above the plurality of optical relief structures, wherein the protective film extends to the peripheral region; and a light-transmissive material layer disposed above the protective film and filling the optical region; wherein the peripheral region comprises: a plurality of first bonding pads bonded to the photonic integrated circuit die; and a plurality of via structures connected to the plurality of first bonding pads, wherein the protective film laterally surrounds sidewalls of the plurality of via structures. The optical region is composed of the plurality of optical relief structures, the protective film, and the light-transmissive material layer, and the light-transmissive material layer is made of silicon oxide or polyimide.
7. The semiconductor package of claim 6, wherein, 8. The semiconductor package of claim 7, wherein the light-transmissive material layer comprises a gap fill material layer disposed on the protective film and at least one first dielectric layer disposed on the gap fill material layer, wherein a top surface of the gap fill material layer is aligned with a top surface of the protective film. The semiconductor package further comprises a cap layer disposed on the protective film, wherein the cap layer comprises an opening portion overlapping the optical region.
9. The semiconductor package of claim 6, wherein the semiconductor package is a flip chip semiconductor package. The peripheral region further comprises a passivation layer laterally surrounding the sidewalls of the plurality of via structures and in contact with sidewalls of the protective film.
10. The semiconductor package of claim 6, wherein,