Protection circuit of semiconductor charging device model and semiconductor device
By designing a combination of power pads, ground pads, ESD and CDM protection elements and protection switches in semiconductor devices, the problem of electrostatic discharge protection for CMOS is solved, effective protection is achieved in different operating modes, and the CDM tolerance and ESD protection reliability are improved.
Patent Information
- Application Number
- CN202423072917.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2034-12-11
AI Technical Summary
In the prior art, semiconductor devices lack effective CDM protection during electrostatic discharge, especially when the input/output circuits are disabled and enabled. The CDM tolerance is weak, and the ESD protection components are easily damaged, which cannot effectively protect the CMOS circuits.
A protection circuit for a semiconductor charging device model is designed, including a power pad, a ground pad, an ESD protection element, and a CDM protection element. The protection switch switches between different states and combines double bonding and normal bonding techniques to provide effective protection when the input/output circuit is disabled and enabled, respectively.
When the input/output circuit is disabled, the protection switch is open to prevent circuit damage; when enabled, the protection switch is closed to effectively suppress static voltage, protect the CMOS circuit from damage, and improve the CDM tolerance and ESD protection reliability.
Smart Images
Figure CN223527781U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of semiconductor, especially a protection circuit of semiconductor charged device model and semiconductor device. BACKGROUND
[0002] Charged Device Model (CDM) is a model for evaluating semiconductor devices in Electrostatic Discharge (ESD). The discharge path and speed of CDM are very short and fast, and the peak current of discharge can be very large. Compared with other ESD models such as Human Body Model (HBM) and Machine Model (MM), CDM often poses a higher risk to semiconductor devices. Therefore, a corresponding protection circuit is set to protect the Complementary Metal-Oxide-Semiconductor (CMOS) in the semiconductor device.
[0003] Due to the requirements of chip functions, there are cases where the input / output circuit needs to be disabled. When the input / output circuit is disabled, the input / output pad is usually connected to the VSS or VDD pin. In the floating state, when electrostatic discharge is applied to the adjacent package pin, the discharge between the pins to the input / output pad will cause the circuit function to be disturbed. In this case, due to the limited number of package pins, the Double bonding (connecting the input / output pad and the ground pad to the VSS or VDD pin) technique can be used to avoid wasting package pins.
[0004] When using the Double bonding technique, the input / output pad usually has a relatively weak CDM tolerance. This is due to physical space limitations and limitations of package design. It is difficult to place CDM protection elements in this configuration. In addition, even if CDM protection elements can be placed, the CDM protection elements themselves are prone to damage during ESD testing. Therefore, when the input / output circuit is enabled by the Normal bonding (connecting the input / output pad to the package pin and connecting the ground pad to the VSS or VDD pin) technique, the CDM tolerance is also weak due to the lack of appropriate CDM protection scheme. Therefore, there is room for improvement. SUMMARY
[0005] The utility model aims at providing a protection circuit of semiconductor charged device model and semiconductor device to protect the CMOS.
[0006] To solve the above technical problems, the utility model is realized by the following technical solutions:
[0007] The utility model provides a kind of protection circuit of semiconductor charging device model, comprising:
[0008] Power supply pad, connect with first power wiring;
[0009] Ground pad, connect with second power wiring;
[0010] ESD protection element, connect between the power supply pad and the ground pad;
[0011] CDM protection element, connect between the power supply pad and the ground pad;And
[0012] Input / output pad, it is connected with the ESD protection element, the CDM protection element and the gate of complementary metal oxide semiconductor respectively;Wherein, the source of the complementary metal oxide semiconductor is connected with the power supply pad, and its drain is connected with the ground pad;
[0013] Wherein, the CDM protection element has protection switch, and the protection switch is connected with the gate of the complementary metal oxide semiconductor.
[0014] In an embodiment of the utility model, when the input / output circuit is disabled, the protection switch is in open state, and the ground pad and the input / output pad are connected to ground pin simultaneously.
[0015] In an embodiment of the utility model, when the input / output circuit is enabled, the protection switch is in closed state, the input / output pad is connected to package pin, and the ground pad is connected to ground pin.
[0016] In an embodiment of the utility model, the ESD protection element includes:
[0017] First transistor, its gate and source are connected with the power supply pad simultaneously;And
[0018] Second transistor, its gate and drain are connected with the ground pad simultaneously;
[0019] Wherein, the drain of the first transistor and the source of the second transistor are connected with the input / output pad simultaneously.
[0020] In an embodiment of the utility model, the first transistor is GDPMOS, and the second transistor is GGNMOS.
[0021] In an embodiment of the utility model, the CDM protection element includes:
[0022] Third transistor, its gate and source are connected with the power supply pad simultaneously, and its drain is connected with the gate of the complementary metal oxide semiconductor.
[0023] a fourth transistor, whose gate and drain are connected to the ground pad simultaneously; and
[0024] a protection switch connected between the source of the fourth transistor and the gate of the complementary metal oxide semiconductor.
[0025] In an embodiment of the present application, the third transistor is a GDPMOS, the fourth transistor is a GGNMOS, and the protection switch is a metal mask selection template.
[0026] In an embodiment of the present application, the semiconductor charging device model further comprises a resistance element connected between the drain of the first transistor and the drain of the third transistor.
[0027] In an embodiment of the present application, the first power supply wiring is a positive power voltage line, and the second power supply wiring is a ground or zero voltage line.
[0028] The present application also provides a semiconductor device comprising the protection circuit of the semiconductor charging device model.
[0029] As described above, the present application provides a protection circuit of a semiconductor charging device model and a semiconductor device, in which, during the testing process, when the input / output circuit is disabled, the protection switch can be set to be in an open state, and at the same time, the ground pad and the input / output pad are connected to the ground pin simultaneously by using Double bonding technology, at this time, the fourth transistor in the circuit cannot work, thereby the CMOS can be effectively prevented from being damaged.
[0030] Of course, it is not necessary for any product implementing the present application to achieve all the advantages described above simultaneously. BRIEF DESCRIPTION OF DRAWINGS
[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.
[0032] Figure 1A schematic diagram of a protection circuit for a semiconductor charging device model;
[0033] Figure 2 A schematic diagram of a protection circuit for a semiconductor charging device model when using Double bonding technology;
[0034] Figure 3 A schematic diagram of a protection circuit for a semiconductor charging device model when using Normal bonding technology;
[0035] Figure 4 A schematic diagram of an input / output circuit of a protection circuit for a semiconductor charging device model when enabled;
[0036] Figure 5 A schematic diagram of an input / output circuit of a protection circuit for a semiconductor charging device model when disabled.
[0037] In the figure: 10, package pin; 20, ground pin; 30, power supply pad; 40, ground pad; 50, input / output pad; 60, first transistor; 70, second transistor; 80, third transistor; 90, fourth transistor; 100, protection switch; 110, resistance element; 120, first element; 130, second element; 140, first power supply wiring; 150, second power supply wiring. DETAILED DESCRIPTION
[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0039] Please refer to Figure 1 , Figure 4 and Figure 5 The present application provides a protection circuit for a semiconductor charging device model, which comprises a package pin 10, a ground pin 20, a power supply pad 30, a ground pad 40, an input / output pad 50, an ESD protection element, a CDM protection element, a resistance element 110, a first power supply wiring 140 and a second power supply wiring 150. The ESD protection element and the CDM protection element can be used to protect a complementary metal oxide semiconductor (CMOS).
[0040] In one embodiment, package pin 10 can be a physical interface between a semiconductor device and a printed circuit board (PCB). In ESD protection, package pin 10 can be directly subjected to electrostatic shock, and thus package pin 10 can be connected to an internal ESD protection circuit to direct the electrostatic discharge to a safe path, mitigating the impact on the circuit. The number of package pins 10 can be unlimited, such as two, three, four, etc.
[0041] In one embodiment, ground pin 20 can serve as a negative supply or ground pin for the protection circuit to serve as a return path for ESD current. In the event of an ESD event, the protection circuit can direct the unusually high voltage to ground pin 20, safely directing the shock current back to ground, thereby protecting sensitive components.
[0042] In one embodiment, power pad 30 can serve as an access point to provide a positive supply. Power pad 30 can be connected to a power supply pin of the semiconductor device. In the event of an ESD event, power pad 30 can be connected to an ESD protection circuit to ensure that any possible electrostatic discharge does not affect the power routing.
[0043] In one embodiment, ground pad 40 can serve as an access point to provide a negative supply or ground. Ground pad 40 can be connected to a power supply pin of the semiconductor device. In the event of an ESD event, ground pad 40 can be connected to an ESD protection circuit as a return path for current, directing ESD current to ground to reduce damage to the circuit.
[0044] In one embodiment, input / output pad 50 refers to an interface between the semiconductor device and external components for receiving input signals or output signals. Input / output pad 50 can be connected to an ESD protection component, a CDM protection component, and a CMOS gate.
[0045] In one embodiment, first power routing 140 can be represented as a positive supply voltage line. Second power routing 150 can be represented as a ground or zero voltage line. First power routing 140 and second power routing 150 are respectively a power supply and a ground system in the protection circuit. Among them, power pad 30 can be connected to first power routing 140, and ground pad 40 can be connected to second power routing 150.
[0046] In one embodiment, an ESD protection element can be connected between the power pad 30 and the ground pad 40. The ESD protection element can be used to prevent damage to the CMOS from external static electricity. Static electricity discharge is a common phenomenon that can cause permanent damage to sensitive electronic components when the static electricity builds up to a certain level and is suddenly released in a powerful current. The ESD protection element protects the CMOS from damage by providing a low impedance path to release the static electricity energy.
[0047] Referring to Figure 1 , Figure 4 and Figure 5 In one embodiment, the ESD protection element can include a first transistor 60 and a second transistor 70. The ESD protection element can quickly conduct and release static electricity energy when the external static electricity is excessive, thereby protecting the CMOS circuit from the static electricity discharge. The first transistor 60 and the second transistor 70 cooperatively form an effective ESD protection network through complementation and cooperation. The first transistor 60 can be a GDPMOS. The second transistor 70 can be a GGNMOS.
[0048] In one embodiment, the gate of the first transistor 60 can be connected to the source of the CMOS, and the source of the first transistor 60 can be connected to the source of the CMOS. When the voltage of the source of the CMOS changes, the voltage of the gate and the source of the first transistor 60 also changes synchronously, so that the first transistor 60 forms a low impedance path between the source and the drain, thereby quickly releasing the static electricity energy.
[0049] In one embodiment, the drain of the first transistor 60 can be connected to the gate of the CMOS, and the source of the second transistor 70 can be connected to the drain of the first transistor 60. When the external static electricity is transmitted to the gate of the CMOS through the drain, the first transistor 60 can quickly conduct to direct the static electricity energy to the source, thereby protecting the gate of the CMOS from damage by excessive voltage.
[0050] In one embodiment, the source of the second transistor 70 can be connected to the gate of the CMOS, and the drain of the first transistor 60 can be connected to the source of the second transistor 70. When the external static electricity is transmitted to the gate of the CMOS through the drain, the second transistor 70 can quickly conduct to direct the static electricity energy to the source, thereby further protecting the gate of the CMOS from damage by excessive voltage.
[0051] In one embodiment, the gate of the second transistor 70 can be connected to the drain of the CMOS, and the drain of the second transistor 70 can be connected to the drain of the CMOS. When the voltage of the drain of the CMOS changes, the voltage of the gate and the drain of the second transistor 70 also changes synchronously, so that the second transistor 70 forms a low impedance path between the drain and the source, thereby quickly releasing the static electricity energy.
[0052] Referring toFigure 1 、 Figure 4 and Figure 5 In one embodiment, the CMOS can include a first element 120 and a second element 130. The first element 120 can be a P-channel MOSFET (PMOS). The second element 130 can be an N-channel MOSFET (NMOS).
[0053] In one embodiment, the source of the first element 120 can be connected to the power supply pad 30. The gate of the first element 120 can be connected to the gate of the second element 130 and to the input / output pad 50. The drain of the first element 120 can be connected to the source of the second element 130. The source of the second element 130 can be connected to the drain of the first element 120. The gate of the second element 130 can be connected to the gate of the first element 120 and to the input / output pad 50. The drain of the second element 130 can be connected to the ground pad 40.
[0054] Referring to Figure 2 In one embodiment, in the design of a semiconductor device, the input / output (I / O) circuit can need to be disabled due to the fact that certain functions are not required in some modes, or other circuit functions have higher priority. In this case, the input / output pad 50 can be connected to the ground pin 20 or the VDD pin to ensure that it is in a known, safe state and not floating. The case of connecting to the ground pin 20 is described as an example.
[0055] Referring to Figure 2 In one embodiment, when the input / output pad 50 is in a floating state, electrostatic discharge from an adjacent package pin 10 can flow into the chip through this floating input / output pad 50, causing current to flow in a path that it should not, causing circuit function disorder or damage. Since the number of package pins 10 is limited, adding extra pins to handle the input / output pad 50 can cause waste of space and cost. Therefore, the Double bonding technology can be used to make a single pin have multiple connection modes in different operation modes, saving the number of pins and making the package design more efficient. In this embodiment, the Double bonding technology can allow a package pin 10 to be connected to two different points on the chip, for example, the ground pin 20 can be connected to the ground pad 40 and the input / output pad 50, and when the input / output function is required, it is connected to the corresponding signal line.
[0056] Referring to Figure 2In one embodiment, when Double bonding technique is used, it can not be feasible to add CDM protection components due to limited physical space on the package and chip, and therefore the input / output pad 50 can not have enough space to place sufficient CDM protection components. The space limitation, combined with package design constraints, can result in a weak tolerance of the input / output pad 50 to CDM events and inadequate protection.
[0057] Referring to Figure 2 In one embodiment, when the input / output circuit is disabled and the ground pad 40 is connected to the ground pin 20 simultaneously with the input / output pad 50 using Double bonding technique, the package space on the chip remains tight, and therefore it can be difficult to add sufficient CDM protection components. In some special designs, even if some protection components can be placed, the protection components can not be able to provide sufficient protection during ESD events due to package constraints. The protection components can be damaged during discharging and therefore lose their protective effect, resulting in a weak tolerance of CDM even with the presence of protection components.
[0058] Referring to Figure 2 and Figure 3 In one embodiment, during the ESD test procedure, the ground pin 20 is treated as a common pin to all other package pins 10 in the test. During the test, each pin is subjected to the application of ESD stress, and the number of times is typically matched to the number of pins in the device, i.e., each package pin 10 is subjected to an ESD test with the ground pin 20. Since all ESD test pulses are applied through the ground pin 20, the input / output pad 50 is repeatedly subjected to all ESD events from other pins. When protection components are connected to the input / output pad 50, the protection components are exposed to each test and therefore subjected to the total number of ESD tests equal to the number of pins. Since ESD test pulses are typically high amplitude, fast rise time voltages, i.e., high energy charge transfer, even well-designed protection components can degrade or be damaged after multiple pulses. Therefore, the protection components on the input / output pad 50 in the Double bonding technique case are at a higher risk of being damaged during ESD tests since the total number of pulses they receive is typically higher than that of a pin that is not connected using Double bonding technique.
[0059] Referring to Figure 4 and Figure 5In one embodiment, a CDM protection element can be connected between the power pad 30 and the ground pad 40. The CDM protection element is used to protect the CMOS from internal static electricity. Internal static electricity refers to the damage to internal circuits due to the accumulation and release of electrical charges during manufacturing, testing and use. The CDM protection element protects the CMOS by providing a low impedance path to quickly release the static electricity energy.
[0060] Referring to Figure 4 and Figure 5 In one embodiment, the CDM protection element includes a third transistor 80, a fourth transistor 90, and a protection switch 100. The third transistor 80 can be a GDPMOS. The fourth transistor 90 can be a GGNMOS.
[0061] In one embodiment, the gate of the third transistor 80 can be connected to the power pad 30. The source of the third transistor 80 can be connected to the power pad 30. The drain of the third transistor 80 can be connected to the gate of the CMOS.
[0062] In one embodiment, the gate of the fourth transistor 90 can be connected to the ground pad 40. The drain of the fourth transistor 90 can be connected to the ground pad 40. The source of the fourth transistor 90 can be connected to one end of the protection switch 100. The other end of the protection switch 100 can be connected to the gate of the CMOS. The protection switch 100 can provide a low impedance path to further ensure that the gate voltage of the CMOS does not exceed the safe range when additional protection is needed.
[0063] In one embodiment, the protection switch 100 can be a metal mask option, which refers to the use of one or more layers of specific patterned masks during the multi-layer metal interconnection process. The mask can be used in the photolithography process to accurately deposit metal material on the surface of the semiconductor device to form the protection switch 100, such as the interconnection between transistors, between transistors and I / O ports, etc. In this embodiment, the protection switch 100 can be selectively used to modify the connection of the metal layer. The protection switch 100 can be used to determine whether the CDM protection element is connected to the circuit or disconnected.
[0064] Referring to Figure 4 and Figure 5In one embodiment, one end of the resistive element 110 can be connected to the input / output pad 50 and the other end can be connected to the gate of the CMOS. The resistive element 110 can be positioned between the connection of the drain of the first transistor 60 and the source of the second transistor 70, and between the connection of the drain of the third transistor 80 and the source of the fourth transistor 90. The resistive element 110 can function to divide voltage and limit current flow, to reduce the current flow of the CMOS, to prevent a high input voltage from directly affecting the gate of the CMOS, and to protect the CMOS from damage.
[0065] Referring to Figure 4 In one embodiment, when the input / output circuit is enabled using the Normal bonding technique, the CDM tolerance is also weak. That is, the ground pad 40 is connected to the ground pin 20 and the input / output pad 50 is connected to the package pin 10, and without providing appropriate ESD protection, the input / output pad 50 is also subject to weak CDM tolerance.
[0066] Referring to Figure 4 In one embodiment, when the input / output circuit is enabled, the input / output pad 50 is connected to the package pin 10 and the ground pad 40 is connected to the ground pin 20 using the Normal bonding technique. At this time, the protection switch 100 can be set to the closed state, and the fourth transistor 90 is connected to the circuit. In this configuration, the fourth transistor 90 is activated and conducts current, and can protect the connected CMOS in the event of a high voltage or ESD event. The on state means that the fourth transistor 90 can respond to and suppress voltages that can cause damage by diverting excess charge to ground, to protect the sensitive CMOS.
[0067] Referring to Figure 5 In one embodiment, when the input / output circuit is disabled, the ground pad 40 and the input / output pad 50 are simultaneously connected to the ground pin 20 using the Double bonding technique. At this time, the protection switch 100 can be set to the open state, and the fourth transistor 90 is disconnected and does not conduct current in the circuit. In this configuration, since the input / output circuit is disabled, connecting the input / output pad 50 directly to the ground pin 20 can prevent current from flowing into the circuit from external interference or ESD when the input / output circuit is not in use, and thus can prevent the CMOS from being damaged. At the same time, in this case, the fourth transistor 90 does not need to protect the CMOS.
[0068] The utility model further provides a semiconductor device, it can include the protection circuit of semiconductor charging device model above, can pass through the protection circuit and protect the CMOS in semiconductor device. The utility model further provides a semiconductor device, it can include the protection circuit of semiconductor charging device model above, can pass through the protection circuit and protect the CMOS in semiconductor device.
[0069] It can be seen that in the above scheme, during the test, the unexpected effect is that when the input / output circuit is disabled, the protection switch can be set to be in the open state, and at the same time, the Double bonding technology is used to connect the ground pad and the input / output pad to the ground pin, at this time, the fourth transistor in the circuit cannot work, and then the CMOS can be effectively avoided from being damaged. When the input / output circuit is enabled, the protection switch can be set to be in the closed state, and at the same time, the Normal bonding technology is used to connect the input / output pad to the package pin and connect the ground pad to the ground pin, at this time, the fourth transistor in the circuit works, can respond and suppress the voltage that may cause damage, and by transferring the excess charge to the ground, the sensitive CMOS is protected.
[0070] The above disclosed embodiments of the utility model are only used to help explain the utility model. The embodiments do not describe all the details, and the utility model is not limited to the specific implementation method. Obviously, according to the content of the specification, many modifications and changes can be made. The specification selects and specifically describes these embodiments, in order to better explain the principle and practical application of the utility model, so that the person skilled in the art can well understand and utilize the utility model. The utility model is limited by the claims and the whole scope and equivalents.
Claims
1. A protection circuit for a semiconductor charge storage device model, characterized by, comprises: a power supply pad connected to a first power supply line; a ground pad connected to a second power supply line; an ESD protection element connected between the power supply pad and the ground pad; a CDM protection element connected between the power supply pad and the ground pad; and an input / output pad connected to the ESD protection element, the CDM protection element, and a gate of a complementary metal oxide semiconductor, respectively; wherein a source of the complementary metal oxide semiconductor is connected to the power supply pad, and a drain of the complementary metal oxide semiconductor is connected to the ground pad; wherein the CDM protection element has a protection switch connected to the gate of the complementary metal oxide semiconductor. When the input / output circuit is disabled, the protection switch is in an open state, and the ground pad and the input / output pad are simultaneously connected to a ground pin.
2. The protection circuit for a semiconductor charging device model according to claim 1, characterized by, When the input / output circuit is enabled, the protection switch is in a closed state, the input / output pad is connected to a package pin, and the ground pad is connected to a ground pin.
3. The protection circuit for a semiconductor charging device model according to claim 1, characterized by, The ESD protection element comprises:
4. The protection circuit for a semiconductor charging device model according to claim 1, characterized by a first transistor having a gate and a source both connected to the power supply pad; and a second transistor having a gate and a drain both connected to the ground pad; wherein a drain of the first transistor and a source of the second transistor are both connected to the input / output pad. The first transistor is a GDPMOS, and the second transistor is a GGNMOS.
5. The protection circuit for a semiconductor charging device model according to claim 4, characterized by The CDM protection element comprises:
6. The protection circuit for a semiconductor charging device model according to claim 4, wherein a third transistor having a gate and a source both connected to the power supply pad, and a drain connected to the gate of the complementary metal oxide semiconductor; a fourth transistor having a gate and a drain both connected to the ground pad; and a protection switch connected between a source of the fourth transistor and the gate of the complementary metal oxide semiconductor. The third transistor is a GDPMOS, the fourth transistor is a GGNMOS, and the protection switch is a metal mask select template.
7. The protection circuit for a semiconductor charging device model according to claim 6, wherein Further comprising a resistance element connected between a drain of the first transistor and a drain of the third transistor.
8. The protection circuit for a semiconductor charging device model according to claim 6, wherein The first power supply line is a positive power supply voltage line, and the second power supply line is a ground or zero voltage line.
9. The protection circuit for a semiconductor charging device model according to claim 1, characterized by, A protection circuit for a semiconductor charging device model as claimed in any one of claims 1 to 9.
10. A semiconductor device, characterized by comprising: