DP-to-HDMI processing equipment

Abstract

The utility model discloses processing equipment for converting DP into HDMI. The processing equipment comprises a main control unit, a first interface unit, a second interface unit, a level conversion unit and a boost unit, the main control unit is electrically connected with the first interface unit and the second interface unit, and establishes communication connection between the signal source equipment and the signal receiving equipment; the main control unit is electrically connected with the level conversion unit and exchanges data with equipment; the boost unit boosts the voltage. Therefore, the main control unit constructs a handshake channel for the signal source device and the signal receiving device, the signal source device which sends the EDID to the DP + + format and outputs the HDMI format video signal through the main control unit, the HDMI format video signal is directly output to the signal receiving device, video signal transmission can be carried out among various devices supporting DP + +, the compatibility is high, and the application range is wide.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of electronic circuits, in particular to a DP-to-HDMI processing device. BACKGROUND

[0002] When transmitting a video signal between different devices, the signal type and signal synchronization need to be considered to ensure that the video signal output by the output end can be reproduced synchronously and completely at the receiving end, so that video playback can be realized. The existing video signal conversion device usually adopts a dedicated signal conversion chip. The signal conversion chip has input / output ports and can convert the received video signal into different data formats based on the program burned in the chip.

[0003] Although the signal conversion device using the dedicated signal conversion chip is simple to develop and design, the cost of the chip itself is relatively high. Taking the DP-to-HDMI signal as an example, the dedicated signal conversion chip converts the clock data and serial data carrying the video content together. If the transmission protocol between the receiving device and the output device is not set in advance, the lack of synchronization signal will cause compatibility problems, and the scope of application is relatively narrow. SUMMARY

[0004] The application discloses a DP-to-HDMI processing device, which specifically comprises the following contents.

[0005] The main control unit, the first interface unit, the second interface unit, the level conversion unit and the voltage boosting unit are electrically connected.

[0006] The main control unit is electrically connected to the first interface unit and the second interface unit to build a communication connection between the signal source device and the signal receiving device to transmit the video signal.

[0007] The main control unit is electrically connected to the level conversion unit to output the level format corresponding to the signal receiving device.

[0008] The voltage boosting unit is used to provide a rated voltage to the signal receiving device.

[0009] Preferably, the first interface unit adopts a terminal J1 which is electrically connected to the signal source device to receive the DP++ format video signal.

[0010] The 15th pin of the terminal J1 is used to transmit the clock data contained in the video signal, the 17th pin is used to transmit the serial data contained in the video signal, and the 20th pin is used for power supply.

[0011] Preferably, the main control unit adopts a main control chip U2 of model MS80F or model FT61EC, the first pin of which is connected with the 17th pin of terminal J1 to obtain serial data, and the 6th pin of which is connected with the 15th pin of terminal J1 to obtain clock data.

[0012] Preferably, the level conversion unit comprises MOS tubes G1 and G2.

[0013] The source of MOS tube G1 is connected with the first pin of main control chip U2, the source of MOS tube G2 is connected with the 6th pin of main control chip U2, and the gate of MOS tube G1 is connected with the drain of MOS tube G2.

[0014] Preferably, the second interface unit adopts terminal J2, which is electrically connected with the signal receiving device to transmit EDID signal to the signal receiving device.

[0015] The 15th pin of terminal J2 is connected with the drain of MOS tube G2 to obtain serial data after format conversion.

[0016] The 16th pin of terminal J2 is connected with the drain of MOS tube D to obtain clock data after format conversion.

[0017] Preferably, the voltage boosting unit adopts voltage boosting chip U1, the 5th pin of which is connected with the 20th pin of terminal J1 to obtain voltage with voltage value of +3.3V and boost to obtain voltage with voltage value of +5V.

[0018] The first pin of which is connected with the 18th pin of terminal J2 to output voltage with voltage value of +5V to the signal receiving device.

[0019] Preferably, the 4th pin of main control chip U2 is used to perform hot plug detection, and the 3rd pin is used to control the signal source device to output video signal when the hot plug detection is triggered.

[0020] Preferably, the signal source device and the signal receiving device communicate based on I2C protocol.

[0021] Compared with the prior art, the embodiment of the present application has the following beneficial effects:

[0022] The main control unit constructs handshake channel for the signal source device and the signal receiving device, and the main control sends EDID to the signal source device of DP++ format to output HDMI format video signal, which is directly output to the signal receiving device, so that the video signal transmission can be performed between various devices supporting DP++, and the compatibility is strong and the application range is wide. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to make the technical solutions in the embodiments of the present application clearer, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings described in the following are only some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0024] Fig. 1 is a circuit principle schematic diagram of a master unit in a DP-to-HDMI processing device disclosed by the embodiments of the present application;

[0025] Fig. 2 is a circuit principle schematic diagram of a first interface unit in a DP-to-HDMI processing device disclosed by the embodiments of the present application;

[0026] Fig. 3 is a circuit principle schematic diagram of a second interface unit in a DP-to-HDMI processing device disclosed by the embodiments of the present application;

[0027] Fig. 4 is a circuit principle schematic diagram of a level conversion unit in a DP-to-HDMI processing device disclosed by the embodiments of the present application;

[0028] Fig. 5 is a circuit principle schematic diagram of a voltage boosting unit in a DP-to-HDMI processing device disclosed by the embodiments of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort belong to the scope of protection of the present application.

[0030] Please refer to Figs. 1-5 The DP-to-HDMI processing device can include the following contents.

[0031] The master unit, the first interface unit, the second interface unit, the level conversion unit and the voltage boosting unit;

[0032] The master unit is electrically connected with the first interface unit and the second interface unit, and is used to build a communication connection between a signal source device and a signal receiving device to transmit a video signal;

[0033] The master unit is electrically connected with the level conversion unit to output a level format corresponding to the signal receiving device;

[0034] The voltage boosting unit is used to provide a rated voltage to the signal receiving device.

[0035] Here, the main control unit constructs a direct communication connection between the signal source device and the signal receiving device, forms a handshake channel, detects the signal format of the signal receiving device and feeds back to the signal source device, and the signal source device outputs a video signal adapted to the signal receiving device accordingly.

[0036] Further, the level conversion unit respectively converts the serial data carrying the video content and the clock data for realizing synchronization in the video signal, and outputs through independent ports, avoiding compatibility problems caused by protocol missing, etc.

[0037] As an optional implementation, the first interface unit adopts terminal J1, which is electrically connected to the signal source device to receive a video signal in DP++ format.

[0038] The 15th pin of terminal J1 is used to transmit clock data contained in the video signal, the 17th pin is used to transmit serial data contained in the video signal, and the 20th pin is used for power supply.

[0039] As an optional implementation, the main control unit adopts a main control chip U2 of model MS80F or model FT61EC, the 1st pin of which is connected to the 17th pin of terminal J1 to obtain serial data, and the 6th pin of which is connected to the 15th pin of terminal J1 to obtain clock data.

[0040] As an optional implementation, the level conversion unit includes MOS tube G1 and MOS tube G2.

[0041] The source of MOS tube G1 is connected to the 1st pin of main control chip U2, the source of MOS tube G2 is connected to the 6th pin of main control chip U2, and the gate of MOS tube G1 is connected to the drain of MOS tube G2.

[0042] As an optional implementation, the second interface unit adopts terminal J2, which is electrically connected to the signal receiving device to transmit a video signal in HDMI format to the signal receiving device.

[0043] The 15th pin of terminal J2 is connected to the drain of MOS tube G2 to obtain serial data after format conversion.

[0044] The 16th pin of terminal J2 is connected to the drain of MOS tube G1 to obtain clock data after format conversion.

[0045] Here, the serial data carrying the video content and the clock data for realizing synchronization are respectively converted independently, effectively ensuring that the clock data does not be confused with other data and compatibility problems do not occur, and can be applied to various devices for video signal transmission.

[0046] As an optional implementation, the voltage boosting unit adopts a voltage boosting chip U1, the 5th pin of which is connected with the 20th pin of the terminal J1, so as to obtain a current with a voltage value of +3.3V and boost the voltage to obtain a current with a voltage value of +5V.

[0047] The 1st pin of the voltage boosting chip U1 is connected with the 18th pin of the terminal J2, so as to output a current with a voltage value of +5V to the signal receiving device.

[0048] Here, different devices have different requirements for the electrical parameters of the video signal, and by performing independent voltage conversion, the transmission distance of the video signal between the two devices is ensured to meet the requirements and can be accurately recognized by the signal receiving device.

[0049] As an optional implementation, the 4th pin of the main control chip U2 is used to perform hot plug detection, and the 3rd pin is used to control the signal source device to output the video signal when the hot plug detection is triggered.

[0050] As an optional implementation, the signal source device and the signal receiving device communicate based on the I2C protocol.

[0051] Here, the main control chip detects whether the terminal J1 and the terminal J2 have been plugged in, and builds a handshake channel when it is detected that the hot plug is completed.

[0052] Compared with the prior art, the embodiment of the application has the following beneficial effects:

[0053] The main control unit builds a handshake channel for the signal source device and the signal receiving device, and the main control sends EDID to the signal source device in the DP++ format to output the video signal in the HDMI format, which is directly output to the signal receiving device, so that the video signal can be transmitted between various devices supporting DP++, the compatibility is strong, and the application range is wide.

Claims

1. A DP-to-HDMI processing device, comprising: The application relates to a signal transmission device, which comprises a main control unit, a first interface unit, a second interface unit, a level conversion unit and a voltage boosting unit. The main control unit is electrically connected with the first interface unit and the second interface unit, and is used for establishing a communication connection between a signal source device and a signal receiving device to transmit a video signal. The main control unit is electrically connected with the level conversion unit to output a level format corresponding to the signal receiving device. The voltage boosting unit is used for providing a rated voltage to the signal receiving device. The first interface unit adopts a terminal J1 which is electrically connected with the signal source device to receive a video signal in a DP++ format.

2. The DP-to-HDMI processing device of claim 1, wherein, A 15th pin of the terminal J1 is used for transmitting clock data contained in the video signal, a 17th pin is used for transmitting serial data contained in the video signal, and a 20th pin is used for power supply. The main control unit adopts a main control chip U2 with a model number of MS80F or a model number of FT61EC, a 1st pin of which is connected with a 17th pin of the terminal J1 to obtain serial data, and a 6th pin of which is connected with a 15th pin of the terminal J1 to obtain clock data. The level conversion unit comprises MOS tubes G1 and G2.

3. The DP-to-HDMI processing device of claim 2, wherein, A source of the MOS tube G1 is connected with a 1st pin of the main control chip U2, a source of the MOS tube G2 is connected with a 6th pin of the main control chip U2, and a gate of the MOS tube G1 is connected with a drain of the MOS tube G2. The second interface unit adopts a terminal J2 which is electrically connected with the signal receiving device to transmit an EDID signal to the signal receiving device.

4. The DP-to-HDMI processing device of claim 3, wherein, A 15th pin of the terminal J2 is connected with a drain of the MOS tube G2 to obtain serial data after format conversion. A 16th pin of the terminal J2 is connected with a drain of the MOS tube D to obtain clock data after format conversion. The voltage boosting unit adopts a voltage boosting chip U1, a 5th pin of which is connected with a 20th pin of the terminal J1 to obtain a voltage with a voltage value of +3.3V and to boost the voltage to obtain a voltage with a voltage value of +5V.

5. The DP-to-HDMI processing device of claim 4, wherein, A 1st pin of the voltage boosting chip U1 is connected with a 18th pin of the terminal J2 to output the voltage with the voltage value of +5V to the signal receiving device. A 4th pin of the main control chip U2 is used for performing hot plug detection, and a 3rd pin is used for controlling the signal source device to output the video signal when the hot plug detection is triggered. The signal source device and the signal receiving device communicate based on an I2C protocol. ​ 6. The DP-to-HDMI processing device of claim 5, wherein, ​ ​ ​ 7. The DP-to-HDMI processing device of claim 3, wherein, ​ ​ 8. The DP-to-HDMI processing device of claim 7, wherein, ​ ​

Images