Phase-sensitive detection circuit

Abstract

The utility model relates to a phase-sensitive detection circuit. The phase-sensitive detection circuit comprises a primary amplifier A1, an inverting amplifier A2, a first analog switch A7A and a second analog switch A7D, the normal phase input end of the first-stage amplifier A1 is suitable for being connected with a square wave signal. The inverted input end of the first-stage amplifier A1 is electrically connected with the output end of the first-stage amplifier A1; the output end of the primary amplifier A1 is electrically connected with the input end of a first analog switch A7A, and the output end of the first analog switch A7A is electrically connected with one end of a resistor R14; when the first analog switch A7A is switched on, the output end of the first analog switch A7A outputs a positive pulse signal; the output end of the primary amplifier A1 is electrically connected with the inverting input end of the inverting amplifier A2, the non-inverting input end of the inverting amplifier A2 is grounded, the output end of the inverting amplifier A2 is electrically connected with the input end of the second analog switch A7D, and the input end of the second analog switch A7D is electrically connected with the resistor R17; when the second analog switch A7D is turned on, the output end of the second analog switch A7D outputs a positive pulse signal.

Description

Technical Field

[0001] This application relates to the field of eight-sided logging technology, and in particular to a phase-sensitive detector circuit. Background Technology

[0002] Phase-sensitive detection is used in eight-sided logging equipment to convert AC signals into DC signals and send them to subsequent circuits. Common phase-sensitive detection techniques often use diodes for unidirectional conduction, i.e., the current is cut off or allowed to flow by turning the diode on or off. However, when the diode is in the forward conduction state, the electrical signal flowing through the diode will experience a voltage drop, resulting in voltage loss. This application proposes a phase-sensitive detection circuit suitable for implementing the detection process and avoiding voltage loss. Summary of the Invention

[0003] In view of this, this application proposes a phase-sensitive detector circuit.

[0004] According to one aspect of this application, a phase-sensitive detection circuit is provided, comprising: a first-stage amplifier A1, an inverting amplifier A2, a first analog switch A7A, and a second analog switch A7D;

[0005] The non-inverting input of the first-stage amplifier A1 is suitable for receiving square wave signals; the inverting input of the first-stage amplifier A1 is electrically connected to the output of the first-stage amplifier A1.

[0006] The output terminal of the first-stage amplifier A1 is electrically connected to the input terminal of the first analog switch A7A, and the output terminal of the first analog switch A7A is electrically connected to one end of the resistor R14; this is suitable for outputting a positive pulse signal at the output terminal of the first analog switch A7A when the first analog switch A7A is turned on.

[0007] The output terminal of the first-stage amplifier A1 is electrically connected to the inverting input terminal of the inverting amplifier A2. The non-inverting input terminal of the inverting amplifier A2 is grounded. The output terminal of the inverting amplifier A2 is electrically connected to the input terminal of the second analog switch A7D. The input terminal of the second analog switch A7D is electrically connected to the resistor R17. This is suitable for outputting a positive pulse signal at the output terminal of the second analog switch A7D when the second analog switch A7D is turned on.

[0008] In one possible implementation, it also includes: resistor R4; the non-inverting input of the first-stage amplifier A1 is connected to a square wave signal through resistor R4.

[0009] In one possible implementation, it also includes: capacitor C9; the output terminal of the first-stage amplifier A1 is electrically connected to the input terminal of the first analog switch A7A through capacitor C9.

[0010] In one possible implementation, resistor R9 is also included;

[0011] The output of the first-stage amplifier A1 is electrically connected to the inverting input of the inverting amplifier A2 via capacitor C9 and resistor R9 in sequence.

[0012] In one possible implementation, it also includes: resistor R20;

[0013] Resistor R14 is electrically connected to resistor R20; resistor R17 is electrically connected to resistor R20.

[0014] In one possible implementation, both the primary amplifier A1 and the inverting amplifier A2 are model UA709HM.

[0015] In one possible implementation, pin 8 of the first-stage amplifier A1 is electrically connected to pin 1 of the first-stage amplifier A1 through capacitor C4 and resistor R7.

[0016] In one possible implementation, pin 8 of the inverting amplifier A2 is electrically connected to pin 1 of the inverting amplifier A2 via capacitor C7 and resistor R13.

[0017] In one possible implementation, both the first analog switch A7A and the second analog switch A7D are of model number ADG412.

[0018] Beneficial effects: Since the signal detection process of this application is achieved by turning on and off an analog switch, the voltage across the analog switch does not change after the analog switch is closed, unlike the unidirectional conduction detection of a diode. Therefore, the voltage loss caused by the forward voltage drop of a diode is avoided. At the same time, this application has high signal amplitude detection accuracy, simple circuit, and can operate at temperatures below 125°C.

[0019] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0020] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0021] Figure 1 A circuit diagram of a phase-sensitive detector circuit according to an embodiment of this application is shown;

[0022] Figure 2 This diagram illustrates the detection process of a phase-sensitive detection circuit according to an embodiment of this application. Detailed Implementation

[0023] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0024] It should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model or simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0026] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0027] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0028] Figure 1 A circuit diagram of a phase-sensitive detector circuit according to an embodiment of this application is shown. Figure 1As shown, a phase-sensitive detector circuit includes: a primary amplifier A1, an inverting amplifier A2, a first analog switch A7A, and a second analog switch A7D; the non-inverting input of the primary amplifier A1 is suitable for receiving a square wave signal; the inverting input of the primary amplifier A1 is electrically connected to the output of the primary amplifier A1; the output of the primary amplifier A1 is electrically connected to the input of the first analog switch A7A, and the output of the first analog switch A7A is electrically connected to one end of a resistor R14; the circuit is suitable for outputting a positive pulse signal when the first analog switch A7A is turned on; the output of the primary amplifier A1 is electrically connected to the inverting input of the inverting amplifier A2, the non-inverting input of the inverting amplifier A2 is grounded, the output of the inverting amplifier A2 is electrically connected to the input of the second analog switch A7D, and the input of the second analog switch A7D is electrically connected to a resistor R17; the circuit is suitable for outputting a positive pulse signal when the second analog switch A7D is turned on.

[0029] It should be noted here that the primary amplifier A1 is suitable for amplifying the input square wave signal by a multiple factor (the specific amplification factor depends on the final output voltage requirement). When APsin is the input square wave signal, the primary amplifier A1 outputs a square wave signal amplified by a multiple factor, and the inverting amplifier A2 outputs a square wave signal amplified by a multiple factor and then inverted. For example, if the amplification factor of the primary amplifier A1 is 21 times, when APsin is the input square wave signal, the primary amplifier A1 outputs a square wave signal amplified by 21 times, and the inverting amplifier A2 outputs a square wave signal amplified by 21 times and then inverted. It should be noted that since the inverting amplifier is a 1x inverting amplifier, the phase of the signal waveform output by the primary amplifier A1 is opposite to the phase of the signal waveform output by the inverting amplifier A2, but the amplitude is the same (e.g., ...). Figure 2 (As described above). When the square wave signal output by the primary amplifier A1 is in the positive half-cycle, the first analog switch A7A is saturated and turned on, and the output terminal of the primary amplifier A1 outputs a positive pulse signal through the first analog switch A7A; when the square wave signal output by the primary amplifier A1 is in the negative half-cycle, the first analog switch A7A...

[0030] When the circuit is off, the output of the first-stage amplifier A1 cannot output a pulse signal. When the square wave signal output by the inverting amplifier A2 is in the positive half-cycle, the second analog switch A7D is saturated and conducting, and the output of the inverting amplifier A2 outputs a positive pulse signal through the second analog switch A7D. When the square wave signal output by the inverting amplifier A2 is in the negative half-cycle, the second analog switch A7D is off, and the output of the inverting amplifier A2 cannot output a pulse signal through the second analog switch A7D. In this way, through the alternating action of the continuous closing and closing of the first analog switch A7A and the second analog switch A7D, the square wave signal can be detected, so that the circuit outputs a stable DC positive voltage.

[0031] Since the signal detection process in this application is achieved through the on and off states of an analog switch, the voltage across the analog switch remains unchanged after the switch is closed. This differs from the single-phase conduction detection method of a diode, thus avoiding voltage loss caused by the forward voltage drop of a diode. Furthermore, this application boasts high signal amplitude detection accuracy (the electronic switch is controlled to be turned on and off, resulting in very low on-resistance and a very low signal voltage drop); its circuitry is also simple (an operational amplifier generates an inverse phase signal, making the circuit relatively simple); and it can operate at temperatures below 125°C (both the amplifier circuit and the electronic switch operate within a temperature range of 125°C).

[0032] In one possible implementation, the first-stage amplifier A1 is model UA709HM. A square wave signal is connected to the non-inverting input (pin 3) of the first-stage amplifier A1; the inverting input (pin 2) is electrically connected to the output (pin 6) of the first-stage amplifier A1 via resistor R6 (resistor R6 is the feedback resistor of the first-stage amplifier A1, and capacitor C3 is the phase compensation capacitor to prevent operational amplifier self-oscillation). Pin 5 of the first-stage amplifier A1 is electrically connected to the output (pin 6) of the first-stage amplifier A1 via capacitor C3; the power input (pin 4) of the first-stage amplifier A1 is connected to a -15V operating voltage via resistor R3; the power input (pin 7) of the first-stage amplifier A1 is connected to a +15V operating voltage via resistor R2; and pin 8 of the first-stage amplifier A1 is electrically connected to pin 1 of the first-stage amplifier A1 via capacitor C4 and resistor R7.

[0033] In one possible implementation, it also includes: resistor R5; one end of resistor R5 is electrically connected to the inverting input terminal (pin 2) of the first-stage amplifier A1, and the other end of resistor R5 is grounded.

[0034] In one possible implementation, capacitor C1 is also included; one terminal of capacitor C1 is electrically connected to resistor R3, and the other terminal of capacitor C1 is grounded. Capacitor C1 is suitable for filtering the power supply voltage.

[0035] In one possible implementation, it also includes: capacitor C2; one terminal of capacitor C2 is electrically connected to the circuit where pin 7 of the first-stage amplifier A1 is connected to resistor R2, and the other terminal of capacitor C2 is grounded.

[0036] In one possible implementation, it also includes: resistor R4; the non-inverting input terminal of the first-stage amplifier A1 is connected to a square wave signal through resistor R4. One end of resistor R4 is connected to the square wave signal, and the other end of resistor R4 is electrically connected to the non-inverting input terminal (pin 3) of the first-stage amplifier A1.

[0037] In one possible implementation, it also includes: resistor R1; one end of resistor R1 is electrically connected to the circuit where resistor R4 is connected to the square wave signal, and the other end of resistor R1 is grounded.

[0038] In one possible implementation, it also includes: capacitor C9; the output terminal of the first-stage amplifier A1 is electrically connected to the input terminal (pin 2) of the first analog switch A7A through capacitor C9. Further, one stage of capacitor C9 is electrically connected to the output terminal (pin 6) of the first-stage amplifier A1; the other stage of capacitor C9 is electrically connected to the input terminal of the first analog switch A7A and the inverting input terminal of the inverting amplifier A2.

[0039] In one possible implementation, it also includes: resistor R9; capacitor C9 is electrically connected to resistor R9, and the output terminal of the first-stage amplifier A1 is electrically connected to the inverting input terminal of the inverting amplifier A2 in sequence through capacitor C9 and resistor R9.

[0040] In one possible implementation, the first analog switch A7A is model ADG412. Pin 1 of the first analog switch A7A is used to input a TTL level signal. The input terminal (pin 2) of the first analog switch A7A is electrically connected to the output terminal (pin 6) of the first stage amplifier A1 through capacitor C9. The output terminal (pin 3) of the first analog switch A7A is electrically connected to resistor R14 to output an electrical signal through resistor R14. The power input terminal (pin 4) of the first analog switch A7A is connected to a -15V operating voltage; the power input terminal (pin 13) of the first analog switch A7A is connected to a +15V operating voltage; pin 12 of the first analog switch A7A is connected to a +5V voltage through resistor R8; pin 5 of the first analog switch A7A is grounded; when a high-level signal is input to pin 1 of the first analog switch A7A, the input terminal (pin 2) and the output terminal (pin 3) of the first analog switch A7A are saturated and conducting, and current can flow through the first analog switch A7A; when pin 1 of the first analog switch A7A is 0V, the input terminal (pin 2) and the output terminal (pin 3) of the first analog switch A7A are cut off, and current cannot flow through the first analog switch A7A.

[0041] In one possible implementation, it also includes: a Zener diode D1; the positive terminal of the Zener diode D1 is grounded, and the negative terminal of the Zener diode D1 is electrically connected to the resistor R8.

[0042] In one possible implementation, the inverting amplifier A2 is model UA709HM. The non-inverting input terminal (pin 3) of the inverting amplifier A2 is grounded through resistor R10; the inverting input terminal (pin 2) of the inverting amplifier A2 is electrically connected to the output terminal (pin 6) of the first-stage amplifier A1 through resistor R9; and the inverting input terminal (pin 2) of the inverting amplifier A2 is electrically connected to the output terminal (pin 6) of the inverting amplifier A2 through resistor R12; pin 5 of the inverting amplifier A2 is electrically connected to the output terminal (pin 6) of the inverting amplifier A2 through capacitor C6; the power input terminal (pin 4) of the inverting amplifier A2 is connected to a -15V operating voltage through resistor R911; the power input terminal (pin 7) of the inverting amplifier A2 is connected to a +15V operating voltage through resistor R15; pin 8 of the inverting amplifier A2 is electrically connected to pin 1 of the inverting amplifier A2 through capacitor C7 and resistor R13; the output terminal (pin 6) of the inverting amplifier A2 is electrically connected to the input terminal (pin 7) of the second analog switch A7D.

[0043] In one possible implementation, it also includes: capacitor C5; one terminal of capacitor C5 is electrically connected to the circuit where pin 7 of inverting amplifier A2 is connected to resistor R15, and the other terminal of capacitor C5 is grounded.

[0044] In one possible implementation, it also includes: capacitor C8; one terminal of capacitor C8 is electrically connected to the circuit where pin 4 of inverting amplifier A2 is connected to resistor R911, and the other terminal of capacitor C8 is grounded.

[0045] In one possible implementation, the second analog switch A7D is model ADG412. Pin 8 of the second analog switch A7D is used to input a TTL level signal. The input terminal (pin 7) of the second analog switch A7D is electrically connected to the output terminal (pin 6) of the inverting amplifier A2, and the output terminal (pin 6) of the second analog switch A7D is electrically connected to resistor R17 to output an electrical signal through resistor R17. The other pins of the second analog switch A7D have the same electrical connection relationship as the other open pins of the first analog switch A7A. When a high-level signal is input to pin 8 of the second analog switch A7D, the input terminal (pin 7) and the output terminal (pin 6) of the second analog switch A7D are saturated and conducting, and current can flow through the second analog switch A7D; when pin 8 of the second analog switch A7D is 0V, the input terminal (pin 7) and the output terminal (pin 6) of the second analog switch A7D are cut off, and current cannot flow through the second analog switch A7D.

[0046] In one possible implementation, it also includes: resistor R20; the output terminal of resistor R14 is electrically connected to resistor R20; the output terminal of resistor R17 is electrically connected to resistor R20, and resistor R20 is suitable for outputting the detected DC voltage.

[0047] In one possible implementation, it also includes: capacitor C12; one terminal of capacitor C12 is electrically connected to resistor R20, and the other terminal of capacitor C12 is grounded.

[0048] like Figure 2 As shown, the square wave signal output from the output terminal (pin 6) of the primary amplifier A1 is out of phase but has the same amplitude as the square wave signal output from the output terminal (pin 6) of the inverting amplifier A2. When the square wave signal output from the output terminal (pin 6) of the primary amplifier A1 is a positive voltage, the first analog switch A7A is closed and conducting. At this time, the square wave signal output from the output terminal (pin 6) of the inverting amplifier A2 is a negative voltage, and the second analog switch A7D is off. Therefore, the first analog switch A7A has a positive current output to resistor R20, and the second analog switch A7D has no current output. When the primary amplifier A1... When the square wave signal output from the output terminal (pin 6) is a negative voltage, the first analog switch A7A is cut off. At this time, the square wave signal output from the output terminal (pin 6) of the inverting amplifier A2 is a positive voltage, and the second analog switch A7D is closed and turned on. Therefore, the second analog switch A7D has a positive current output to resistor R20, and the first analog switch A7A has no current output. Finally, under the alternating action of the first analog switch A7A and the second analog switch A7D, the output terminal of resistor R20 will output a DC positive voltage. Under the filtering effect of capacitor C12, a stable DC positive voltage will be obtained.

[0049] The phase-sensitive detection circuit of this application can be applied in the main electrode output amplifier circuit, barrier output amplifier circuit, and lateral amplifier circuit of an eight-sided logging equipment; it is used to detect AC signals into DC signals for subsequent circuits; it should be noted that the high-level signal input to pin 1 of the first analog switch A7A and the high-level signal input to pin 8 of the second analog switch A7D are both TTL level signals taken from the detection electrode of the front-end circuit.

[0050] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A phase-sensitive detection circuit, characterized in that, include: A primary amplifier A1, an inverting amplifier A2, a first analog switch A7A, and a second analog switch A7D; The non-inverting input terminal of the first-stage amplifier A1 is suitable for receiving square wave signals; the inverting input terminal of the first-stage amplifier A1 is electrically connected to the output terminal of the first-stage amplifier A1. The output terminal of the first-stage amplifier A1 is electrically connected to the input terminal of the first analog switch A7A, and the output terminal of the first analog switch A7A is electrically connected to one end of the resistor R14. When the first analog switch A7A is turned on, the output terminal of the first analog switch A7A outputs a positive pulse signal. The output terminal of the first-stage amplifier A1 is electrically connected to the inverting input terminal of the inverting amplifier A2. The non-inverting input terminal of the inverting amplifier A2 is grounded. The output terminal of the inverting amplifier A2 is electrically connected to the input terminal of the second analog switch A7D. The input terminal of the second analog switch A7D is electrically connected to the resistor R17. This configuration is suitable for outputting a positive pulse signal when the second analog switch A7D is turned on.

2. The phase-sensitive detection circuit according to claim 1, characterized in that, Also includes: Resistor R4; The non-inverting input terminal of the first-stage amplifier A1 is connected to the square wave signal through the resistor R4.

3. The phase-sensitive detector circuit according to claim 1, characterized in that, Also includes: Capacitor C9; The output terminal of the first-stage amplifier A1 is electrically connected to the input terminal of the first analog switch A7A through the capacitor C9.

4. The phase-sensitive detection circuit according to claim 3, characterized in that, Also includes: Resistor R9; The output terminal of the first-stage amplifier A1 is electrically connected to the inverting input terminal of the inverting amplifier A2 via the capacitor C9 and the resistor R9 in sequence.

5. A phase-sensitive detection circuit according to claim 1, characterized in that, It also includes: resistor R20; The resistor R14 is electrically connected to the resistor R20; the resistor R17 is electrically connected to the resistor R20.

6. The phase-sensitive detection circuit according to claim 1, characterized in that, The primary amplifier A1 and the inverting amplifier A2 are both model UA709HM.

7. A phase-sensitive detection circuit according to claim 1, characterized in that, Pin 8 of the first-stage amplifier A1 is electrically connected to pin 1 of the first-stage amplifier A1 through capacitor C4 and resistor R7.

8. A phase-sensitive detection circuit according to claim 1, characterized in that, Pin 8 of the inverting amplifier A2 is electrically connected to pin 1 of the inverting amplifier A2 via capacitor C7 and resistor R13.

9. A phase-sensitive detection circuit according to claim 1, characterized in that, The first analog switch A7A and the second analog switch A7D are both model ADG412.

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