Lead frame and packaging structure
By using a multi-island design and packaging structure of the lead frame, the problems of large packaging structure size and high cost are solved, achieving miniaturization and cost reduction of the packaging structure, which is suitable for highly integrated semiconductor packaging.
Patent Information
- Application Number
- CN202422853223.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-11-11
- Estimated Expiration
- 2034-11-21
AI Technical Summary
Existing semiconductor packaging structures are large in size and expensive, making it difficult to meet the requirements for high integration and miniaturization.
The lead frame employs a multi-base-island structure, which shortens the lead connection length by setting base islands for semiconductor chips and switching elements. Combined with plastic encapsulation, it forms a package structure. The use of independent base islands and pin designs reduces package size and lowers costs.
It achieves miniaturization and cost reduction of the packaging structure, making it suitable for high-integration semiconductor packaging needs.
Smart Images
Figure CN223539597U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, and in particular to a lead frame and packaging structure. Background Technology
[0002] In the field of semiconductor packaging, with the development of technology, the requirements for packaging in semiconductor product applications are becoming increasingly stringent. For example, a package needs to integrate more chips to achieve high integration, reduce package size, and shorten chip interconnect distances to improve chip processing speed. For instance, the IPM (Intelligent Power Module), commonly found in the market, typically includes one or more switching devices such as power MOSFETs, IGBTs (Insulated Gate Bipolar Transistors), or SiC (Silicon Carbide), and a driver circuit controls the on / off state of these switching devices.
[0003] However, such IPM modules are usually plug-in chips or QFN (Quad Flat No-lead Package) chips. Plug-in chips are relatively large, which is not conducive to the miniaturization design of IPM modules; while QFN chips are expensive.
[0004] Based on the above description, the existing packaging structure is relatively large, and if the QFN chip packaging method is used, the cost of the packaging structure will be high.
[0005] Therefore, it is necessary to provide improved technical solutions to overcome the above-mentioned technical problems existing in the prior art. Utility Model Content
[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide a lead frame and packaging structure that reduces the volume of the packaging structure and has a lower cost.
[0007] To achieve the above objectives, this application adopts the following technical solution:
[0008] In a first aspect, this application provides a lead frame, which includes multiple base islands and multiple pins. Adjacent base islands are electrically isolated from each other. Some base islands are used to carry semiconductor chips, and other base islands are used to carry switching elements. Multiple pins are arranged around the multiple base islands and are connected to the semiconductor chip and / or switching elements through several leads. The multiple base islands include a first base island on which the semiconductor chip is disposed and multiple second base islands on which the switching elements are disposed, with the first base island located between the multiple second base islands.
[0009] Furthermore, among the multiple pins, the pin with a first width is defined as the first pin, and the pin with a second width is defined as the second pin. The first pin is directly connected to the first base island and the second base island, and the second pin is connected to the semiconductor chip and the switching element through several leads. The first width is greater than the second width.
[0010] Furthermore, the first width ranges from 0.36 mm to 1.55 mm.
[0011] Furthermore, the first pins are arranged on both sides of the multiple base islands; wherein, a portion of the first pins connected to the first base islands are arranged on one side of the lead frame, and another portion of the first pins connected to the second base islands are arranged on the other side of the lead frame.
[0012] Furthermore, the center-to-center spacing between any two adjacent pins in the plurality of pins ranges from 1.43 mm to 2.96 mm.
[0013] Secondly, this application also provides a packaging structure, which includes a lead frame according to any of the first aspects described above, as well as a semiconductor chip, a switching element, a plurality of leads, and a molding compound. The semiconductor chip is disposed on a corresponding base island among a plurality of base islands, and the plurality of leads connect a plurality of pins to the semiconductor chip. The molding compound covers the lead frame, the plurality of base islands, the plurality of pins, the semiconductor chip, the switching element, and the plurality of leads. The switching element is connected to the plurality of pins and / or the semiconductor chip through the plurality of leads. The plurality of base islands include a first base island disposed of the semiconductor chip and a plurality of second base islands disposed of the switching element, with the first base island located between the plurality of second base islands.
[0014] Furthermore, the switching element has a control terminal connected to the semiconductor chip via a portion of a plurality of leads, the control terminal being located on the side of the switching element closer to the semiconductor chip.
[0015] Furthermore, the package structure also includes a metal layer covering the lead frame; the semiconductor chip disposed on the first base island is electrically connected to a plurality of pins through the metal layer; and / or, the switching element disposed on the second base island is electrically connected to a plurality of pins through the metal layer; and / or, the semiconductor chip disposed on the first base island is electrically connected to the switching element disposed on the second base island through the metal layer.
[0016] Furthermore, the number of switching elements is set to multiple, and the multiple base islands include second base islands with the same number of switching elements. Each second base island is equipped with a switching element, and the multiple second base islands are arranged around the first base island.
[0017] Furthermore, the packaging structure is an SOP (Surface Mount Technology) packaging structure.
[0018] The lead frame provided in this application sets up multiple base islands, with the base island containing the semiconductor chip as the first base island and the base island containing the switching element as the second base island. When there are at least two second base islands, the first base island is placed between at least two second base islands. Based on the above lead frame, the length of several leads connecting the semiconductor chip and the switching element can be shortened, resulting in a smaller package structure using this lead frame. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the packaging structure in an embodiment of this application;
[0020] Figure 2 This is a schematic diagram of the first cross-sectional structure of the encapsulation structure in an embodiment of this application;
[0021] Figure 3 This is a second cross-sectional view of the encapsulation structure in an embodiment of this application. Detailed Implementation
[0022] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.
[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0024] The present application will now be described in detail with reference to the accompanying drawings.
[0025] Figure 1 A schematic diagram of the packaging structure 100 provided according to an embodiment of this application is shown.
[0026] The packaging structure 100 disclosed in this application can be applied to SOP (Small Out-Line Package) packaging.
[0027] See Figure 2 and Figure 3 The package structure 100 includes a lead frame 11, a semiconductor chip 12, several leads, a plastic encapsulation body 13, and a switching element 14.
[0028] The lead frame 11 includes multiple base islands 111 and multiple pins 112. The multiple base islands 111 are located in the internal region of the lead frame 11, and adjacent base islands are electrically isolated from each other. Among them, a portion of the multiple base islands 111 are used to carry semiconductor chip 12, and another portion of the multiple base islands 111 are used to carry switching element 14.
[0029] Multiple pins 112 are arranged around multiple base islands 111, with any two adjacent pins 112 spaced apart from each other. In this embodiment, the multiple pins 112 are located in the lead frame 11 region surrounding the multiple base islands 111. The number of pins disposed on each side region of the lead frame 11 may be the same or different.
[0030] Optionally, each of the plurality of pins 112 is provided with a pin pad, and each pin is electrically connected to one of the plurality of base islands 112 via the pin pad (the lead is connected to the pin pad between the lead frame 11 by a bonding process); or each of the plurality of pins 112 is integrally formed with the corresponding base island.
[0031] In this embodiment, any two pins among the plurality of pins 112 are electrically isolated from each other (except for certain specific chip circuit connection structure requirements). That is, each of the plurality of base islands 111 is electrically isolated from any pin among the plurality of pins 112, or each of the plurality of base islands 111 is directly connected to one pin among the plurality of pins 112. This means that a base island will not be directly connected to two or more pins among the plurality of pins 112 simultaneously, preventing two or more pins among the plurality of pins 112 from being electrically connected through base islands, thereby isolating the signal connections between the plurality of pins 112.
[0032] Specifically, the center distance between any two adjacent pins in the plurality of pins 112 ranges from 1.43 mm to 2.96 mm.
[0033] Semiconductor chip 12 is disposed on a corresponding base island among multiple base islands 111. Multiple leads connect multiple pins 112 to semiconductor chip 12. Switching element 14 is connected to multiple pins 112 and / or semiconductor chip 12 through multiple leads, wherein multiple leads are all metal wires.
[0034] The molding compound 13 encapsulates the lead frame 11, multiple base islands 111, multiple pins 112, semiconductor chip 12, switching element 14, and several leads to form an independent package structure 100. In this embodiment, the molding compound 13 is made of a material with insulating properties and strong adhesion, such as epoxy resin. Furthermore, the sides of the multiple base islands 111 and multiple pins 112 relative to the molding compound 13 can be roughened to increase the adhesion between them and the molding compound 13, so that the final package structure 100 has good stability.
[0035] The plurality of base islands 111 includes a first base island 1111 on which a semiconductor chip 12 is disposed, and a plurality of second base islands 1112 on which a switching element 14 is disposed, wherein the first base island 1111 is located between the plurality of second base islands 1112. However, it is understood that the above description is merely exemplary, and the plurality of second base islands 1112 in the package structure 100 indicates that the number of second base islands 1112 is at least two. The design can be adjusted according to the specific number of switching elements 14 to be packaged, or according to the package size of the package structure 100, and this application does not impose any limitations on this.
[0036] like Figure 3 As shown in this embodiment, there are two second base islands 1112, and the number of switching elements 14 is the same as the number of second base islands 1112. The two switching elements 14 are defined as a first switching element 141 and a second switching element 142, respectively. The first switching element 141 is disposed on one second base island 1112, and the second switching element 142 is disposed on the other second base island 1112. The two second base islands 1112 are arranged on opposite sides of the first base island 1111. This arrangement ensures that the spacing between the semiconductor chip 12 and the first switching element 141 and the second switching element 142 is substantially consistent, and also avoids crossing during the connection of several leads.
[0037] In some embodiments, the number of switching elements 14 can be set to multiple, and the multiple base islands 111 include second base islands 1112 with the same number of switching elements 14. Each second base island 1112 is configured with a switching element 14, and the multiple second base islands 1112 are arranged around the first base island 1111.
[0038] For example, a bridge drive circuit is formed by combining multiple switching elements 14 (the bridge drive circuit includes a full-bridge drive circuit consisting of four switching elements 14 or a half-bridge drive circuit consisting of two switching elements 14). Each switching element 14 in the bridge drive circuit is disposed on a second base island 1112, and the semiconductor chip 12 is disposed between the multiple switching elements 14, thereby shortening the length of several leads from the semiconductor chip 12 to the multiple switching elements 14, and thus reducing the size of the package structure 100.
[0039] Optionally, multiple switching elements 14 can be combined to form a two-phase switching circuit (including 4 switching elements 14), a three-phase switching circuit (including 6 switching elements 14), a four-phase switching circuit (including 8 switching elements 14), etc., wherein each switching element 14 is disposed on a second base island 1112, and the semiconductor chip 12 is disposed between multiple switching elements 14, thereby shortening the length of several leads from the semiconductor chip 12 to the multiple switching elements 14, and thus reducing the size of the package structure 100.
[0040] It should be noted that this application does not specifically limit the number of switching elements 14. Different numbers of switching elements 14 configured with semiconductor chips 12 can be combined to form different power conversion modules. Any power conversion module that satisfies the above arrangement of switching elements 14 and semiconductor chips 12 is within the scope of protection claimed in this application.
[0041] In summary, by setting up multiple base islands 111 and setting up semiconductor chips 12 and multiple switching elements 14 on the corresponding base islands of the multiple base islands 111, and arranging the semiconductor chips 12 between the multiple switching elements 14, the size of the semiconductor package in the length and width directions can be effectively reduced.
[0042] Furthermore, the semiconductor chip 12 and the switching element 14 are disposed on the plurality of base islands 111 by means of an adhesive material such as an insulating adhesive.
[0043] like Figure 3 As shown, in some embodiments, a pin with a first width among the plurality of pins 112 is defined as a first pin 1121, and a pin with a second width is defined as a second pin 1122. As can be seen from the foregoing, the package structure 100 of this application embodiment has a plurality of independent base islands 111. The first pin 1121 is connected to a corresponding base island among the plurality of base islands 111, and the second pin 1122 is connected to the semiconductor chip 12 and the switching element 13 through a plurality of leads. The first width is greater than the second width.
[0044] For example, the first width ranges from 0.36 mm to 1.55 mm.
[0045] Since some of the base islands 111 are provided with semiconductor chips 12 and / or switching elements 14, the first pin 1121 is connected to the corresponding base island among the multiple base islands 111. By increasing the width of the first pin 1121, the heat dissipation efficiency of the semiconductor chip 12 and the switching element 14 can be improved.
[0046] In this embodiment of the application, the first pin 1121 is arranged on both sides of the lead frame 11, wherein a portion of the first pin 1121 connected to the first base island 1111 is arranged on one side of the lead frame 11, and another portion of the first pin 1121 connected to the second base island 1112 is arranged on the other side of the lead frame 11.
[0047] For example, the package structure 100 is specifically an SOP9 pin package. As described above, the package structure 100 has multiple independent base islands 111. The width of some of the nine pins in the package structure 100 ranges from 1.45 mm to 1.55 mm, and these pins are those connected to corresponding base islands among the multiple base islands 111. Apart from the aforementioned pins, the width of the remaining nine pins ranges from 0.38 mm to 0.46 mm.
[0048] As can be seen from the above, in order to reduce the size of the package structure 100, the semiconductor chip 12 is arranged between multiple switching elements 14 to reduce the length of the leads connecting the semiconductor chip 12 and the switching elements 14. Figure 3 As shown in the embodiment of this application, the switching element 14 has a control terminal that is electrically connected to the semiconductor chip 12 through a portion of a plurality of leads. The control terminal is located on the side of the switching element 14 close to the semiconductor chip 12, further shortening the length of the plurality of leads connecting the semiconductor chip 12 and the switching element 14.
[0049] In some embodiments, the package structure 100 further includes a metal layer 15 covering the lead frame 11, and the semiconductor chip 12 disposed on the first base island 1111 is electrically connected to the corresponding pins of the plurality of pins 112 through the metal layer 15.
[0050] Optionally, the switching element 14 disposed on the second base island 1112 is electrically connected to the corresponding pin among the plurality of pins 112 through the metal layer 15.
[0051] Optionally, the semiconductor chip 12 disposed on the first base island 1111 is electrically connected to the switching element 14 disposed on the second base island 1112 through the metal layer 15.
[0052] It should be noted that the semiconductor chip 12 and the metal layer 15, as well as the switching element 14 and the metal layer 15, are connected by several leads.
[0053] The metal layer 15 includes, but is not limited to, a silver plating layer, a copper plating layer, or a nickel-palladium-gold plating layer.
[0054] In summary, this application divides multiple base islands 111 into a first base island 1111 for setting up a semiconductor chip 12 and a second base island 1112 for setting up a switching element 14. When the number of switching elements 14 is at least two, the same number of second base islands 1112 are set up, and the first base island 1111 is set between at least two second base islands 1112, thereby shortening the length of several leads connecting the semiconductor chip 12 and the switching element 14, and thus reducing the size of the package structure 100.
[0055] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0056] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A lead frame, characterized in that, The lead frame includes: Multiple base islands, adjacent base islands are electrically isolated from each other, some base islands are used to carry semiconductor chips, and other base islands are used to carry switching elements; Multiple pins are arranged around the multiple base islands, and the multiple pins are connected to the semiconductor chip and / or the switching element via a number of leads; The plurality of base islands includes a first base island on which the semiconductor chip is disposed and a plurality of second base islands on which the switching element is disposed, wherein the first base island is located between the plurality of second base islands.
2. The lead frame according to claim 1, characterized in that, Among the plurality of pins, the pin with a first width is defined as the first pin, and the pin with a second width is defined as the second pin. The first pin is directly connected to the first base island and the second base island, and the second pin is connected to the semiconductor chip and the switching element through the plurality of leads. The first width is greater than the second width.
3. The lead frame according to claim 2, characterized in that, The first width ranges from 0.36 mm to 1.55 mm.
4. The lead frame according to claim 2, characterized in that, The first pin is arranged on both sides of the plurality of base islands, wherein a portion of the first pin connected to the first base island is arranged on one side of the lead frame, and another portion of the first pin connected to the second base island is arranged on the other side of the lead frame.
5. The lead frame according to claim 1, characterized in that, The center-to-center distance between any two adjacent pins in the plurality of pins ranges from 1.43 mm to 2.96 mm.
6. A packaging structure, characterized in that, The packaging structure includes a lead frame as described in any one of claims 1 to 5, a semiconductor chip, a switching element, a plurality of leads, and a molding compound. The semiconductor chip is disposed on a corresponding base island among the plurality of base islands, and the plurality of leads connect the plurality of pins to the semiconductor chip. The molding compound covers the lead frame, the plurality of base islands, the plurality of pins, the semiconductor chip, the switching element, and the plurality of leads. The switching element is connected to the plurality of pins and / or the semiconductor chip through the plurality of leads. The plurality of base islands includes a first base island on which the semiconductor chip is disposed and a plurality of second base islands on which the switching element is disposed, and the first base island is located between the plurality of second base islands.
7. The packaging structure according to claim 6, characterized in that, The switching element has a control terminal connected to the semiconductor chip via a portion of the plurality of leads, the control terminal being located on the side of the switching element closer to the semiconductor chip.
8. The packaging structure according to claim 6, characterized in that, The packaging structure further includes a metal layer covering the lead frame; the semiconductor chip disposed on the first base island is electrically connected to the plurality of pins through the metal layer; And / or, the switching element disposed on the second base island is electrically connected to the plurality of pins through the metal layer; And / or, the semiconductor chip disposed on the first base island is electrically connected to the switching element disposed on the second base island through the metal layer.
9. The packaging structure according to claim 6, characterized in that, The number of switching elements is set to multiple, and the multiple base islands include second base islands with the same number of switching elements. Each second base island is equipped with one switching element, and the multiple second base islands are arranged around the first base island.
10. The packaging structure according to claim 6, characterized in that, The packaging structure is an SOP (Surface Mount Technology) packaging structure.