DPAK packaging structure, electronic circuit and electronic equipment

Abstract

The utility model provides a DPAK packaging structure, an electronic circuit and an electronic device, the packaging structure comprises a lead frame, at least one first chip and a packaging body, the packaging body is used for packaging the lead frame and the first chip; the lead frame comprises a first pin, a plurality of second pins and a base island, and the distance between the first pin and the second pins, the distance between the base island and the first pin and the distance between the base island and the second pins are both larger than the first distance. Therefore, the DPAK packaging structure provided by the utility model can be used for packaging a high-voltage high-power chip. Wherein the first pin and the base island can be used for high-voltage output, so that the DPAK packaging structure can be used more flexibly, and the application scene of the DPAK packaging structure is widened.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging, and in particular to a DPAK packaging structure, electronic circuit, and electronic device. Background Technology

[0002] DPAK packaging is a packaging technology widely used in power semiconductor devices, and it has been widely applied in high-power applications such as power management, motor drives, and DC-DC converters.

[0003] However, in existing DPAK package structures, the pin spacing is smaller than the high-voltage safety distance. Therefore, existing DPAK package structures cannot package high-voltage power chips, thus limiting the application scenarios of DPAK package structures.

[0004] Therefore, providing a DPAK packaging structure capable of encapsulating high-voltage power chips has become a technology that the industry urgently needs to solve. Utility Model Content

[0005] This invention provides a DPAK packaging structure to solve the problem that the DPAK packaging structure cannot be used to package high-power chips.

[0006] To solve the above-mentioned technical problems, this utility model provides a DPAK packaging structure according to a first aspect, including a lead frame, at least one first chip, and a package body, wherein the package body is used to encapsulate the lead frame and the first chip.

[0007] The lead frame includes:

[0008] First pin;

[0009] A plurality of second pins, wherein the distance between each second pin and the first pin is greater than a first distance; wherein the first pin and the second pins are located on a first side of the package structure;

[0010] A base island is disposed on the surface of the package, and the extension structure of the base island relative to the package is located on the second side of the package; the first chip is mounted on one side of the base island; wherein the distance between the base island and the first pin and the distance between the base island and the plurality of second pins are both greater than the first distance, and the first side and the second side of the package are opposite to each other.

[0011] Optionally, the first distance is 1.8 mm.

[0012] Optionally, the thickness of the packaging structure is 1.2 mm to 2.3 mm.

[0013] Optionally, the width of both the first pin and the second pin is 0.3 mm to 0.5 mm.

[0014] Optionally, the base island has a size of 5.1 mm × 5.7 mm.

[0015] Optionally, the first chip may include a high-power MOS chip.

[0016] Optionally, the first chip includes a driver chip and a high-power MOS chip.

[0017] Optionally, the first pin is electrically connected to the high-power MOS chip and used as a high-voltage current input;

[0018] Several second pins are electrically connected to the driver chip, and the several second pins include:

[0019] The first signal pin is used as a power input.

[0020] The second signal pin is used for voltage and current detection.

[0021] The third signal pin is used for optocoupler current feedback detection.

[0022] The fourth signal pin is used for source current sensing;

[0023] The fifth signal pin is used as ground.

[0024] According to a second aspect, this utility model provides an electronic circuit, which includes the DPAK package structure.

[0025] According to a third aspect, this utility model provides an electronic device, which includes the aforementioned electronic device.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] This invention provides a DPAK package structure. By setting the distances between the first and second pins, the distance between the base island and the first pin, and the distance between the base island and the second pin to be greater than a first distance, the DPAK package structure provided by this invention can be used to package high-voltage, high-power chips. Both the first pin and the base island can be used for high-voltage output, making the use of the DPAK package structure more flexible and thus broadening its application scenarios. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the DPAK packaging structure provided in one embodiment of the present invention. Figure 1 ;

[0029] Figure 2 This is a schematic diagram of the DPAK packaging structure provided in one embodiment of the present invention. Figure 2 .

[0030] Figure label:

[0031] 1 - First pin;

[0032] 2 - Second pin;

[0033] 3-Base island;

[0034] 4-Package;

[0035] 5-Driver chip;

[0036] 6-High-power MOS chips;

[0037] 201 - First signal pin;

[0038] 202 - Second signal pin;

[0039] 203 - Third signal pin;

[0040] 204 - Fourth signal pin;

[0041] 205 - Fifth signal pin. Detailed Implementation

[0042] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0043] In the description of this utility model, it should be understood that the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0044] In the description of this utility model, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0045] In the description of this utility model, "multiple" means multiple, such as two, three, four, etc., unless otherwise explicitly specified.

[0046] In the description of this utility model, unless otherwise expressly specified and limited, the term "connection" and other such terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can refer to a mechanical connection, an electrical connection, or a connection that allows communication between the components; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0047] The technical solution of this utility model will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0048] As described in the background section, the existing DPAK package structure has a pin spacing smaller than the high-voltage safety distance, which makes it impossible to package high-voltage power chips, thus limiting the application scenarios of the DPAK package structure.

[0049] The following analysis of the existing DPAK packaging structure illustrates the problems with it.

[0050] The existing DPAK package structure includes three pins, a base island, a second chip, and a package body; the package body is used to encapsulate the three pins, the base island, and the second chip, the three pins are disposed on a first side of the package body, the base island is disposed on the surface of the package body, and the extension structure of the base island relative to the package body is located on a second side of the package body; wherein, the first side and the second side of the package body are opposite to each other.

[0051] Because the middle pin is connected to the base island, the high-voltage safety distance between the middle pin and the base island is not met. Furthermore, because all three pins are relatively thick, the distance between the pins on either side and the middle pin also does not meet the high-voltage safety distance requirement.

[0052] Therefore, the existing DPAK packaging structure cannot be used to package high-voltage chips, but can only package low-voltage chips within 500V, i.e., the second chip is a low-voltage chip, thus limiting the application scenarios of the existing DPAK packaging structure.

[0053] In view of this, the present invention creatively provides a DPAK packaging structure.

[0054] in, Figure 1 This is a schematic diagram of the DPAK packaging structure provided in one embodiment of the present invention. Figure 1 .

[0055] Please refer to Figure 1 An embodiment of the present invention provides a DPAK packaging structure, the DPAK packaging structure including a lead frame, at least one first chip and a package body 4, the package body 4 being used to encapsulate the lead frame and the first chip;

[0056] The lead frame includes:

[0057] Pin 1;

[0058] A plurality of second pins 2, wherein the distance between each second pin 2 and the first pin 1 is greater than a first distance; wherein the first pin 1 and the second pins 2 are located on the first side of the package structure;

[0059] Base island 3 is disposed on the surface of package 4, and the extension structure of base island 3 relative to package 4 is located on the second side of package 4; the first chip is mounted on one side of base island 3; wherein the distance between base island 3 and the first pin 1 and the distance between base island 3 and the plurality of second pins 2 are both greater than the first distance, and the first side and the second side of package 4 are opposite to each other.

[0060] This invention sets the first pin 1 and several second pins 2 to be unconnected to the base island 3, and sets the distances between the base island 3 and the first pin 1, the base island 3 and the second pins 2, and the first pin 1 and the second pins 2 to be greater than a first distance. That is, the distances between the base island 3 and the first pin 1, the base island 3 and the second pins 2, and the first pin 1 and the second pins 2 all meet the high-voltage safety distance, so that the base island 3 and the first pin 1 can be used as high-voltage output pins. Therefore, the DPAK package structure can be used to package high-power chips, thereby broadening the application scenarios of the DPAK package structure.

[0061] To make the above-mentioned objectives, features and beneficial effects of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0062] The base island 3 is disposed on the surface of the package body 4, and the extension structure of the base island 3 relative to the package body 4 is located on the second side of the package body 4. This makes the area of ​​the base island 3 exposed outside the package body 4 larger, thereby enabling the first chip to dissipate heat better.

[0063] As an example, the size of the base island 3 can be set to 5.1 mm to 5.7 mm.

[0064] In one specific implementation, the first distance is 1.8 mm. This first distance is a safe distance between the high-voltage pin and the low-voltage pin, ensuring safe isolation between them. Therefore, both the first pin 1 and the base island 3 can be used as high-voltage pins.

[0065] In one specific implementation, the width of the first pin 1 and the second pin 2 is 0.3 mm to 0.5 mm. Compared with the pins in existing DPAK package structures, the width of the first pin 1 and the second pin 2 is smaller, allowing more pins to be arranged on one side of the DPAK package structure. This increases the number of functional pins in the DPAK package structure, thereby further expanding its application scenarios. For example, the DPAK package structure of this invention can package two or more chips. Of course, the specific number of the second pin 2 depends on the specific type of the first chip and is not limited here.

[0066] In one specific implementation, the thickness of the DPAK packaging structure can be as thin as 1.2 mm to 2.3 mm.

[0067] As one specific implementation, because the DPAK package structure of this embodiment can package high-power chips, the first chip specifically includes a high-power MOS chip. Furthermore, because the DPAK package structure of this embodiment can package multiple chips, in addition to the high-power MOS chip, the DPAK package structure of this embodiment can also package an IC driver chip.

[0068] Specifically, the material of the high-power MOS chip can be, for example, gallium nitride or silicon carbide. Of course, there are many other types of high-power MOS chips, and this invention is not limited to them.

[0069] in, Figure 2 This is a schematic diagram of the DPAK packaging structure provided in one embodiment of the present invention. Figure 2 .

[0070] Please refer to Figure 2 The following describes the specific functions of the first pin 1 and the plurality of second pins 2, taking the DPAK package structure of this embodiment to package a high-power MOS chip 6 and a driver chip 5 as an example: The first pin 1 is electrically connected to the high-power MOS chip 6 and is used as a high-voltage current input;

[0071] Several second pins 2 are electrically connected to the driver chip 5, and the several second pins 2 include:

[0072] The first signal pin 201 is used as a power input;

[0073] The second signal pin 202 is used for voltage and current detection.

[0074] The third signal pin 203 is used as optocoupler current feedback detection;

[0075] The fourth signal pin 204 is used for source current sensing;

[0076] The fifth signal pin 205 is used as ground.

[0077] It should be noted that the function settings and connection relationships of the first pin 1 and the second pin 2 are not fixed. Those skilled in the art can set them according to the actual situation, and this utility model is not limited thereto.

[0078] In summary, the DPAK packaging structure provided by this utility model, by setting the distance between the first and second pins, the distance between the base island and the first pin, and the distance between the base island and the second pin to be greater than a first distance, enables the DPAK packaging structure to be used to package high-voltage, high-power chips. Furthermore, both the first pin and the base island can be used for high-voltage output, making the use of the DPAK packaging structure more flexible and broadening its application scenarios.

[0079] This utility model embodiment also provides an electronic circuit, which includes the DPAK package structure.

[0080] This utility model embodiment also provides an electronic device, which includes the electronic circuit.

[0081] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A DPAK packaging structure, characterized in that, It includes a lead frame, at least one first chip, and a package, wherein the package is used to encapsulate the lead frame and the first chip; The lead frame includes: First pin; A plurality of second pins, wherein the distance between each second pin and the first pin is greater than a first distance; wherein the first pin and the second pins are located on a first side of the package structure; A base island is disposed on the surface of the package, and the extension structure of the base island relative to the package is located on the second side of the package; the first chip is mounted on one side of the base island; wherein the distance between the base island and the first pin and the distance between the base island and the plurality of second pins are both greater than the first distance, and the first side and the second side of the package are opposite to each other.

2. The DPAK packaging structure according to claim 1, characterized in that, The first distance is 1.8 mm.

3. The DPAK packaging structure according to claim 1, characterized in that, The thickness of the DPAK packaging structure is 1.2 mm to 2.3 mm.

4. The DPAK packaging structure according to claim 1, characterized in that, The width of both the first pin and the second pin is 0.3 mm to 0.5 mm.

5. The DPAK packaging structure according to claim 1, characterized in that, The base island measures 5.1 mm × 5.7 mm.

6. The DPAK packaging structure according to claim 1, characterized in that, The first chip includes a high-power MOS chip.

7. The DPAK packaging structure according to claim 1, characterized in that, The first chip includes a driver chip and a high-power MOS chip.

8. The DPAK packaging structure according to claim 7, characterized in that, The first pin is electrically connected to the high-power MOS chip and is used as a high-voltage current input; Several second pins are electrically connected to the driver chip, and the several second pins include: The first signal pin is used as a power input. The second signal pin is used for voltage and current detection. The third signal pin is used for optocoupler current feedback detection. The fourth signal pin is used for source current sensing; The fifth signal pin is used as ground.

9. An electronic circuit, characterized in that, The electronic circuit includes the DPAK package structure as described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the electronic circuitry as described in claim 9.

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