Network side relay control circuit for uninterruptible power supply upgrading program of optical storage inverter

Abstract

The utility model belongs to the technical field of optical storage inverters, and particularly discloses a network side relay control circuit of an uninterruptible power supply upgrading program of an optical storage inverter. Comprising a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, triodes, triodes, triodes, a first network side relay, a second network side relay and the like. According to the utility model, through the redundant circuit design of the MCU chip, the DSP chip and the ARM chip, when one chip is used for program upgrading, the relay can be kept in a continuous closed state as long as the other two chips are ensured to output normal drive, so that the bypass output is ensured to be always electrified.

Description

Technical Field

[0001] This utility model relates to the field of photovoltaic-storage inverter technology, and in particular to a grid-side relay control circuit for uninterrupted power-off upgrade program of photovoltaic-storage inverter. Background Technology

[0002] Relays are frequently used in inverter circuits for circuit closing and opening control. For safety reasons, grid-side relays are certified to prevent abnormal grid connection caused by single-point failures, thus requiring redundancy in relay control. However, traditional solutions disconnect grid-side relays during inverter program upgrades, resulting in power outages to the bypass output. Utility Model Content

[0003] The purpose of this invention is to solve the technical problems existing in the background art. To this end, a grid-side relay control circuit for uninterrupted power-off upgrade program of photovoltaic-storage inverter is provided.

[0004] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0005] The grid-side relay control circuit for the uninterrupted upgrade program of the photovoltaic-storage inverter includes NAND gate 1, NAND gate 2, NAND gate 3, NAND gate 4, transistor Q1, and transistor Q2.

[0006] The input terminal of the NAND gate is electrically connected to the output terminal of the ARM chip and the first output terminal of the DSP chip;

[0007] The input terminal of the NAND gate 2 is electrically connected to the first output terminal of the DSP chip and the first output terminal of the MCU chip;

[0008] The input terminal of the NAND gate 3 is electrically connected to the first output terminal of the MCU chip and the output terminal of the ARM chip;

[0009] The input terminal of NAND gate 4 is electrically connected to the output terminals of NAND gate 1, NAND gate 2, and NAND gate 3;

[0010] The output of the NAND gate is electrically connected to the base of transistor Q2 through resistor R7. The collector of transistor Q2 is electrically connected to the base of transistor Q1 through a parallel resistor group. The collector of transistor Q1 is electrically connected to the first grid-side relay.

[0011] The following is a further defined technical solution of this utility model: the output terminal of the ARM chip is electrically connected to the input terminals of NAND gate one and NAND gate three through resistor R1, and the output terminal of the ARM chip is grounded through resistor R19.

[0012] The first output terminal of the DSP chip is electrically connected to the input terminals of NAND gate one and NAND gate two through resistor R2, and the first output terminal of the DSP chip is grounded through resistor R20.

[0013] The first output terminal of the MCU chip is electrically connected to the input terminals of NAND gate 2 and NAND gate 3 through resistor R3, and the first output terminal of the MCU chip is grounded through resistor R21.

[0014] The following is a further defined technical solution of this utility model: the base and emitter of the transistor Q2 are electrically connected by a resistor R8, and the emitter of the transistor Q2 is grounded.

[0015] The following is a further defined technical solution of this utility model: the base and emitter of the transistor Q1 are electrically connected by a resistor R9, and the emitter of the transistor Q1 is connected to a 12V power supply voltage.

[0016] The following is a further defined technical solution of this utility model: the positive terminal of the first grid-side relay is electrically connected to the collector of transistor Q1, and the negative terminal of the first grid-side relay is grounded.

[0017] The following is a further defined technical solution of this utility model, which also includes NAND gate 5, NAND gate 6, NAND gate 7, NAND gate 8, transistor Q3 and transistor Q4;

[0018] The input terminal of the NAND gate 5 is electrically connected to the output terminal of the ARM chip and the second output terminal of the DSP chip;

[0019] The input terminal of the NAND gate 6 is electrically connected to the second output terminal of the DSP chip and the second output terminal of the MCU chip;

[0020] The input terminal of the NAND gate 7 is electrically connected to the second output terminal of the MCU chip and the output terminal of the ARM chip;

[0021] The input terminal of NAND gate 8 is electrically connected to the output terminals of NAND gate 5, NAND gate 6, and NAND gate 7.

[0022] The output terminal of the NAND gate is electrically connected to the base of transistor Q4 through resistor R16. The collector of transistor Q4 is electrically connected to the base of transistor Q3 through a parallel resistor group. The collector of transistor Q3 is electrically connected to the second grid-side relay.

[0023] The following is a further defined technical solution of this utility model: the output terminal of the ARM chip is electrically connected to the input terminals of NAND gate 5 and NAND gate 7 through resistor R1, and the output terminal of the ARM chip is grounded through resistor R19.

[0024] The second output terminal of the DSP chip is electrically connected to the input terminals of NAND gate 5 and NAND gate 6 through resistor R11;

[0025] The second output terminal of the MCU chip is electrically connected to the input terminals of NAND gate 6 and NAND gate 7 through resistor R12.

[0026] The following is a further defined technical solution of this utility model: the base and emitter of the transistor Q4 are electrically connected by a resistor R17, and the emitter of the transistor Q4 is grounded.

[0027] The following is a further defined technical solution of this utility model: the base and emitter of the transistor Q3 are electrically connected by a resistor R18, and the emitter of the transistor Q3 is connected to a 12V power supply voltage.

[0028] The following is a further defined technical solution of this utility model: the positive terminal of the second grid-side relay is electrically connected to the collector of transistor Q3, and the negative terminal of the second grid-side relay is grounded.

[0029] Compared with the prior art, the present invention has the following technical effects:

[0030] This invention employs a redundant circuit design for three chips: an MCU chip, a DSP chip, and an ARM chip. When one chip is undergoing an upgrade, as long as the other two chips are driven normally, the relay can remain continuously closed, thus ensuring that the bypass output is always powered.

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is the circuit schematic diagram of this utility model. Detailed Implementation

[0034] To make the above-mentioned objects, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a full understanding of this utility model. However, this utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this utility model. Therefore, this utility model is not limited to the specific embodiments disclosed below.

[0035] like Figure 1 As shown, this embodiment provides a grid-side relay control circuit for the uninterrupted upgrade program of the photovoltaic-storage inverter, which mainly consists of NAND gate 1 A1, NAND gate 2 A2, NAND gate 3 A3, NAND gate 4 A4, NAND gate 5 A5, NAND gate 6 A6, NAND gate 7 A7, NAND gate 8 A8, transistor Q1, transistor Q2, transistor Q3, transistor Q4, first grid-side relay Relay1, and second grid-side relay Relay2.

[0036] It should be noted that the NAND gate is a basic logic circuit in digital circuits. If all inputs are high, the output is low; if at least one input is low, the output is high. The NAND gates A1, A2, A3, A4, A5, A6, A7, and A8 together form a 3-to-2 multiplexer circuit, enabling 3-to-2 multiplexing functionality for ARM chips, DSP chips, and MCU chips.

[0037] The transistors Q1 and Q2 mentioned above are used to drive the first grid-side relay Relay1; the transistors Q3 and Q4 mentioned above are used to drive the second grid-side relay Relay2.

[0038] The output terminal ARM-I / O-DRV1 of the ARM chip is electrically connected to the input terminals of NAND gate A1 and NAND gate A2 through resistor R1 (signal series resistor). The output terminal ARM-I / O-DRV1 of the ARM chip is also electrically connected to the input terminals of NAND gate A5 and NAND gate A7 through resistor R1. The output terminal ARM-I / O-DRV1 of the ARM chip is grounded through resistor R19 (signal pull-down resistor).

[0039] The first output terminal of the DSP chip, DSP-I / O-DRV2, is electrically connected to the input terminals of NAND gate A1 and NAND gate A2 through resistor R2 (signal series resistor). The first output terminal of the DSP chip, DSP-I / O-DRV2, is grounded through resistor R20 (signal pull-down resistor). The second output terminal of the DSP chip, DSP-I / O-DRV4, is electrically connected to the input terminals of NAND gate A5 and NAND gate A6 through resistor R11.

[0040] The first output terminal of the MCU chip, MCU-I / O-DRV3, is electrically connected to the input terminals of NAND gate 2 (A2) and NAND gate 3 (A3) through resistor R3 (signal series resistor). The first output terminal of the MCU chip, MCU-I / O-DRV3, is grounded through resistor R21 (signal pull-down resistor). The second output terminal of the MCU chip, MCU-I / O-DRV5, is electrically connected to the input terminals of NAND gate 6 (A6) and NAND gate 7 (A7) through resistor R12 (signal series resistor).

[0041] The input of NAND gate A4 is electrically connected to the outputs of NAND gates A1, A2, and A3. The input of NAND gate A8 is electrically connected to the outputs of NAND gates A5, A6, and A7.

[0042] The output of NAND gate A4 is electrically connected to the base of transistor Q2 through resistor R7 (transistor current limiting resistor), and the output of NAND gate A8 is electrically connected to the base of transistor Q4 through resistor R16 (transistor current limiting resistor).

[0043] A resistor R8 (transistor input pull-down resistor) is electrically connected between the base and emitter of transistor Q2, and the emitter of transistor Q2 is grounded. The collector of transistor Q2 is electrically connected to the base of transistor Q1 through a parallel resistor group (resistors R4, R5, and R6). A resistor R9 (transistor input pull-down resistor) is electrically connected between the base and emitter of transistor Q1, and the emitter of transistor Q1 is connected to a 12V power supply. The positive terminal of the first grid-side relay Relay1 is electrically connected to the collector of transistor Q1, and the negative terminal of the first grid-side relay Relay1 is grounded.

[0044] A resistor R17 is electrically connected between the base and emitter of transistor Q4, and the emitter of transistor Q4 is grounded. The collector of transistor Q4 is electrically connected to the base of transistor Q3 through a parallel resistor group (resistors R13, R14, and R15). A resistor R18 is electrically connected between the base and emitter of transistor Q3, and the emitter of transistor Q3 is connected to a 12V power supply. The positive terminal of the second grid-side relay Relay2 is electrically connected to the collector of transistor Q3, and the negative terminal of the second grid-side relay Relay2 is grounded.

[0045] When the relay is normally controlled to open and close, ARM-I / O-DRV1 outputs a normally high signal, and MCU-I / O-DRV3 and DSP-I / O-DRV4 output normally low signals: (1) When Relay1 needs to be closed, DSP-I / O-DRV2 outputs a normally high signal, which, after passing through the circuit, outputs a drive signal to drive Relay1. (2) When Relay2 needs to be closed, MCU-I / O-DRV5 outputs a normally high signal, which, after passing through the circuit, outputs a drive signal to drive Relay2.

[0046] When a program upgrade is required, Relay1 and Relay2 must remain closed to maintain power. (1) When an ARM chip upgrade is required, DSP-I / O-DRV2, MCU-I / O-DRV3, DSP-I / O-DRV4, and MCU-I / O-DRV5 are closed simultaneously. Through the circuit, the output drive signal drives Relay1 and Relay2. (2) When a DSP chip upgrade is required, ARM-I / O-DRV1, MCU-I / O-DRV3, and MCU-I / O-DRV5 are closed simultaneously. Through the circuit, the output drive signal drives Relay1 and Relay2. (3) When an MCU chip upgrade is required, DSP-I / O-DRV2, ARM-I / O-DRV1, and DSP-I / O-DRV4 are closed simultaneously. Through the circuit, the output drive signal drives Relay1 and Relay2.

[0047] Therefore, when one of the chips is being upgraded, as long as the other two chips are driven normally, the relay can remain closed, thus ensuring that the bypass output is always powered.

[0048] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model in any way. Any person skilled in the art can make many possible variations and modifications to the technical solution of this utility model using the disclosed methods and techniques, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of this utility model. Therefore, all equivalent changes made based on the shape, structure, and principle of this utility model without departing from its technical solution should be covered within the protection scope of this utility model.

Claims

1. A grid-side relay control circuit for uninterrupted upgrade program of a photovoltaic-storage inverter, characterized in that, This includes NAND gate 1, NAND gate 2, NAND gate 3, NAND gate 4, transistor Q1, and transistor Q2. The input terminal of the NAND gate is electrically connected to the output terminal of the ARM chip and the first output terminal of the DSP chip; The input terminal of the NAND gate 2 is electrically connected to the first output terminal of the DSP chip and the first output terminal of the MCU chip; The input terminal of the NAND gate 3 is electrically connected to the first output terminal of the MCU chip and the output terminal of the ARM chip; The input terminal of NAND gate 4 is electrically connected to the output terminals of NAND gate 1, NAND gate 2, and NAND gate 3; The output of the NAND gate is electrically connected to the base of transistor Q2 through resistor R7. The collector of transistor Q2 is electrically connected to the base of transistor Q1 through a parallel resistor group. The collector of transistor Q1 is electrically connected to the first grid-side relay.

2. The grid-side relay control circuit for uninterrupted upgrade program of photovoltaic-storage inverter as described in claim 1, characterized in that, The output terminal of the ARM chip is electrically connected to the input terminals of NAND gate 1 and NAND gate 3 through resistor R1, and the output terminal of the ARM chip is grounded through resistor R19. The first output terminal of the DSP chip is electrically connected to the input terminals of NAND gate one and NAND gate two through resistor R2, and the first output terminal of the DSP chip is grounded through resistor R20. The first output terminal of the MCU chip is electrically connected to the input terminals of NAND gate 2 and NAND gate 3 through resistor R3, and the first output terminal of the MCU chip is grounded through resistor R21.

3. The grid-side relay control circuit for uninterrupted upgrade program of photovoltaic-storage inverter as described in claim 1, characterized in that, The base and emitter of the transistor Q2 are electrically connected by a resistor R8, and the emitter of the transistor Q2 is grounded.

4. The grid-side relay control circuit for uninterrupted upgrade program of photovoltaic-storage inverter as described in claim 1, characterized in that, The base and emitter of the transistor Q1 are electrically connected by a resistor R9, and the emitter of the transistor Q1 is connected to a 12V power supply voltage.

5. The grid-side relay control circuit for uninterrupted upgrade program of photovoltaic-storage inverter as described in claim 1, characterized in that, The positive terminal of the first grid-side relay is electrically connected to the collector of transistor Q1, and the negative terminal of the first grid-side relay is grounded.

6. The grid-side relay control circuit for uninterrupted upgrade program of photovoltaic-storage inverter as described in claim 1, characterized in that, It also includes NAND gate 5, NAND gate 6, NAND gate 7, NAND gate 8, transistor Q3, and transistor Q4; The input terminal of the NAND gate 5 is electrically connected to the output terminal of the ARM chip and the second output terminal of the DSP chip; The input terminal of the NAND gate 6 is electrically connected to the second output terminal of the DSP chip and the second output terminal of the MCU chip; The input terminal of the NAND gate 7 is electrically connected to the second output terminal of the MCU chip and the output terminal of the ARM chip; The input terminal of NAND gate 8 is electrically connected to the output terminals of NAND gate 5, NAND gate 6, and NAND gate 7; The output terminal of the NAND gate is electrically connected to the base of transistor Q4 through resistor R16. The collector of transistor Q4 is electrically connected to the base of transistor Q3 through a parallel resistor group. The collector of transistor Q3 is electrically connected to the second grid-side relay.

7. The grid-side relay control circuit for uninterrupted upgrade program of photovoltaic-storage inverter as described in claim 6, characterized in that, The output terminal of the ARM chip is electrically connected to the input terminals of NAND gate 5 and NAND gate 7 through resistor R1, and the output terminal of the ARM chip is grounded through resistor R19. The second output terminal of the DSP chip is electrically connected to the input terminals of NAND gate 5 and NAND gate 6 through resistor R11; The second output terminal of the MCU chip is electrically connected to the input terminals of NAND gate 6 and NAND gate 7 through resistor R12.

8. The grid-side relay control circuit for uninterrupted upgrade program of photovoltaic-storage inverter as described in claim 6, characterized in that, The base and emitter of the transistor Q4 are electrically connected by a resistor R17, and the emitter of the transistor Q4 is grounded.

9. The grid-side relay control circuit for uninterrupted upgrade program of photovoltaic-storage inverter as described in claim 6, characterized in that, The base and emitter of the transistor Q3 are electrically connected by a resistor R18, and the emitter of the transistor Q3 is connected to a 12V power supply voltage.

10. The grid-side relay control circuit for uninterrupted upgrade program of photovoltaic-storage inverter as described in claim 6, characterized in that, The positive terminal of the second grid-side relay is electrically connected to the collector of transistor Q3, and the negative terminal of the second grid-side relay is grounded.

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