Packaging structure of GaN chip and electronic equipment

Abstract

The utility model discloses a packaging structure of a GaN chip and electronic equipment. The packaging structure of the GaN chip comprises the GaN chip, a lead frame, a first conductive structure, a second conductive structure and a third conductive structure, the first conductive structure, the second conductive structure and the third conductive structure are connected with the lead frame; the GaN chip comprises a semiconductor body, a grid electrode, a source electrode and a drain electrode, and the semiconductor body is provided with a first conductive column; one of the grid electrode, the source electrode and the drain electrode is connected to the first conductive structure, and the other two of the grid electrode, the source electrode and the drain electrode are respectively connected to the second conductive structure and the third conductive structure; or, two of the grid electrode, the source electrode and the drain electrode are connected to the first conductive structure and the second conductive structure respectively, and the other one of the grid electrode, the source electrode and the drain electrode is connected to the third conductive structure. The heat dissipation path of the packaging structure of the GaN chip is short, so that the parasitic thermal resistance of the packaging structure of the GaN chip is greatly reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technical field especially relates to a kind of packaging structure and electronic equipment of GaN chip. BACKGROUND

[0002] The gate, source and drain of gallium nitride (GaN) chip are located on the same side of the GaN chip. Currently, the packaging of GaN chip is also based on the gate, source and drain located on the same side to realize packaging through wire bonding process. However, due to the gate, source and drain of GaN chip located on the same side, it can only be connected with lead frame by thin lead wire during packaging, which may cause electrode breakdown. At the same time, the heat generated by GaN chip needs to be transferred downward from the junction through the substrate, which results in long heat dissipation path and large parasitic thermal resistance of GaN chip packaging. SUMMARY

[0003] The utility model provides a kind of packaging structure and electronic equipment of GaN chip to solve the problem of electrode breakdown and large parasitic thermal resistance caused by current GaN chip packaging structure.

[0004] In a first aspect, the utility model provides a kind of packaging structure of GaN chip, and the packaging structure of GaN chip includes: GaN chip, lead frame, first conductive structure, second conductive structure and third conductive structure;First conductive structure, second conductive structure and third conductive structure are connected with lead frame;

[0005] The GaN chip includes semiconductor body, gate, source and drain, and the gate, source and drain are located on the first surface of the semiconductor body;The semiconductor body is provided with first conductive column;

[0006] The first conductive structure is located on the second surface of the semiconductor body, and the second conductive structure and the third conductive structure are spaced apart on the side of the drain away from the semiconductor body;One of the gate, source and drain is connected to the first conductive structure through the first conductive column, and the other two of the gate, source and drain are connected to the second conductive structure and the third conductive structure respectively;

[0007] Alternatively, the first conductive structure and the second conductive structure are spaced apart on the second surface of the semiconductor body, and the third conductive structure is located on the side of the drain away from the semiconductor body;Two of the gate, source and drain are connected to the first conductive structure and the second conductive structure respectively through the first conductive column, and the other one of the gate, source and drain is connected to the third conductive structure.

[0008] Optionally, the GaN chip further includes: a dielectric layer;

[0009] The medium layer is located at a first surface of the semiconductor body, a vertical projection of the medium layer on the first surface covers vertical projections of the gate, the source and the drain on the first surface, and the medium layer is used to insulate the gate, the source and the drain from each other; the medium layer is provided with the second conductive column;

[0010] The first conductive structure is located at a second surface of the semiconductor body, the second conductive structure and the third conductive structure are spaced apart on a side of the medium layer away from the semiconductor body; one of the gate, the source and the drain is connected to the first conductive structure through the first conductive column, and the other two of the gate, the source and the drain are respectively connected to the second conductive structure and the third conductive structure through the second conductive column;

[0011] Alternatively, the first conductive structure and the second conductive structure are spaced apart on the second surface of the semiconductor body, and the third conductive structure is located on the side of the medium layer away from the semiconductor body; two of the gate, the source and the drain are respectively connected to the first conductive structure and the second conductive structure through the first conductive column, and the other one of the gate, the source and the drain is connected to the third conductive structure through the second conductive column.

[0012] Optionally, the first conductive structure and the second conductive structure are spaced apart on the second surface of the semiconductor body, and the third conductive structure is located on the side of the drain away from the semiconductor body;

[0013] The drain is connected to the third conductive structure, and the gate and the source are respectively connected to the first conductive structure and the second conductive structure through the first conductive column.

[0014] Optionally, the third conductive structure comprises a first conductive layer and a second conductive layer;

[0015] The first conductive layer is located on the side of the drain away from the semiconductor body, and the second conductive layer is located on the side of the first conductive layer away from the drain; the second conductive layer is connected to the lead frame.

[0016] Optionally, the first conductive structure and the second conductive structure are connected to the lead frame through wire bonding, and the third conductive structure is welded on the lead frame.

[0017] Optionally, the first conductive structure is located on the second surface of the semiconductor body, and the second conductive structure and the third conductive structure are spaced apart on the side of the drain away from the semiconductor body;

[0018] The source is connected to the first conductive structure through the first conductive column, and the gate and the drain are respectively connected to the second conductive structure and the third conductive structure.

[0019] Optionally, the second conductive structure comprises a third conductive layer and a fourth conductive layer, and the third conductive structure comprises a first conductive layer and a second conductive layer;

[0020] The third conductive layer is located on the side of the drain electrode away from the semiconductor body, and the fourth conductive layer is located on the side of the third conductive layer away from the drain electrode; the fourth conductive layer is connected with the lead frame; the first conductive layer is located on the side of the drain electrode away from the semiconductor body, and the second conductive layer is located on the side of the first conductive layer away from the drain electrode; the second conductive layer is connected with the lead frame.

[0021] Optionally, the first conductive structure is welded on the lead frame, and the second conductive structure and the third conductive structure are connected with the lead frame through wire bonding.

[0022] Optionally, the lead frame comprises a copper layer, and the first conductive structure, the second conductive structure and the third conductive structure are connected with the copper layer.

[0023] In the second aspect, the utility model provides a kind of electronic equipment, wherein, electronic equipment includes the packaging structure of GaN chip provided in the first aspect.

[0024] The technical scheme of the embodiment of the utility model, by being provided with first conductive column in the semiconductor body of GaN chip, one or two of gate, source and drain electrode in GaN chip are connected to the conductive structure located at the second surface of semiconductor body, and are connected with lead frame through the conductive structure of the second surface of semiconductor body.Ga N chip remaining two or one are connected to the conductive structure located at the side of drain electrode away from semiconductor body, and are connected with lead frame through the conductive structure located at the side of drain electrode away from semiconductor body.The technical scheme of the embodiment of the utility model, in the packaging structure of GaN chip, the gate, source and drain electrode of GaN chip are not in the same plane, so that the electrode of GaN chip can be connected with lead frame using thicker lead, or be welded together with lead frame in large area, effectively solve the problem that electrode breakdown occurs in the packaging structure of existing GaN chip.Meanwhile, since the gate, source and drain electrode of GaN chip are not in the same plane, and the electrode of GaN chip can be connected with lead frame using thicker lead, or be welded together with lead frame in large area, the heat generated by GaN chip can be transferred to lead frame for heat dissipation from junction through the connection structure of electrode and lead frame, realize the double-side heat dissipation of the packaging structure of GaN chip, and the heat dissipation path is short, so that the parasitic thermal resistance of the packaging structure of GaN chip is greatly reduced.

[0025] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the utility model, and is not used to limit the scope of the utility model. Other features of the utility model will become easy to understand through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical scheme in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0027] Figure 1 is a structure diagram of a packaging structure of a GaN chip provided by the embodiment of the present application;

[0028] Figure 2 is a structure diagram of another packaging structure of a GaN chip provided by the embodiment of the present application;

[0029] Figures 3-6 is a preparation method of the packaging structure of the GaN chip shown in the embodiment of the present application; Figure 2 is a structure diagram corresponding to each step in the preparation method of the packaging structure of the GaN chip shown in the embodiment of the present application;

[0030] Figures 7-9 is a preparation method of the packaging structure of the GaN chip shown in the embodiment of the present application; Figure 1 is a structure diagram corresponding to each step in the preparation method of the packaging structure of the GaN chip shown in the embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the personnel in the technical field better understand the present application scheme, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical scheme in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present application.

[0032] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0033] Figure 1is a structure diagram of a packaging structure of a GaN chip provided by the embodiment of the utility model, Figure 2 is a structure diagram of another packaging structure of a GaN chip provided by the embodiment of the utility model, the packaging structure of the GaN chip 2 includes: the GaN chip 2, the lead frame 1, the first conductive structure 3, the second conductive structure 4 and the third conductive structure 5.The first conductive structure 3, the second conductive structure 4 and the third conductive structure 5 are connected with the lead frame 1.The GaN chip 2 includes a semiconductor body 21, a gate 22, a source 24 and a drain 23, and the gate 22, the source 24 and the drain 23 are located on the first surface of the semiconductor body 21; the semiconductor body 21 is provided with a first conductive column 211.As shown in Figure 1 , the first conductive structure 3 is located on the second surface of the semiconductor body 21, and the second conductive structure 4 and the third conductive structure 5 are spaced apart on the side of the drain 23 away from the semiconductor body 21.One of the gate 22, the source 24 and the drain 23 is connected to the first conductive structure 3 through the first conductive column 211, and the other two of the gate 22, the source 24 and the drain 23 are connected to the second conductive structure 4 and the third conductive structure 5 respectively.As shown in Figure 2 , the first conductive structure 3 and the second conductive structure 4 are spaced apart on the second surface of the semiconductor body 21, and the third conductive structure 5 is located on the side of the drain 23 away from the semiconductor body 21.Two of the gate 22, the source 24 and the drain 23 are connected to the first conductive structure 3 and the second conductive structure 4 through the first conductive column 211 respectively, and the other one of the gate 22, the source 24 and the drain 23 is connected to the third conductive structure 5.

[0034] Specifically, the lead frame 1 can include a direct bonded copper (DBC) ceramic substrate, and the semiconductor body 21 can include a substrate, a buffer layer, a channel layer, a barrier layer and a p-type gate layer. Figure 1 Exemplarily, the source 24 is connected to the first conductive structure 3 located on the second surface of the semiconductor body 21 through the first conductive column 211, and in some embodiments of the utility model, the gate 22 or the drain 23 is also connected to the first conductive structure 3 located on the second surface of the semiconductor body 21 through the first conductive column 211, which is not limited herein.Exemplarily, the source 24 can be connected to the first conductive structure 3 located on the second surface of the semiconductor body 21 through the first conductive column 211, and the gate 22 and the drain 23 can be connected to the second conductive structure 4 and the third conductive structure 5 respectively.The first conductive structure 3, the second conductive structure 4 and the third conductive structure 5 are connected with the lead frame 1, that is, the gate 22, the source 24 and the drain 23 of the GaN chip 2 are connected with the lead frame through the second conductive structure 4, the first conductive structure 3 and the third conductive structure 5 respectively, so as to realize the packaging of the GaN chip 2.

[0035] Figure 2 Exemplarily, the gate 22 and the source 24 are connected to the first conductive structure 3 and the second conductive structure 4 located on the second surface of the semiconductor body 21 through the first conductive column 211, and in some embodiments of the utility model, the gate 22 and the drain 23 or the source 24 and the drain 23 are also connected to the first conductive structure 3 and the second conductive structure 4 located on the second surface of the semiconductor body 21 through the first conductive column 211, which is not specifically limited here. Exemplarily, the gate 22 can be connected to the first conductive structure 3 located on the second surface of the semiconductor body 21 through the first conductive column 211, the source 24 can be connected to the second conductive structure 4 located on the second surface of the semiconductor body 21 through the first conductive column 211, and the drain 23 can be connected to the third conductive structure 5. The first conductive structure 3, the second conductive structure 4 and the third conductive structure 5 are connected with the lead frame 1, that is, the gate 22, the source 24 and the drain 23 of the GaN chip 2 are connected with the lead frame through the first conductive structure 3, the second conductive structure 4 and the third conductive structure 5 respectively, realizing the packaging of the GaN chip 2. Exemplarily, the first conductive column 211 can include a tungsten plug.

[0036] The packaging structure of the GaN chip 2 can also include a plastic package 6, the vertical projection of the plastic package 6 on the lead frame 1 covers the GaN chip 2 and the vertical projection of the connection structure between the GaN chip 2 and the lead frame 1 on the lead frame 1, that is, the plastic package 6 wraps the GaN chip 2 and the connection structure between the GaN chip 2 and the lead frame 1. The plastic package 6 can protect the GaN chip 2 and the circuit connection structure between the GaN chip 2 and the lead frame 1 from external force and external environment, prolonging the service life of the packaging structure of the GaN chip 2. At the same time, the plastic package 6 can also provide mechanical support to prevent the GaN chip 2 from being mechanically impacted.

[0037] The technical scheme of the embodiment of the utility model discloses, through setting first conductive column in the semiconductor body of GaN chip, make one or two of the gate, source and drain in GaN chip connect to the conductive structure of the second surface of semiconductor body, and connect with lead frame through the conductive structure of the second surface of semiconductor body. The remaining two or one of GaN chip are connected to the conductive structure of the side of drain away from semiconductor body, and are connected with lead frame through the conductive structure of the side of drain away from semiconductor body. The technical scheme of the embodiment of the utility model discloses, in the packaging structure of GaN chip, the gate, source and drain of GaN chip are not in the same plane, make the electrode of GaN chip can adopt thicker lead and connect with lead frame, or be welded together with lead frame in large area, effectively solve the problem that the electrode breakdown will occur in the packaging structure of existing GaN chip. Meanwhile, because the gate, source and drain of GaN chip are not in the same plane, and the electrode of GaN chip can adopt thicker lead and connect with lead frame, or be welded together with lead frame in large area, the heat generated by GaN chip can be transferred to lead frame from junction through the connecting structure of electrode and lead frame and radiated, realize the double-side radiating of the packaging structure of GaN chip, and the radiating path is short, thereby greatly reduce the parasitic thermal resistance of the packaging structure of GaN chip.

[0038] Optionally, on the basis of each embodiment described above, continuing to refer to Figure 1 and Figure 2 , the GaN chip 2 further comprises: a dielectric layer 25. The dielectric layer 25 is located on the first surface of the semiconductor body 21, and the vertical projection of the dielectric layer 25 on the first surface covers the vertical projections of the gate 22, the source 24 and the drain 23 on the first surface. The dielectric layer 25 is used to insulate the gate 22, the source 24 and the drain 23 from each other. The dielectric layer 25 is provided with a second conductive column 251, as shown in Figure 1 , the first conductive structure 3 is located on the second surface of the semiconductor body 21, and the second conductive structure 4 and the third conductive structure 5 are located on the side of the dielectric layer 25 away from the semiconductor body 21. One of the gate 22, the source 24 and the drain 23 is connected to the first conductive structure 3 through the first conductive column 211, and the other two of the gate 22, the source 24 and the drain 23 are connected to the second conductive structure 4 and the third conductive structure 5 respectively through the second conductive column 251. Alternatively, as shown in Figure 2 , the first conductive structure 3 and the second conductive structure 4 are located on the second surface of the semiconductor body 21, and the third conductive structure 5 is located on the side of the dielectric layer 25 away from the semiconductor body 21. Two of the gate 22, the source 24 and the drain 23 are connected to the first conductive structure 3 and the second conductive structure 4 respectively through the first conductive column 211, and the other one of the gate 22, the source 24 and the drain 23 is connected to the third conductive structure 5 through the second conductive column 251.

[0039] Specifically, the GaN chip 2 can further include a dielectric layer 25, in which a second conductive pillar 251 can be disposed. The second conductive pillar 251 can include, for example, a tungsten plug.

[0040] As shown in FIG. 1, one of the gate 22, the source 24 and the drain 23 of the GaN chip 2 can be connected to the first conductive structure 3 through the first conductive pillar 211, and the other two electrodes can be connected to the second conductive structure 4 and the third conductive structure 5, respectively, through the second conductive pillar 251. The second conductive structure 4 and the third conductive structure 5 can be insulated by the dielectric layer 25. Figure 1 As shown in FIG. 2, two of the gate 22, the source 24 and the drain 23 of the GaN chip 2 can be connected to the first conductive structure 3 and the second conductive structure 4, respectively, through the first conductive pillar 211, and the other electrode can be connected to the third conductive structure 5 through the second conductive pillar 251.

[0041] Figure 2 As shown in FIG. 3, two of the gate 22, the source 24 and the drain 23 of the GaN chip 2 can be connected to the first conductive structure 3 and the second conductive structure 4, respectively, through the first conductive pillar 211, and the other electrode can be connected to the third conductive structure 5 through the second conductive pillar 251.

[0042] Optionally, on the basis of the above embodiments, with reference to FIG. 4, when any two of the gate 22, the source 24 and the drain 23 of the GaN chip 2 are connected to the second surface of the semiconductor body 21 through the first conductive pillar 211, the first conductive structure 3 and the second conductive structure 4 are spaced apart on the second surface of the semiconductor body 21, and the third conductive structure 5 is located on the side of the drain 23 away from the semiconductor body 21. The drain 23 is connected to the third conductive structure 5, and the gate 22 and the source 24 are connected to the first conductive structure 3 and the second conductive structure 4, respectively, through the first conductive pillar 211. Figure 2 Specifically, any two of the gate 22, the source 24 and the drain 23 of the GaN chip 2 can be connected to the second surface of the semiconductor body 21 through the first conductive pillar 211. For example, the gate 22 can be connected to the first conductive structure 3 on the second surface of the semiconductor body 21 through the first conductive pillar 211, the source 24 can be connected to the second conductive structure 4 on the second surface of the semiconductor body 21 through the first conductive pillar 211, and the drain 23 can be connected to the third conductive structure 5. The first conductive structure 3, the second conductive structure 4 and the third conductive structure 5 are connected to the lead frame 1, that is, the gate 22, the source 24 and the drain 23 of the GaN chip 2 are connected to the lead frame through the first conductive structure 3, the second conductive structure 4 and the third conductive structure 5, respectively, to realize the packaging of the GaN chip 2.

[0043]

[0044] ​​In the packaging structure of the GaN chip, the gate, the source and the drain of the GaN chip are not in the same plane, so that the electrodes of the GaN chip can be connected with the lead frame by thick leads or are welded with the lead frame in a large area, effectively solving the problem of electrode breakdown in the existing packaging structure of the GaN chip. At the same time, the packaging structure of the GaN chip can realize double-sided heat dissipation, the heat dissipation path is short, and thus the parasitic thermal resistance of the packaging structure of the GaN chip is greatly reduced.

[0045] Optionally, on the basis of each of the above embodiments, with reference to Figure 2 When any two of the gate 22, the source 24 and the drain 23 of the GaN chip 2 are connected to the second surface of the semiconductor body 21 through the first conductive column 211, the third conductive structure 5 comprises: a first conductive layer 51 and a second conductive layer 52. The first conductive layer 51 is located on the side of the drain 23 away from the semiconductor body 21, and the second conductive layer 52 is located on the side of the first conductive layer 51 away from the drain 23. The second conductive layer 52 is connected with the lead frame 1.

[0046] Specifically, any two of the gate 22, the source 24 and the drain 23 of the GaN chip 2 can be connected to the second surface of the semiconductor body 21 through the first conductive column 211, and the other electrode can be connected to the conductive structure located on the side of the dielectric layer 25 away from the semiconductor body 21 through the second conductive column 251. The third conductive structure 5 is located on the side of the drain 23 away from the semiconductor body 21, that is, the third conductive structure 5 is located on the side of the dielectric layer 25 away from the semiconductor body 21, at this time, the third conductive structure 5 can be provided to comprise a first conductive layer 51 and a second conductive layer 52, the material of the first conductive layer 51 can be the same as that of the electrode connected therewith, and the material of the second conductive layer 52 can be copper, nickel-gold alloy or titanium-nickel-silver alloy, etc.

[0047] Optionally, on the basis of each of the above embodiments, with reference to Figure 2 When any two of the gate 22, the source 24 and the drain 23 of the GaN chip 2 are connected to the second surface of the semiconductor body 21 through the first conductive column 211, the first conductive structure 3 and the second conductive structure 4 are connected with the lead frame 1 through wire bonding; and the third conductive structure 5 is welded on the lead frame 1.

[0048] Specifically, two of the gate 22, the source 24 and the drain 23 of the GaN chip 2 can be connected to the first conductive structure 3 and the second conductive structure 4 respectively through the first conductive column 211, and the other electrode can be connected to the third conductive structure 5 through the second conductive column 251. The third conductive structure 5 is arranged close to the lead frame 1, and the first conductive structure 3 and the second conductive structure 4 are arranged away from the lead frame 1. At this time, the third conductive structure 5 can be welded on the lead frame 1, and can also be pasted on the lead frame 1 through conductive glue. The first conductive structure 3 and the second conductive structure 4 can be connected with the lead frame 1 through wire bonding, that is, the lead wire 7 is bonded and connected with the first conductive structure 3 and the second conductive structure 4, and the lead wire 7 is also bonded and connected with the lead frame 1. In addition, the lead wire 7 can also be welded on the first conductive structure 3 and the second conductive structure 4, and can also be welded on the lead frame 1.

[0049] Optionally, on the basis of each of the above embodiments, continuing to refer to Figure 1 When any one of the gate 22, the source 24 and the drain 23 of the GaN chip 2 is connected to the second surface of the semiconductor body 21 through the first conductive column 211, the first conductive structure 3 is located on the second surface of the semiconductor body 21, and the second conductive structure 4 and the third conductive structure 5 are spaced apart on the side of the drain 23 away from the semiconductor body 21. The source 24 is connected to the first conductive structure 3 through the first conductive column 211, and the gate 22 and the drain 23 are connected to the second conductive structure 4 and the third conductive structure 5 respectively.

[0050] Specifically, any one of the gate 22, the source 24 and the drain 23 of the GaN chip 2 can be connected to the second surface of the semiconductor body 21 through the first conductive column 211. For example, the source 24 can be connected to the first conductive structure 3 located on the second surface of the semiconductor body 21 through the first conductive column 211, and the gate 22 and the drain 23 can be connected to the second conductive structure 4 and the third conductive structure 5 respectively. The first conductive structure 3, the second conductive structure 4 and the third conductive structure 5 are connected with the lead frame 1, that is, the gate 22, the source 24 and the drain 23 of the GaN chip 2 are connected with the lead frame through the second conductive structure 4, the first conductive structure 3 and the third conductive structure 5 respectively, realizing the packaging of the GaN chip 2.

[0051] In the packaging structure of the GaN chip, the gate, the source and the drain of the GaN chip are not in the same plane, so that the electrodes of the GaN chip can be connected with the lead frame through relatively thick lead wires, or can be welded together with the lead frame in a large area, effectively solving the problem that the electrodes of the existing GaN chip packaging structure can be broken down. At the same time, the double-sided heat dissipation of the packaging structure of the GaN chip can be realized, the heat dissipation path is short, and thus the parasitic thermal resistance of the packaging structure of the GaN chip is greatly reduced.

[0052] Optionally, on the basis of each of the above embodiments, with reference to the above Figure 1 When any one of the gate 22, the source 24 and the drain 23 of the GaN chip 2 is connected to the second surface of the semiconductor body 21 through the first conductive pillar 211, the second conductive structure 4 includes a third conductive layer 41 and a fourth conductive layer 42, and the third conductive structure 5 includes a first conductive layer 51 and a second conductive layer 52. The third conductive layer 41 is located on the side of the drain 23 away from the semiconductor body 21, and the fourth conductive layer 42 is located on the side of the third conductive layer 41 away from the drain 23. The fourth conductive layer 42 is connected to the lead frame 1. The first conductive layer 51 is located on the side of the drain 23 away from the semiconductor body 21, and the second conductive layer 52 is located on the side of the first conductive layer 51 away from the drain 23. The second conductive layer 52 is connected to the lead frame 1.

[0053] Specifically, any one of the gate 22, the source 24 and the drain 23 of the GaN chip 2 can be connected to the second surface of the semiconductor body 21 through the first conductive pillar 211, and the other two electrodes can be connected to the conductive structures located on the side of the dielectric layer 25 away from the semiconductor body 21 through the second conductive pillars 251. The second conductive structure 4 and the third conductive structure 5 are spaced apart on the side of the dielectric layer 25 away from the semiconductor body 21, and at this time, the second conductive structure 4 can be provided to include the third conductive layer 41 and the fourth conductive layer 42, and the third conductive structure 5 can be provided to include the first conductive layer 51 and the second conductive layer 52. The materials of the third conductive layer 41 and the first conductive layer 51 can be the same as the materials of the electrodes connected thereto, and the materials of the fourth conductive layer 42 and the second conductive layer 52 can be copper, nickel-gold alloy, or titanium-nickel-silver alloy, etc.

[0054] Optionally, on the basis of each of the above embodiments, with reference to the above Figure 1 When any one of the gate 22, the source 24 and the drain 23 of the GaN chip 2 is connected to the second surface of the semiconductor body 21 through the first conductive pillar 211, the first conductive structure 3 is soldered on the lead frame 1, and the second conductive structure 4 and the third conductive structure 5 are connected to the lead frame 1 through wire bonding.

[0055] Specifically, any one of the gate 22, the source 24 and the drain 23 of the GaN chip 2 can be connected to the first conductive structure 3 through the first conductive column 211, and the other two electrodes can be connected to the second conductive structure 4 and the third conductive structure 5 through the second conductive column 251 respectively. The first conductive structure 3 is arranged close to the lead frame 1, and the second conductive structure 4 and the third conductive structure 5 are arranged away from the lead frame 1, at this time, the first conductive structure 3 can be welded on the lead frame 1, and can also be pasted on the lead frame 1 through conductive glue. The second conductive structure 4 and the third conductive structure 5 can be connected with the lead frame 1 through wire bonding, that is, the lead wire 7 is bonded and connected with the second conductive structure 4 and the third conductive structure 5, and the lead wire 7 is also bonded and connected with the lead frame 1. In addition, the lead wire 7 can also be welded on the second conductive structure 4 and the third conductive structure 5, and can also be welded on the lead frame 1.

[0056] Optionally, on the basis of each of the above embodiments, continuing to refer to Figure 1 and Figure 2 , the lead frame 1 comprises a copper layer 11, and the first conductive structure 3, the second conductive structure 4 and the third conductive structure 5 are connected with the copper layer 11.

[0057] Specifically, the lead frame 1 can comprise a copper layer 11, and the copper layer 11 is patterned through photolithography and etching. For example, as shown in Figure 1 , the lead wire 7 can be bonded and connected with the copper layer 11, or can be welded together with the copper layer 11. The first conductive structure 3 can be welded on the copper layer 11, or can be pasted on the copper layer 11 through a conductive adhesive tape. As shown in Figure 2 , the lead wire 7 can be bonded and connected with the copper layer 11, or can be welded together with the copper layer 11. The third conductive structure 5 can be welded on the copper layer 11, or can be pasted on the copper layer 11 through a conductive adhesive tape.

[0058] The utility model embodiment provides a kind of electronic equipment, wherein, electronic equipment includes the packaging structure of any one GaN chip provided in any one of the above embodiments, with the beneficial effects of the packaging structure of any one GaN chip provided in any one of the above embodiments of the utility model.

[0059] Optionally, Figures 3-6 is the preparation method of the packaging structure of GaN chip provided in the utility model embodiment. Figure 2 As shown in Figure 3 , Figure 3 is a top view of a GaN chip, a first conductive column 211 is arranged in a semiconductor body 21, and a second conductive column 251 is arranged in a dielectric layer. Figure 3 The dielectric layer is not shown in Figure 4 , Figure 4is a sectional view of a GaN chip, a first conductive layer 51 is formed on a side of a dielectric layer 25 away from a semiconductor body 21, a drain electrode 23 is connected to the first conductive layer 51 through a second conductive column 251, and a second surface of the semiconductor body 21 is thinned. Figure 5 As shown in the figure, a second conductive layer 52 is formed on a side of the first conductive layer 51 away from the semiconductor body 21, and a first conductive structure 3 and a second conductive structure 4 are formed on the second surface of the semiconductor body 21. Figure 6 As shown in the figure, Figure 6 is a top view of a packaging structure of a GaN chip, the GaN chip is surface-mounted, and the first conductive structure 3 and the second conductive structure 4 are connected to a copper layer 11 through wire bonding or soldering of a tin paste.

[0060] Optionally, Figures 7-9 is a preparation method of a packaging structure of a GaN chip provided by an embodiment of the present application. Figure 1 As shown in the figure, Figure 7 As shown in the figure, Figure 7 is a top view of a GaN chip, a first conductive column 211 is arranged in a semiconductor body 21, and a second conductive column 251 is arranged in a dielectric layer. Figure 7 The dielectric layer is not shown in the figure. As shown in the figure, Figure 8 A first conductive structure 3 is formed on a second surface of the semiconductor body 21, and a second conductive structure 4 and a third conductive structure 5 are formed on a side of a dielectric layer 25 away from the semiconductor body 21. Figure 9 As shown in the figure, Figure 9 is a top view of a packaging structure of a GaN chip, the GaN chip is surface-mounted, and the second conductive structure 4 and the third conductive structure 5 are connected to a copper layer 11 through wire bonding or soldering of a tin paste.

[0061] It should be understood that the various forms of the flow shown above can be used to reorder, add or delete steps. For example, the steps described in the present application can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0062] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A packaging structure of a GaN chip, characterized by, The application relates to a GaN chip, a lead frame, a first conductive structure, a second conductive structure and a third conductive structure. The first conductive structure, the second conductive structure and the third conductive structure are connected with the lead frame. The GaN chip comprises a semiconductor body, a gate, a source and a drain, the gate, the source and the drain are located on a first surface of the semiconductor body; the semiconductor body is provided with a first conductive column; The first conductive structure is located on a second surface of the semiconductor body, the second conductive structure and the third conductive structure are located on a side of the drain away from the semiconductor body; one of the gate, the source and the drain is connected to the first conductive structure through the first conductive column, and the other two of the gate, the source and the drain are connected to the second conductive structure and the third conductive structure respectively; Alternatively, the first conductive structure and the second conductive structure are located on the second surface of the semiconductor body, and the third conductive structure is located on the side of the drain away from the semiconductor body; two of the gate, the source and the drain are connected to the first conductive structure and the second conductive structure respectively through the first conductive column, and the other one of the gate, the source and the drain is connected to the third conductive structure. The GaN chip further comprises a dielectric layer; 2. The packaging structure of GaN chips according to claim 1, wherein, The dielectric layer is located on the first surface of the semiconductor body, a vertical projection of the dielectric layer on the first surface covers vertical projections of the gate, the source and the drain on the first surface, and the dielectric layer is used for insulating the gate, the source and the drain from each other; the dielectric layer is provided with a second conductive column; The first conductive structure is located on the second surface of the semiconductor body, the second conductive structure and the third conductive structure are located on a side of the dielectric layer away from the semiconductor body; one of the gate, the source and the drain is connected to the first conductive structure through the first conductive column, and the other two of the gate, the source and the drain are connected to the second conductive structure and the third conductive structure respectively through the second conductive column; Alternatively, the first conductive structure and the second conductive structure are located on the second surface of the semiconductor body, and the third conductive structure is located on the side of the dielectric layer away from the semiconductor body; two of the gate, the source and the drain are connected to the first conductive structure and the second conductive structure respectively through the first conductive column, and the other one of the gate, the source and the drain is connected to the third conductive structure through the second conductive column. The first conductive structure and the second conductive structure are located on the second surface of the semiconductor body, and the third conductive structure is located on the side of the drain away from the semiconductor body; 3. The packaging structure of GaN chips according to claim 1, wherein, The drain is connected to the third conductive structure, and the gate and the source are connected to the first conductive structure and the second conductive structure respectively through the first conductive column. The third conductive structure comprises a first conductive layer and a second conductive layer.

4. The packaging structure of GaN chips according to claim 3, wherein, ​ The first conductive layer is located on the side of the drain away from the semiconductor body, and the second conductive layer is located on the side of the first conductive layer away from the drain; the second conductive layer is connected with the lead frame.

5. The packaging structure of GaN chips according to claim 3, wherein, The first conductive structure and the second conductive structure are connected with the lead frame through wire bonding, and the third conductive structure is welded on the lead frame.

6. The packaging structure of GaN chips according to claim 1, wherein, The source is connected to the first conductive structure through the first conductive column, and the gate and the drain are connected to the second conductive structure and the third conductive structure respectively.

7. The packaging structure of GaN chips according to claim 6, wherein, The second conductive structure comprises a third conductive layer and a fourth conductive layer, and the third conductive structure comprises a first conductive layer and a second conductive layer. The third conductive layer is located on the side of the drain away from the semiconductor body, and the fourth conductive layer is located on the side of the third conductive layer away from the drain; the fourth conductive layer is connected with the lead frame; the first conductive layer is located on the side of the drain away from the semiconductor body, and the second conductive layer is located on the side of the first conductive layer away from the drain; the second conductive layer is connected with the lead frame.

8. The packaging structure of GaN chips according to claim 6, wherein, The first conductive structure is welded on the lead frame, and the second conductive structure and the third conductive structure are connected with the lead frame through wire bonding.

9. The packaging structure of GaN chips according to claim 1, wherein, The lead frame comprises a copper layer, and the first conductive structure, the second conductive structure and the third conductive structure are connected with the copper layer.

10. An electronic device, comprising: A packaging structure comprising the GaN chip of any one of claims 1-9. A packaging structure comprising the GaN chip of any one of claims 1-9.

Images