Chip structure

Abstract

The utility model discloses a chip structure, which comprises a first base layer, a second base layer and a box dam structure connected with the first base layer and the second base layer, the first base layer is provided with a through hole penetrating along the thickness direction of the first base layer, the second base layer comprises a first welding pad area, and the chip structure comprises a heat dissipation column arranged in the through hole. The box dam structure comprises a second metal supporting dam used for connecting the heat dissipation column and the first welding pad area; the first welding pad area, the second metal supporting dam and the heat dissipation column form an upward heat dissipation channel, so that the heat dissipation capability is enhanced.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of semiconductor package testing especially relates to a chip structure. BACKGROUND

[0002] In prior art, image sensing chip package structure usually includes cover plate wafer, device wafer and dam structure. The surface of device wafer facing cover plate wafer is provided with solder pad area, and the surface of device wafer away from cover plate wafer is provided with through hole and soldering column. On the one hand, soldering column is used for electrically connecting to outside, on the other hand, through hole and soldering column can form downward heat dissipation channel for heat dissipation of chip structure.

[0003] However, with the progress of semiconductor chip package structure process, the number of transistors per unit area is increasing, and the unit heat of chip package structure will also increase, so the heat dissipation capacity of chip package structure needs to be strengthened. SUMMARY

[0004] One of the purposes of the utility model is to provide a chip structure to solve the technical problem of insufficient heat dissipation capacity in prior art.

[0005] To achieve the above-mentioned one of the purposes of the utility model, one embodiment of the utility model provides a chip structure, which comprises: first base layer, second base layer and dam structure connecting first base layer and second base layer, the first base layer is provided with through hole penetrating along its thickness direction, the second base layer comprises first solder pad area, the chip structure comprises heat dissipation column arranged in the through hole, and the dam structure comprises second metal support dam for connecting the heat dissipation column and the first solder pad area.

[0006] As a further improvement of one embodiment of the utility model, the second base layer has functional surface and functional area arranged on the functional surface, the first solder pad area is located outside the functional area, and the second metal support dam is arranged outside the functional area.

[0007] As a further improvement of one embodiment of the utility model, the first base layer has first surface facing the second base layer and second surface away from the second base layer, the through hole penetrates the first surface and the second surface, the chip structure comprises heat dissipation layer arranged on the second surface, and one end of the heat dissipation column away from the second metal support dam is connected to the heat dissipation layer.

[0008] As a further improvement of one embodiment of the utility model, the area covered by the heat dissipation layer is opposite to the area outside the functional area.

[0009] As a further improvement of one embodiment of the utility model, the area covered by the heat dissipation layer is opposite to the functional area and the first solder pad area.

[0010] As a further improvement of the embodiment of the present application, the chip structure comprises a heat dissipation module arranged on the heat dissipation layer.

[0011] As a further improvement of the embodiment of the present application, the chip structure comprises a circuit board arranged on the second base layer away from the first base layer, the first pad area is connected to the circuit board, and the heat dissipation module is connected to a heat dissipation area of the circuit board.

[0012] As a further improvement of the embodiment of the present application, the dam structure comprises a first metal support dam located outside the second metal support dam, the first metal support dam is located outside the first pad area, and a gap is formed between the first metal support dam and the second metal support dam.

[0013] As a further improvement of the embodiment of the present application, the dam structure comprises an organic support dam located between the first base layer and the second base layer, and the organic support dam is located outside the functional area.

[0014] As a further improvement of the embodiment of the present application, the first base layer has a first surface facing the second base layer and a second surface away from the second base layer, the chip structure comprises a metal light shielding layer attached to the first surface, the metal light shielding layer is located outside the functional area, and the metal light shielding layer is thinner than the dam structure.

[0015] Compared with the prior art, the chip structure of the present application forms an upward heat dissipation channel through the heat dissipation column, the first pad area and the second metal support dam connecting the heat dissipation column and the first pad area, thereby enhancing the heat dissipation capacity. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a schematic diagram of the chip structure in the first embodiment of the present application.

[0017] Figure 2 is a schematic diagram of the chip structure in the second embodiment of the present application.

[0018] Figure 3 is a schematic diagram of the chip structure in the third embodiment of the present application.

[0019] Figure 4 is a schematic diagram of the chip structure in the fourth embodiment of the present application.

[0020] Figure 5 is a schematic diagram of the chip structure in the fourth embodiment of the present application.

[0021] Figure 6 is a schematic diagram of the chip structure in the fourth embodiment of the present application.

[0022] Figure 7 is a step schematic diagram of manufacturing the second metal supporting dam in the second embodiment of the utility model.

[0023] Figure 8 is a step schematic diagram of manufacturing the second metal supporting dam in the third embodiment of the utility model.

[0024] Figure 9 is a step schematic diagram of manufacturing the second metal supporting dam in the fourth embodiment of the utility model.

[0025] Figure 10 is a step schematic diagram of bonding the first wafer and the second wafer in an embodiment of the utility model.

[0026] Figure 11 is a step schematic diagram of cutting the wafer level package structure in an embodiment of the utility model.

[0027] Figure 12 is a schematic diagram of the first wafer surface heat dissipation layer in an embodiment of the utility model.

[0028] Figure 13 is a schematic diagram of the heat dissipation layer surface setting heat dissipation module in an embodiment of the utility model.

[0029] Figure 14 is a schematic diagram of the heat dissipation module connecting to the circuit board in an embodiment of the utility model. DETAILED DESCRIPTION

[0030] The utility model will be described in detail below in combination with the specific embodiments shown in the drawings. But these embodiments do not limit the utility model, and the structural, method or functional changes made by the ordinary skilled in the art according to these embodiments are all included in the protection scope of the utility model.

[0031] It should be noted that the term "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. In addition, the terms "first", "second", "third", "fourth" and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0032] The term "connect", "connected to" or any other variant is intended to cover various relative positions of connection, so as to include direct connection or indirect connection.

[0033] Please refer to Figure 1 A structure diagram of a chip structure 1000 provided by an embodiment of the present application is shown in the figure.

[0034] The chip structure 1000 comprises a first base layer 10, a second base layer 20 and a dam structure 30 connecting the first base layer 10 and the second base layer 20, the first base layer 10 is provided with a through hole 101 penetrating along the thickness direction thereof, the second base layer 20 comprises a first solder pad area 22, the chip structure 1000 comprises a heat dissipation column 40 arranged in the through hole 101, and the dam structure 30 comprises a second metal support dam 32 for connecting the heat dissipation column 40 and the first solder pad area 21.

[0035] The heat dissipation column 40, the first solder pad area 22 and the second metal support dam 32 form an upward heat dissipation channel, thereby enhancing the heat dissipation capacity of the chip structure 1000.

[0036] The connection between the second metal support dams 32 of the first solder pad area 21 can be electrical connection or insulation connection, and it can be understood that when the two are electrically connected, other wiring electrical connection design can be reduced and the heat conduction performance can be enhanced, but the second metal support dam 32 needs to be matched with the first solder pad area 21 to be arranged as an intermittent annular structure to prevent a loop from being formed between the first solder pad areas 21; when the two are insulated, the first solder pad area 21 can be selected to be arranged as a continuous annular structure or an intermittent annular structure; the annular structure of the connection has better air tightness.

[0037] The first base layer 10 can be a cover plate base layer, the first base layer 10 has a first surface facing the second base layer 20 and a second surface away from the second base layer 20, the through hole 101 penetrates the first surface and the second surface, the heat dissipation column 40 is arranged in the through hole 101, the heat dissipation column 40 is a metal material and can conduct heat to transfer the heat of the first surface of the first base layer 10 to the second surface and dissipate it.

[0038] The chip structure 1000 comprises a heat dissipation layer 41 arranged on the second surface, one end of the heat dissipation column 40 away from the second metal support dam 32 is connected to the heat dissipation layer 41, the heat dissipation layer 41 is also a metal material, the heat dissipation layer 41 is attached to the second surface and has a relatively thin thickness, which is used to increase the heat dissipation area and improve the heat dissipation efficiency.

[0039] refer to Figure 1 In the first embodiment, the area covered by the heat dissipation layer 41 is opposite to the functional area 21 and the first pad area 22. The heat dissipation layer 41 basically covers the entire area of ​​the second surface to increase the heat dissipation area and improve the heat dissipation efficiency. This type of heat dissipation layer 41 is designed for chip structures 1000 with high heat dissipation requirements.

[0040] refer to Figure 2 In the second embodiment, the area covered by the heat dissipation layer 41 is opposite to the area outside the functional area 21. It can be seen that the heat dissipation layer 41 does not block the functional area 21, but is only disposed on the outer periphery of the second surface. On the one hand, it can be used for heat dissipation; on the other hand, in special applications, it can be used for light shielding to improve optical performance.

[0041] In other embodiments, the heat dissipation layer 41 may be optionally configured to have other shapes or structures. The key point is that the heat dissipation layer 41 should be connected to the heat dissipation column 40 in order to dissipate the heat emitted by the first pad area 22.

[0042] The chip structure 1000 includes a heat dissipation module 42 disposed on the heat dissipation layer 41, combined with Figure 13 As shown, an independent heat dissipation block or heat dissipation fin is added to the surface of the heat dissipation layer 41.

[0043] Combination Figure 14 As shown, the chip structure includes a circuit board 50 disposed on the side of the second base layer 20 away from the first base layer 10, the first solder pad area 22 is connected to the circuit board 50, and the heat dissipation module 42 is connected to the heat dissipation area of ​​the circuit board 50. In other embodiments, the heat dissipation module 42 can also be connected to the circuit board 50 at the same time to enhance the heat dissipation performance.

[0044] The second base layer 20 can be selected as a device base layer. The second base layer 20 includes an electrically coupled functional area 21 and a first pad area 22. The dam structure 30 is arranged outside the functional area 21 and is ring-shaped.

[0045] The second base layer 20 has a functional surface facing the first base layer 10. The functional area 21 is disposed on the functional surface. The first welding pad area 22 is located outside the functional area 21. The second metal support dam 32 is ring-shaped and surrounds the functional area 21. When the second metal support dam 32 and the first welding pad area 22 are connected by insulating adhesive, the second metal support dam 32 can be optionally configured as a continuous ring structure to enhance the sealing performance.

[0046] The dam structure 30 includes a first metal support dam 31 outside the second metal support dam 32, the first metal support dam 31 is outside the first pad area 22, and the first metal support dam 31 and the second metal support dam 32 have a gap therebetween.

[0047] The first metal support dam 31 is arranged as a continuous ring structure and is close to the outer periphery of the chip structure 1000, and is sealed at the outer side to prevent moisture and water vapor from entering; the second metal support dam 32 is arranged in the second pad area, which is not only used for heat dissipation, but also used for sealing connection in one application scenario, and can also be used to realize electrical connection between the first base layer 10 and the second base layer 20 in other application scenarios, reduce other wiring design, and facilitate miniaturization of the chip structure 1000.

[0048] The first and second metal support dams are annular, in other words, the dam structure 30 includes at least two metal support dams, and at least one metal support dam is a continuous ring structure to enhance airtightness. In other embodiments, a continuous ring metal support dam can be further added to provide better airtightness and support.

[0049] The dam structure 30 includes an organic support dam 33 between the first base layer 10 and the second base layer 20, and the organic support dam 33 is outside the functional area 21. The dam structure 30 is formed as a hybrid support dam to prevent the metal support dam from being too soft to provide better support, while saving costs. The organic support dam 33 is arranged outside the first and second metal support dams.

[0050] The chip structure 1000 includes a metal light shielding layer 60 attached to the first surface, the metal light shielding layer 60 is outside the functional area 21, and the metal light shielding layer 60 is thinner than the dam structure 30. In combination Figures 3-4 As shown, the inner side of the second metal support dam 32 and the outer side of the functional area 21 are provided with a metal light shielding layer 60, which is used to shield stray light and other light that negatively affects imaging, to improve optical performance.

[0051] The present application also discloses a wafer level packaging method, in combination Figures 5-6 The chip structure 1000 is made by the wafer level packaging method. The wafer level packaging method includes the following steps:

[0052] A first wafer 100 and a second wafer 200 are provided, the first wafer 100 is a cover wafer, and the second wafer 200 is a device wafer, the second wafer 200 includes a function area 21 and a pad area 22 electrically coupled.

[0053] In the first wafer 100, a through hole 101 is formed, which penetrates the first and second surfaces of the first wafer 100 and is arranged along the thickness direction of the first wafer 100.

[0054] A heat dissipation column 40 is formed in the through hole 101.

[0055] A second metal support dam 32 is formed, which is connected to the heat dissipation column 40.

[0056] The second metal support dam 32 and the first pad area 22 are connected, which is equivalent to connecting the first wafer 100 and the second wafer 200.

[0057] In this way, the first pad area 22, the second metal support dam 32, and the heat dissipation column 40 form a heat dissipation channel.

[0058] The "forming a heat dissipation column 40 in the through hole 101" includes:

[0059] In combination with Figure 5 b, a metal layer is plated on the surface of the first wafer 100 and in the through hole 101, forming a metal seed layer on the surface of the first wafer 100 and a heat dissipation column 40 in the through hole 101.

[0060] After "forming a heat dissipation column 40 in the through hole 101", it further includes patterning the metal seed layer to form a heat dissipation layer 41 on the second surface. In combination with Figures 6-7 As shown in

[0061] In combination with Figure 6 a, 7a, and 8a, 9a, "patterning the metal seed layer" includes: coating a colloidal layer on part of the surface of the metal seed layer, and the position where the colloidal layer is coated is the position of the heat dissipation layer 41 that needs to be reserved. Therefore, the colloidal layer can be coated at the appropriate position as needed to obtain the required heat dissipation layer 41, and the exposed metal seed layer is removed by chemical etching.

[0062] In the first and second embodiments, in combination with Figures 6-7 As shown in

[0063] In combination with Figure 6 b, 7b, a colloidal layer is coated on one side of the first wafer 100 and is patterned to form a transition layer 110 and a through groove arranged at intervals. It can be understood that the transition layer 110 is located on the opposite side of the first wafer 100 from the heat dissipation layer 41 described above.

[0064] The metal support dam is formed by electroplating metal in the through slot, and the metal support dam includes the first metal support dam 31 and the second metal support dam 32. The first metal support dam 31 is located outside the first pad area 22, and the second metal support dam 32 is located in the first pad area 22. In other embodiments, more metal support dams can be made according to the needs.

[0065] After the transition layer 110 is removed, it can be understood that the metal seed layer located outside the metal support dam and the metal light-shielding layer 60 also needs to be removed, and the first transition layer 111 and the second transition layer 112 are removed. Figure 6 c, 7c.

[0066] In the third and fourth embodiments, the first transition layer 111 and the second transition layer 112 are removed. Figures 8-9 If the metal light-shielding layer 60 also needs to be made at the same time, two steps of electroplating metal need to be performed after the heat dissipation layer 41 is made, and the "making the second metal support dam 32" specifically includes:

[0067] The first transition layer 111 and the first through slot are formed by coating a glue layer on one side of the first wafer 100 for the first time and performing the first patterning.

[0068] The metal light-shielding layer 60 is formed by electroplating metal in the first through slot, and the metal light-shielding layer 60 is relatively thin and can be formed by sputtering, evaporation or peeling, and the first transition layer 111 and the second transition layer 112 are removed. Figure 8 b, 9b.

[0069] The second transition layer 112 and the second through slot are formed by coating a glue layer on one side of the metal light-shielding layer 60 for the second time and performing the second patterning.

[0070] The metal support dam is formed by electroplating metal in the second through slot, and the metal support dam includes the second metal support dam 32. The metal support dam can also include the first metal support dam 31, and the first transition layer 111 and the second transition layer 112 are removed. Figure 8 c, 9c.

[0071] The first transition layer 111 and the second transition layer 112 are removed, and the metal seed layer located outside the metal support dam and the metal light-shielding layer 60 also needs to be removed, and the first transition layer 111 and the second transition layer 112 are removed. Figure 8 d, 9d.

[0072] The first transition layer 111 and the second transition layer 112 are removed. Figure 10As shown, the "connecting the second metal support dam 32 and the first pad area 22" includes: connecting the second metal support dam and the first pad area by means of metal bonding or conductive adhesive bonding, the second metal support dam and the first pad area are electrically connected, the second metal support dam 32 should be formed into an intermittent ring structure; or connecting the second metal support dam 32 and the first pad area 22 by means of insulating adhesive bonding, the second metal support dam 32 and the first pad area 22 are insulatively connected, the second metal support dam can be selected as a continuous ring structure; or connecting the second metal support dam 32 and the first pad area 22 by means of medium-free bonding. The present case does not limit the specific bonding mode between the second metal support dam 32 and the first pad area 22, which can be selected according to actual needs.

[0073] In one embodiment, the dam structure 30 can only include the second metal support dam 32, or simultaneously include the first metal support dam 31, and only realize the sealing connection function through the metal support dam.

[0074] In one embodiment, the "connecting the second metal support dam 32 and the first pad area 22" includes: making an organic support dam 33 between the first wafer 100 and the second wafer 200. In one embodiment, in combination with Figure 10 As shown, in order to strengthen the support of the dam structure 30, an organic support dam 33 can also be made at the same time, the organic support dam 33 can be arranged outside the metal support dam, or can be arranged in a spaced manner with the metal support dam, and the position of the organic support dam 22 and the metal support dam can be adjusted as needed.

[0075] In specific embodiments, the dam structure 30 can be made on the surface of the first wafer 100.

[0076] In combination with Figure 10 As shown, the first wafer 100 and the second wafer 200 are connected by the dam structure 30, in other words, the first wafer 100 and the second wafer 200 are connected by the metal support dam and / or the organic support dam.

[0077] The wafer-level packaging method includes the steps of:

[0078] A metal bump 70 is made on the side of the second wafer 200 away from the first wafer 100, the metal bump 70 is connected to the first pad area 22, forming a wafer-level packaging structure.

[0079] The wafer-level packaging structure is cut to form a single chip structure 1000.

[0080] In combination with Figure 11As shown, the first pad area 22 is arranged on the side of the second wafer 200 facing the first wafer 100, and the second wafer 200 is provided with metal connecting columns on the side away from the first wafer 100, and the metal bump 70 is connected to the first pad area 22 through the metal connecting columns, and the metal bump 70 is welded to the circuit board 50 to realize the electrical connection between the chip structure 1000 and the circuit board 50.

[0081] In one embodiment, the wafer level packaging method comprises the steps of: Figure 12 As shown, the whole second wafer 200 should include a plurality of second pad areas 22, and the surface of the first wafer 100 can form a whole metal heat dissipation layer, and then the whole metal heat dissipation layer is divided into a plurality of different second pad areas 22, and the second pad area with large heat dissipation is divided into a larger area, and the second pad area with small heat dissipation is divided into a relatively small area.

[0082] In one embodiment, the wafer level packaging method comprises the steps of:

[0083] A heat dissipation module 42 is provided and connected to the heat dissipation layer 41 of the chip structure 1000. Figure 13 As shown, the heat dissipation module 42 is arranged on the side of the first wafer 100 away from the second wafer 200 and connected to the heat dissipation layer 41 to assist heat dissipation.

[0084] A circuit board 50 is provided, and the metal bump 70 of the chip structure 1000 is welded to the circuit board 50 to realize the connection of the chip structure 1000 to the outside.

[0085] The heat dissipation module 42 and the heat dissipation area of the circuit board 50 are connected. Figure 14 As shown, the heat dissipation module 42 is used for heat dissipation of the circuit board 50.

[0086] The beneficial effects of the utility model lie in that the heat dissipation column 40, the first pad area 22 and the second metal support dam 32 form an upward heat dissipation channel, and the heat dissipation capacity of the chip structure 1000 is strengthened, the heat dissipation layer 41 further increases the heat dissipation area and improves the heat dissipation performance, and the heat dissipation module 42 is additionally provided to assist heat dissipation.

[0087] Any of the technical solutions provided in the foregoing can be formed, and details are not repeated here.

[0088] It should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be combined appropriately to form other embodiments that can be understood by those skilled in the art.

[0089] The series of detailed descriptions listed above are only specific descriptions for the feasible implementation manners of the present application, and are not used to limit the protection scope of the present application. Any equivalent implementation manners or changes made without departing from the spirit of the present application should be included in the protection scope of the present application.

Claims

1. A chip structure, characterized by The application relates to a chip structure, comprising: a first base layer, a second base layer and a dam structure connecting the first base layer and the second base layer, the first base layer is provided with a through hole penetrating in the thickness direction of the first base layer, the second base layer comprises a first solder pad area, the chip structure comprises a heat dissipation column arranged in the through hole, and the dam structure comprises a second metal support dam for connecting the heat dissipation column and the first solder pad area.

2. The chip structure of claim 1, wherein, The second base layer has a functional surface and a functional area arranged on the functional surface, the first solder pad area is located outside the functional area, and the second metal support dam is arranged outside the functional area.

3. The chip structure of claim 2, wherein, The first base layer has a first surface facing the second base layer and a second surface away from the second base layer, the through hole penetrates the first surface and the second surface, the chip structure comprises a heat dissipation layer arranged on the second surface, and one end of the heat dissipation column away from the second metal support dam is connected to the heat dissipation layer.

4. The chip structure of claim 3, wherein, The area covered by the heat dissipation layer is opposite to the area outside the functional area.

5. The chip structure of claim 3, wherein, The area covered by the heat dissipation layer is opposite to the functional area and the first solder pad area.

6. The chip structure of claim 3, wherein, The chip structure comprises a heat dissipation module arranged on the heat dissipation layer.

7. The chip structure of claim 6, wherein, The chip structure comprises a circuit board arranged on the side of the second base layer away from the first base layer, the first solder pad area is connected to the circuit board, and the heat dissipation module is connected to the heat dissipation area of the circuit board.

8. The chip structure of claim 1, wherein, The dam structure comprises a first metal support dam located outside the second metal support dam, the first metal support dam is located outside the first solder pad area, and a gap is formed between the first metal support dam and the second metal support dam.

9. The chip structure of claim 2, wherein, The dam structure comprises an organic support dam located between the first base layer and the second base layer, and the organic support dam is located outside the functional area.

10. The chip structure of claim 2, wherein, The first base layer has a first surface facing the second base layer and a second surface away from the second base layer, the chip structure comprises a metal light shielding layer attached to the first surface, the metal light shielding layer is located outside the functional area, and the metal light shielding layer is thinner than the dam structure.

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