Gallium nitride semiconductor power device

Abstract

The utility model discloses a gallium nitride semiconductor power device, which comprises a gallium nitride substrate, a passivation layer, a dielectric lamination layer and an interlayer dielectric layer which are sequentially laminated, the dielectric stack comprises a first dielectric layer, a first etching barrier layer, a second dielectric layer, a second etching barrier layer and a third dielectric layer which are stacked from top to bottom, a first gate field plate is arranged between the first dielectric layer and the interlayer dielectric layer, and a second gate field plate is arranged between the second dielectric layer and the interlayer dielectric layer; a grid electrode is arranged between the passivation layer and the interlayer dielectric layer, an ohmic metal layer isolated from the grid electrode is arranged between the third dielectric layer and the passivation layer, and source electrodes electrically connected with the ohmic metal layer are arranged in the interlayer dielectric layer and the third dielectric layer.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor device, concretely relates to a gallium nitride semiconductor power device. BACKGROUND

[0002] Gallium nitride is a kind of wide band gap semiconductor material, has high efficiency, high frequency, low energy consumption and so on, it has wide application prospect in power electronic device field.Compared with traditional silicon power electronic device, gallium nitride power electronic device has higher working frequency and lower energy loss, can complete the same power conversion task in shorter time, to improve energy utilization efficiency.Therefore, in recent years, gallium nitride power electronic device has become the research hotspot in electronic power field.

[0003] The existing gallium nitride power device is usually in the process of making gate and gate field plate, that is, a layer of dielectric layer is made first, then the gate is made on the dielectric layer, then a layer of dielectric layer is made again, then the gate field plate is made on the dielectric layer, until the gate field plate is made.The existing manufacturing method has the problems of complex process, high cost, large volume of the prepared power device, etc., which affects the performance to a certain extent.Therefore, how to simplify the preparation process of the existing gallium nitride power device, reduce the cost, and make the gallium nitride power device with small volume has become a problem to be solved. SUMMARY

[0004] The utility model provides a kind of gallium nitride semiconductor power device for solving the problems such as complex process, high cost, large volume of the prepared device in the process of making the existing gallium nitride semiconductor power device.

[0005] To achieve the purpose of the utility model, the utility model provides a kind of gallium nitride semiconductor power device, wherein the power device includes gallium nitride substrate, passivation layer, dielectric stack and interlayer dielectric layer which are sequentially stacked, the dielectric stack includes first dielectric layer, first etching stop layer, second dielectric layer, second etching stop layer and third dielectric layer which are stacked from top to bottom, first gate field plate is provided between the first dielectric layer and the interlayer dielectric layer, second gate field plate is provided between the second dielectric layer and the interlayer dielectric layer, gate is provided between the passivation layer and the interlayer dielectric layer, ohmic metal layer is provided between the third dielectric layer and the passivation layer, and the ohmic metal layer is isolated from the gate, source electrode is provided in the interlayer dielectric layer and the third dielectric layer, and the source electrode is electrically connected to the ohmic metal layer.

[0006] The utility model has the advantages that:

[0007] The gallium nitride semiconductor power device of the utility model in the manufacturing process, the dielectric stack is made on the passivation layer, then the dielectric stack is etched according to the position of the gate and the gate field plate, to form the gate region and the gate field plate region, then the gate and the gate field plate are made in the gate region and the gate field plate region respectively, not only simplify the manufacturing process, but also can reduce the manufacturing cost.

[0008] On the other hand, when the gate and the gate field plate are prepared, the dielectric stack is etched at the same time, and the dielectric stack between the gate region and the source region is etched, and when the gate and the gate field plate are completed, the source contact hole is immediately prepared, so that only the interlayer dielectric layer and the third dielectric layer are around the source contact hole, not only the structure is simple, but also the quality of the prepared source contact hole is better.

[0009] In addition, since the first gate field plate and the second gate field plate are arranged on the side of the gate away from the source, the distance (Lgs) between the gate and the source can be reduced, the device volume is reduced, and the electric field distribution between the gate and the source is optimized. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 It is the method flow chart of the utility model embodiment 1.

[0011] Figure 2 It is the sectional view of the structure obtained after the utility model embodiment 1 executes step S10.

[0012] Figure 3 It is the sectional view of the structure obtained after the utility model embodiment 1 executes step S20.

[0013] Figure 4 It is the sectional view of the structure obtained after the utility model embodiment 1 executes step S30.

[0014] Figure 5 It is the sectional view of the structure obtained after the utility model embodiment 1 executes step S41.

[0015] Figure 6 It is the sectional view of the structure obtained after the utility model embodiment 1 executes step S42.

[0016] Figure 7 It is the sectional view of the structure obtained after the utility model embodiment 1 executes step S43.

[0017] Figure 8 It is the sectional view of the structure obtained after the utility model embodiment 1 executes step S51.

[0018] Figure 9 It is the sectional view of the structure obtained after the utility model embodiment 1 executes step S52.

[0019] Figure 10 is a sectional view of the structure obtained after step S53 of the embodiment 1 of the present application is executed.

[0020] Figure 11 is a sectional view of the structure obtained after step S61 of the embodiment 1 of the present application is executed.

[0021] Figure 12 is a sectional view of the structure obtained after step S62 of the embodiment 1 of the present application is executed.

[0022] Figure 13 is a sectional view of the structure obtained after step S63 of the embodiment 1 of the present application is executed.

[0023] Figure 14 is a sectional view of the structure obtained after step S70 of the embodiment 1 of the present application is executed.

[0024] Figure 15 is a sectional view of the structure obtained after step S80 of the embodiment 1 of the present application is executed.

[0025] Figure 16 is a sectional view of the structure obtained after the source contact hole is formed in step S90 of the embodiment 1 of the present application.

[0026] Figure 17 is a sectional view of the structure obtained after step S90 of the embodiment 1 of the present application is executed.

[0027] Figure 18 is a structure schematic view of the embodiment 2 of the present application.

[0028] In the figure, 10, substrate, 20, passivation layer, 30, ohmic metal layer, 40, dielectric stack, 41, first dielectric layer, 42, first etching stop layer, 43, second dielectric layer, 44, second etching stop layer, 45, third dielectric layer, 46, first photoresist layer, 47, second photoresist layer, 48, third photoresist layer, 50, first gate field plate, 60, second gate field plate, 70, gate, 80, interlayer dielectric layer, 90, source. DETAILED DESCRIPTION

[0029] The technical solutions of the present application will be described clearly and completely below in combination with the drawings and specific embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0030] As Figure 18As shown in the figure, the gallium nitride semiconductor power device of the embodiment comprises a gallium nitride substrate 10, a passivation layer 20, a dielectric stack 40 and an interlayer dielectric layer 80 which are sequentially stacked, an ohmic metal layer 30 and a gate 70 are arranged between the passivation layer 20 and the dielectric stack 40, and a gate field plate and a source 90 are arranged between the dielectric stack 40 and the interlayer dielectric layer 80. The gallium nitride semiconductor power device prepared in the embodiment is a D-type gallium nitride high electron mobility transistor, which can be used as a switching device or an amplifier device and other high-power application devices.

[0031] As shown in the figure, Figure 18 The substrate 10 is a gallium nitride substrate, and a passivation layer 20 is arranged on the upper surface of the substrate 10. The passivation layer 20 serves as a gate insulator to prevent gate leakage current. An ohmic metal layer 30 is formed on the source position of the passivation layer 20, which is used to electrically connect with the source 90. The cross section of the ohmic metal layer 30 is in the shape of "T", and the lower surface of the horizontal part is connected with the upper surface of the passivation layer 20, and the vertical part is arranged in the passivation layer 20.

[0032] As shown in the figure, Figure 18 A dielectric stack 40 is arranged on the passivation layer 20 and the ohmic metal layer 30, which is used to define electrodes and achieve electrical separation. The dielectric stack 40 comprises multiple dielectric layers and etching stop layers arranged between adjacent two dielectric layers. By arranging the etching stop layers, the thickness uniformity of the dielectric layers under the etching stop layers can be ensured. The thickness of each dielectric layer and etching stop layer can be set according to actual needs. A gate 70 and a gate field plate are arranged on the dielectric stack 40, an interlayer dielectric layer 80 is arranged on the gate 70 and the gate field plate, and a source 90 is arranged on the interlayer dielectric layer 80. The source is electrically connected with the ohmic metal layer 30.

[0033] Specifically, as shown in the figure, Figure 18In the illustrated embodiment, the dielectric stack 40 includes a first dielectric layer 41, a first etch stop layer 42, a second dielectric layer 43, a second etch stop layer 44, and a third dielectric layer 45 stacked from top to bottom. The gate field plate includes a first gate field plate 50 and a second gate field plate 60. The first gate field plate 50 is disposed on the first dielectric layer 41 on the side of the gate region away from the source region. The first gate field plate 50 has a rectangular cross-section, and its lower surface covers the upper surface of the first dielectric layer 41. The second gate field plate 60 is located on the second dielectric layer 43 on the side of the gate region away from the source region and is connected to the first gate field plate 50. The second gate field plate 60 has a rectangular cross-section, and its lower surface covers a portion of the upper surface of the second dielectric layer 43. Its side away from the source 90 is connected to the side of the first dielectric layer 41 and the side of the first etch stop layer 42. The gate 70 is located on the third dielectric layer 45, connected to the second gate field plate 60, and spaced apart from the ohmic metal layer 30. The gate 70 has a "T" shaped cross-section. The lower surface of its horizontal portion is connected to the upper surface of part of the third dielectric layer 45. The side of its horizontal portion away from the source 90 is connected to the side of the second dielectric layer 43 and the side of the second etch barrier layer 44, respectively. Its vertical portion passes through the third dielectric layer 45 and is connected to the passivation layer 20.

[0034] The first dielectric layer 41, the second dielectric layer 43, and the third dielectric layer 45 are made of silicon nitride, while the first etch barrier layer 42 and the second etch barrier layer 44 are made of aluminum nitride. Since the etching conditions of silicon nitride and aluminum nitride are different, etching silicon nitride can better ensure the thickness uniformity of the underlying aluminum nitride layer, and similarly, etching aluminum nitride can better ensure the thickness uniformity of the underlying silicon nitride layer.

[0035] like Figure 18 As shown, an interlayer dielectric layer 80 is provided on the gate field plate and the gate 70. This interlayer dielectric layer 80 covers the upper surface and the side near the source of the first gate field plate 50, the upper surface and the side near the source of the second gate field plate 60, the upper surface and the side near the source of the horizontal portion of the gate 70, and a portion of the upper surface of the third dielectric layer 45. A source contact hole is provided at the source position of the third dielectric layer 45, extending from the upper surface of the interlayer dielectric layer 80 to the lower surface of the third dielectric layer 45. A source electrode 90 is provided within the source contact hole and is electrically connected to the ohmic metal layer 30. The source electrode 90 has a "T"-shaped cross-section; the lower surface of its horizontal portion connects to the upper surface of a portion of the interlayer dielectric layer 80, and its vertical portion is located within the source contact hole, allowing the vertical portion of the source electrode 90 to sequentially pass through the interlayer dielectric layer 80 and the third dielectric layer 45 and connect to the ohmic metal layer 30.

[0036] like Figure 18As shown, the first gate field plate 50 and the second gate field plate 60 of the embodiment are arranged on the side of the gate region away from the source region, and no gate field plate is arranged on the side of the gate region and the source region, so that the distance between the gate and the source can be reduced, the volume of the device can be reduced, and the electric field distribution between the gate and the source can be optimized. On the other hand, since only the interlayer dielectric layer 80 and the third dielectric layer 45 are arranged around the source contact hole, the structure around the source contact hole is simple, and the quality of the source contact hole prepared is better.

[0037] The specific manufacturing process of the gallium nitride semiconductor power device of the embodiment will be described in detail below.

[0038] As shown in Figure 1 , the gallium nitride semiconductor power device prepared in the embodiment includes but is not limited to MIS-HEMT device, P-GaN HEMT device, and SBD-Gate HEMT device, which can be a D-type gallium nitride high electron mobility transistor, which can be used as a switching device or an amplifier device, etc. high-power application device.

[0039] Specifically, as shown in Figure 1 , the manufacturing method of the gallium nitride semiconductor power device of the embodiment includes the following steps:

[0040] S10, providing a substrate 10, and growing a passivation layer 20 on the substrate 10.

[0041] In this step, as shown in Figure 2 , the substrate 10 is a gallium nitride substrate, and the passivation layer 20 is deposited on the substrate 10 by a method of metal organic chemical vapor deposition (MOCVD) or plasma enhanced chemical vapor deposition (PECVD). The passivation layer 20 is made of silicon nitride or silicon dioxide material, which acts as a gate insulator to prevent gate leakage current.

[0042] S20, preparing an ohmic metal layer 30.

[0043] In this step, as shown in Figure 3 , the ohmic metal layer 30 is formed at the source position on the passivation layer 20. The ohmic metal layer 30 is formed at the source position on the passivation layer 20 by metal deposition, and the material of the ohmic metal layer 30 can be titanium, aluminum, titanium nitride alloy, etc., which is used for electrical connection with the source 90.

[0044] S30, preparing a dielectric layer 40.

[0045] In this step, as shown in Figure 4As shown, a dielectric stack 40 is formed on the passivation layer 20 and the ohmic metal layer 30 to define the electrodes and achieve electrical separation. The dielectric stack 40 can be formed on the passivation layer 20 and the ohmic metal layer 30 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition methods. This dielectric stack 40 includes multiple dielectric layers and etch barrier layers disposed between adjacent dielectric layers. By setting the etch barrier layers, it is ensured that etching the upper dielectric layer does not affect the lower dielectric layer, thereby ensuring the thickness uniformity of the same dielectric layer. The thickness of each dielectric layer and the etch barrier layer can be set according to actual needs. Figure 4 In the illustrated embodiment, the dielectric stack 40 includes a first dielectric layer 41, a first etch stop layer 42, a second dielectric layer 43, a second etch stop layer 44, and a third dielectric layer 45 stacked from top to bottom. Specifically, the first dielectric layer 41, the second dielectric layer 43, and the third dielectric layer 45 are made of silicon nitride. In this embodiment, the first dielectric layer 41, the second dielectric layer 43, and the third dielectric layer 45 are made of silicon nitride. The first etch stop layer 42 and the second etch stop layer 44 are made of aluminum nitride, which are used to ensure the uniformity of the thickness of the second dielectric layer 43 and the third dielectric layer 45, respectively.

[0046] S40, forming the first gate field plate region.

[0047] In this step, such as Figure 5 , Figure 6 and Figure 7 As shown, a first gate field plate region is formed on the first dielectric layer 41, and the first gate field plate region is located on the side of the gate region away from the source region.

[0048] Specifically, the steps include:

[0049] S41, Form the first photoresist layer 46.

[0050] like Figure 5 As shown, in order to retain the first dielectric layer 41 located in the first gate field plate region, a first photoresist layer 46 can be filled at the first gate field plate location so that the first photoresist layer 46 covers the surface of the first dielectric layer 41 located in the first gate field plate region.

[0051] S42, Etch the first dielectric layer 41 and the first etch barrier layer 42.

[0052] like Figure 6As shown, the first dielectric layer 41 in the non-first gate field plate region is etched. After etching the first dielectric layer 41, the first etch barrier layer 42 in the non-first gate field plate region is then etched. Since the surface of the first dielectric layer 41 in the first gate field plate region is covered by the first photoresist layer 46, it is retained. The etching of the first dielectric layer 41 can be performed using a dry etching method or a wet etching method. The etching method of the first etch barrier layer 42 is different from that of the first dielectric layer 41. That is, etching the first dielectric layer 41 will not affect the underlying first etch barrier layer 42. Similarly, etching the first etch barrier layer 42 will not affect the underlying second dielectric layer 43. This can effectively control the etching depth and avoid affecting the thickness uniformity of the second dielectric layer 43.

[0053] S43, Remove the first photoresist layer 46.

[0054] like Figure 7 As shown, after etching the first dielectric layer 41 and the first etch barrier layer 42 in the non-first gate field plate region, the first photoresist layer 46 is removed to form the first gate field plate region. The removal of the first photoresist layer 46 can be performed using either dry etching or wet etching methods.

[0055] S50, forming the second gate field plate region.

[0056] In this step, such as Figure 8 , Figure 9 and Figure 10 As shown, a second gate field plate region is formed on the second dielectric layer 43, and the second gate field plate region is located on the side of the first gate field plate region away from the source region.

[0057] Specifically, the steps include:

[0058] S51, Form the second photoresist layer 47.

[0059] like Figure 8 As shown, in order to retain the second dielectric layer 43 located in the second gate field plate region and the first gate field plate region, a second photoresist layer 47 can be filled on the second dielectric layer 43 at the second gate field plate location and the first gate field plate region, so that the second photoresist layer 47 covers the surface of the first dielectric layer 41 located in the first gate field plate region and the surface of the second dielectric layer 43 located in the second gate field plate region.

[0060] S52, Etch the second dielectric layer 43 and the second etching barrier layer 44.

[0061] like Figure 9As shown, the second dielectric layer 43 in the non-second gate field plate region is etched. After etching the second dielectric layer 43, the second etch barrier layer 44 in the non-second gate field plate region is then etched. Since the surfaces of the second dielectric layer 43 in the first gate field plate region and the second gate field plate region are covered by the second photoresist layer 47, they are preserved. The etching of the second dielectric layer 43 can be performed using either a dry etching method or a wet etching method. The etching method for the second etch barrier layer 44 differs from that for the second dielectric layer 43; that is, etching the second dielectric layer 43 does not affect the underlying second etch barrier layer 44. Similarly, etching the second etch barrier layer 44 does not affect the underlying third dielectric layer 45. This effectively controls the etching depth and avoids affecting the thickness uniformity of the third dielectric layer 45.

[0062] S53, Remove the second photoresist layer 47.

[0063] like Figure 10 As shown, after etching the second dielectric layer 43 and the second etch barrier layer 44, the second photoresist layer 47 is removed to form the second gate field plate region. The removal of the second photoresist layer 47 can be performed using either dry etching or wet etching methods.

[0064] S60, forming the gate region.

[0065] In this step, such as Figure 11 , Figure 12 and Figure 13 As shown, a gate region is formed on the third dielectric layer 45.

[0066] Specifically, the steps include:

[0067] S61, Form the third photoresist layer 48.

[0068] like Figure 11 As shown, in order to etch the third dielectric layer 45 located at the gate position, a third photoresist layer 48 can be formed at the non-gate position to retain the dielectric layer at the non-gate position.

[0069] S62, Etch the third dielectric layer 45.

[0070] like Figure 12 As shown, the third dielectric layer 45 at the gate location is etched to form the gate region. The etching of the third dielectric layer 45 can be performed using either a dry etching method or a wet etching method.

[0071] S63, Remove the third photoresist layer 48.

[0072] like Figure 13As shown, after etching the third dielectric layer 45, the third photoresist layer 48 is removed, exposing the first gate field plate region, the second gate field plate region, the gate region, and the third dielectric layer 45 between the gate and the source. The removal of the third photoresist layer 48 can be performed using either dry etching or wet etching methods.

[0073] S70. Prepare the first gate field plate 50, the second gate field plate 60, and the gate 70.

[0074] In this step, such as Figure 14 As shown, a first gate field plate, a second gate field plate, and a gate are formed in a first gate field plate region, a second gate field plate region, and a gate region, respectively. Specifically, metal layers are deposited on the surfaces of a first dielectric layer 41 in the first gate field plate region, a second dielectric layer 43 in the second gate field plate region, a third dielectric layer 45 in the gate region, and a third dielectric layer 45 between the gate and the source. Metal etching is then performed on the metal layers in the first gate field plate region, the second gate field plate region, and the regions outside the gate region to form a first gate field plate 50, a second gate field plate 60, and a gate 70. In this embodiment, the first gate field plate 50 and the second gate field plate 60 are located on the side of the gate 70 away from the source 90, and the second gate field plate 60 and the first gate field plate 50 are stepped field plates extending upwards towards the side away from the source 90. The second gate field plate 60 is connected to both the first gate field plate 50 and the gate 70. The materials of the first gate field plate 50, the second gate field plate 60, and the gate 70 include, but are not limited to, Al, Ti, and TiN.

[0075] S80, Prepare interlayer dielectric layer 80.

[0076] In this step, such as Figure 15 As shown, an interlayer dielectric layer 80 is formed on the upper surfaces of the first gate field plate 50, the second gate field plate 60, the gate 70, and the third dielectric layer 45 extending from the gate region to the source region. This interlayer dielectric layer 80 can be formed using chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0077] S90, preparation of source electrode 90.

[0078] In this step, such as Figure 16 , Figure 17As shown, the source contact hole is made on the interlayer dielectric layer 80 and the third dielectric layer 45 at the source position, and the source 90 is formed in the contact hole and electrically connected with the ohmic metal layer 30. Specifically, the interlayer dielectric layer 80 and the third dielectric layer 45 at the source position are etched respectively to make the source contact hole at the source position, and the source 90 is formed in the contact hole. The interlayer dielectric layer 80 and the third dielectric layer 45 at the source position are removed by dry etching or wet etching. The source 90 can be made by metal evaporation such as magnetron sputtering, electron beam evaporation and thermal evaporation.

[0079] In the manufacturing process of the gallium nitride semiconductor power device of the embodiment, the dielectric stack 40 is first made on the passivation layer 20, then the first dielectric layer 41 is etched according to the position of the first gate field plate 50, the second dielectric layer 43 is etched according to the position of the second gate field plate 60, and the third dielectric layer 45 is etched according to the position of the gate 70, and the first gate field plate 50, the second gate field plate 60 and the gate 70 are arranged at the first gate field plate position, the second gate field plate position and the gate position respectively, which not only simplifies the manufacturing process of the gate and the gate field plate, but also reduces the manufacturing cost.

[0080] On the other hand, when the first gate field plate 50, the second gate field plate 60 and the gate 70 are prepared, the dielectric stack is etched synchronously from the gate area to the source area while the dielectric stack is etched, and the source contact hole is made immediately after the first gate field plate 50, the second gate field plate 60 and the gate 70 are made, so that only the interlayer dielectric layer 80 and the third dielectric layer 45 are around the source contact hole, which not only has a simple structure, but also has a better quality of the source contact hole.

[0081] In addition, since the first gate field plate 50 and the second gate field plate 60 are arranged on the side of the gate away from the source, and no gate field plate is arranged between the gate 70 and the source 90, the distance between the gate and the source can be reduced, the size of the device can be reduced, and the electric field distribution between the gate and the source can be optimized.

[0082] Although the utility model is disclosed through the above embodiment, the protection scope of the utility model is not limited to this, and the deformation, replacement and the like of the above components without deviating from the concept of the utility model will fall within the scope of the claims of the utility model.

Claims

1. A gallium nitride semiconductor power device, characterized in that, The power device includes a gallium nitride substrate, a passivation layer, a dielectric stack, and an interlayer dielectric layer stacked sequentially. The dielectric stack includes a first dielectric layer, a first etch stop layer, a second dielectric layer, a second etch stop layer, and a third dielectric layer stacked from top to bottom. A first gate field plate is provided between the first dielectric layer and the interlayer dielectric layer, a second gate field plate is provided between the second dielectric layer and the interlayer dielectric layer, a gate is provided between the passivation layer and the interlayer dielectric layer, and an ohmic metal layer isolated from the gate is provided between the third dielectric layer and the passivation layer. A source electrode electrically connected to the ohmic metal layer is provided within the interlayer dielectric layer and the third dielectric layer.

2. The gallium nitride semiconductor power device as described in claim 1, characterized in that, The first gate field plate and the second gate field plate are disposed on the side of the gate away from the source, and the second gate field plate and the first gate field plate are stepped field plates that extend upwards in stages away from the source. The second gate field plate is connected to the first gate field plate and the gate, respectively.

3. The gallium nitride semiconductor power device as described in claim 2, characterized in that, The first gate field plate has a rectangular cross-section, with its upper surface and side portions connected to a portion of the interlayer dielectric layer, and its lower surface connected to the upper surface of the first dielectric layer. The second gate field plate has a rectangular cross-section. Its upper surface and the side near the source are connected to a portion of the interlayer dielectric layer, its lower surface is connected to a portion of the upper surface of the second dielectric layer, and its other side is connected to the side of the first dielectric layer and the side of the first etch barrier layer. The gate has a "T" shaped cross-section. The upper surface of its horizontal portion and the side near the source are connected to a portion of the interlayer dielectric layer, the lower surface of its horizontal portion is connected to a portion of the upper surface of the third dielectric layer, the other side of its horizontal portion is connected to the side of the second dielectric layer and the side of the second etch barrier layer, and its vertical portion passes through the third dielectric layer and is connected to the passivation layer.

4. The gallium nitride semiconductor power device as described in claim 1, characterized in that, The cross-section of the ohmic metal layer is "T" shaped, the lower surface of the horizontal portion of the ohmic metal layer is connected to the upper surface of the passivation layer, and the vertical portion of the ohmic metal layer is disposed within the passivation layer.

5. The gallium nitride semiconductor power device as described in claim 1, characterized in that, The interlayer dielectric layer covers the upper surface of the first gate field plate and the side near the source, covers the upper surface of the second gate field plate and the side near the source, covers the upper surface of the horizontal portion of the gate and the side near the source, and covers part of the upper surface of the third dielectric layer.

6. The gallium nitride semiconductor power device as described in claim 5, characterized in that, A source contact hole is provided at the source position of the third dielectric layer, and the source contact hole extends from the upper surface of the interlayer dielectric layer to the lower surface of the third dielectric layer; the source is provided in the source contact hole, and the source is electrically connected to the ohmic metal layer.

7. The gallium nitride semiconductor power device as described in claim 6, characterized in that, The source electrode has a "T" shaped cross-section. The lower surface of the horizontal portion of the source electrode is connected to the upper surface of part of the interlayer dielectric layer. The vertical portion of the source electrode is disposed in the source electrode contact hole, so that the vertical portion of the source electrode passes through the interlayer dielectric layer and the third dielectric layer in sequence and is connected to the ohmic metal layer.

8. The gallium nitride semiconductor power device as described in claim 1, characterized in that, The first dielectric layer, the second dielectric layer, and the third dielectric layer are made of silicon nitride.

9. The gallium nitride semiconductor power device as described in claim 1, characterized in that, Both the first and second etching barrier layers are made of aluminum nitride.

10. The gallium nitride semiconductor power device as described in claim 1, characterized in that, The semiconductor power devices include, but are not limited to, MIS-HEMT devices, P-GaN HEMT devices, and SBD-Gate HEMT devices.

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