Impedance element calibration clamp for reducing parasitic capacitance of PCB (Printed Circuit Board)

Abstract

The utility model belongs to the technical field of integrated circuit and semiconductor manufacturing, and particularly relates to an impedance element calibration clamp capable of reducing PCB parasitic capacitance, which comprises a PCB, a limiting hole, an element bonding pad, a test point bonding pad and the like. The calibration fixture is designed to be placed on the front and back surfaces, and the element bonding pad and the test point bonding pad both adopt a through hole form and penetrate through the front and back surfaces of the PCB, so that the flexibility and universality of the fixture are improved. The side wall of each through hole is provided with a conductive layer which can be used as a welding point and a testing point, so that tin contact is ensured to be sufficient and uniform, and the stability and accuracy of welding and testing are improved. According to the clamp, the limitation of a traditional calibration clamp in the aspects of space limitation, poor welding contact and high-frequency signal calibration is solved, the clamp is suitable for calibration of various impedance elements, and the calibration efficiency and reliability are improved.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit and semiconductor manufacturing technology, specifically relating to an impedance component calibration fixture for reducing PCB parasitic capacitance. Background Technology

[0002] In the electronics industry, the calibration of impedance components is a critical step in ensuring stable and accurate circuit performance. Traditional calibration fixture designs typically rely on specific pad layouts on the PCB board to achieve electrical connections with the impedance components. These pads are usually located on the surface of the PCB board and connected to external test equipment via wires or soldering. Furthermore, for precise calibration, test points are usually also located on the PCB board for signal measurement via test probes. However, with the continuous development of electronic technology, the requirements for calibration fixtures are becoming increasingly stringent.

[0003] While traditional calibration fixtures meet the calibration requirements of impedance components to some extent, they have some significant drawbacks. First, because the pads and test points are located on the surface of the PCB, this limits the flexibility and applicability of the calibration fixtures. Especially in space-constrained applications or those requiring high integration, traditional calibration fixtures often fall short. Second, existing calibration fixtures may experience poor solder contact or unstable signal transmission during soldering and testing, affecting the accuracy and reliability of the calibration. Furthermore, due to the parasitic capacitance effect on the PCB, traditional calibration fixtures also have limitations in high-frequency signal calibration. Utility Model Content

[0004] The purpose of this invention is to provide a highly flexible, stable, and reliable impedance component calibration fixture for reducing PCB parasitic capacitance and accurately calibrating impedance components.

[0005] This utility model achieves the above objectives through the following technical solutions:

[0006] This utility model proposes a calibration fixture for impedance components to reduce parasitic capacitance on PCBs, comprising:

[0007] PCB board, the PCB board having at least one calibration surface;

[0008] A limiting hole, which extends through the PCB board, is used for embedding resistive components;

[0009] The calibration surface is provided with two element pads, both of which have a welding point near the end of the limiting hole and a measuring point pad one and a measuring point pad two respectively away from the end of the limiting hole; wherein the welding point is used for connecting with the impedance element, the measuring point pad one is used for receiving an external excitation signal, and the measuring point pad two is used for outputting a measuring signal.

[0010] Further, the PCB board has two calibration surfaces, which are respectively located on the front surface and the back surface of the PCB board.

[0011] Further, the element pad, the measuring point pad one and the measuring point pad two are all in the form of through holes, which penetrate the front surface and the back surface of the PCB board.

[0012] Further, the welding point is in the form of a through hole, which is used for welding connection with the corresponding terminal of the impedance element.

[0013] Further, during calibration, the measuring point pad one and the measuring point pad two located on the front surface or the back surface of the PCB board are connected with an external excitation signal source and a signal receiving device through a test probe, so as to realize signal output data transmission and measurement.

[0014] Further, each through hole has a conductive layer on the side wall, which is used as a welding point for electrical connection with the impedance element and / or as a test point for signal measurement through a test probe.

[0015] Further, the element pad, the measuring point pad one and the measuring point pad two and the internal conductive layer thereof located on the front surface and the back surface of the PCB board are not parallel.

[0016] The beneficial effects of the utility model lie in:

[0017] 1. The calibration clamp can be placed on the front surface or the back surface, which significantly improves flexibility and applicability. The clamp allows the impedance element to be embedded from the front surface or the back surface of the PCB board, thereby solving the limitations of traditional calibration clamps in space-limited or high-integration application scenarios. In addition, the element pad and the test point are in the form of through holes and penetrate the front surface and the back surface of the PCB board, which further enhances the versatility and compatibility of the clamp. This design enables the present application to be more widely applied to calibration of various types of impedance elements, improving calibration efficiency and accuracy.

[0018] 2.The application also significantly improves the stability and reliability in the welding and testing process by optimizing the structure of the pads and test points. Each via is provided with a bare copper layer on the sidewall, which can be used as a welding point for electrical connection with the impedance element and as a test point for signal measurement through a test probe. This design ensures the sufficiency and uniformity of the tin contact, thereby avoiding the tin contact problem that may exist in the traditional calibration fixture. At the same time, since the copper layer is directly exposed on the sidewall of the via, the signal transmission is more stable, the influence of the parasitic capacitance effect on the high-frequency signal calibration is reduced, and the accuracy and reliability of the calibration are improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is the overall front structure schematic diagram of the impedance element calibration fixture for reducing PCB parasitic capacitance provided by the application;

[0020] Figure 2 is the overall front structure schematic diagram of the impedance element calibration fixture for reducing PCB parasitic capacitance provided by the application, which contains a to-be-tested element;

[0021] Figure 3 is the overall back structure schematic diagram of the impedance element calibration fixture for reducing PCB parasitic capacitance provided by the application, which contains a to-be-tested element;

[0022] Figure 4 is a structure schematic diagram of the PCB in the impedance element calibration fixture for reducing PCB parasitic capacitance provided by the application.

[0023] In the figure: 1, PCB; 2, limiting hole; 3, element pad; 4, test point pad one; 5, test point pad two; 6, welding point; 7, impedance element. DETAILED DESCRIPTION

[0024] It is necessary to point out here that the following detailed description is only used to further illustrate the application, and cannot be understood as limiting the protection scope of the application. Those skilled in the art can make some non-essential improvements and adjustments to the application according to the above application content.

[0025] Example 1

[0026] As Figures 1-4As shown, the present embodiment proposes an impedance element calibration fixture for reducing PCB parasitic capacitance, comprising: a PCB board 1, a limiting hole 2, an element pad 3, a measurement point pad one 4 and a measurement point pad two 5, the PCB board 1 has at least one calibration surface; the limiting hole 2 penetrates the PCB board 1, and can be specifically provided at the center of the PCB board 1, for embedding the impedance element 7, and can be specifically mechanically cut at the center of the PCB board 1 to form the limiting hole 2; the calibration surface is provided with two element pads 3, both of which have a welding point 6 at the end close to the limiting hole 2, and have the measurement point pad one 4 and the measurement point pad two 5 at the end away from the limiting hole 2; wherein the welding point 6 is used for connecting with the impedance element 7, the measurement point pad one 4 is used for receiving an external excitation signal, and the measurement point pad two 5 is used for outputting a measurement signal.

[0027] It can be understood that the impedance element 7 in the present embodiment can be a resistor, a capacitor, an inductor or the like which needs to be calibrated or tested.

[0028] Optionally, in combination with Figure 1 and Figure 2 , the limiting hole 2 in the present embodiment can be designed as a rectangular hole for embedding the impedance element 7 during calibration or testing.

[0029] In addition, the embedded installation mode of the impedance element 7 in the present application makes the tin contact more sufficient and uniform, and can realize front and back testing without additional via lead.

[0030] Optionally, the PCB board 1 has two calibration surfaces, specifically the front surface and the back surface of the PCB board 1 (specifically see Figure 2 and Figure 3 , wherein TOP represents the front surface of the PCB board 1, and BOT represents the back surface of the PCB board 1).

[0031] In some preferred embodiments, the PCB board 1 is specifically a double-layer PCB structure, comprising a front surface and a back surface, and further has the following characteristics:

[0032] As preferred, the element pad 3, the measurement point pad one 4 and the measurement point pad two 5 all adopt a through-hole form, and the through-hole penetrates the front surface and the back surface of the PCB board 1. These through-holes completely penetrate the front surface and the back surface of the PCB board 1; this design not only improves the adaptability of the fixture to different sizes and types of impedance elements, but also increases the flexibility of the layout.

[0033] As preferred, the welding point 6 adopts a through-hole form, and is used for welding connection with the corresponding terminal of the impedance element 7; this design ensures the sufficiency and stability of the welding contact, thereby significantly improving the welding quality.

[0034] As preferred, during the calibration process, the test point pad one 4 and the test point pad two 5 on the front or back of the PCB board 1 are connected with the external excitation signal source and the signal receiving device through the test probe. This connection mode realizes reliable transmission and accurate measurement of signal data, thereby ensuring the smooth completion of the impedance calibration process.

[0035] For example, the test point pad one 4 is used to connect the excitation signal source to provide the required excitation signal for the impedance element 7; the test point pad two 5 is used to connect the signal receiving device to receive and measure the response signal output from the impedance element 7; the excitation signal source and the signal receiving device are synchronously controlled and data collected by the test system controller to realize accurate calibration and testing of the impedance element.

[0036] As preferred, each through hole has a conductive layer (such as a bare copper layer) on the sidewall, which serves as a soldering point for electrical connection with the impedance element 7 and / or as a test point for signal measurement through the test probe.

[0037] As preferred, as shown in Figure 1 The element pad 3, the test point pad one 4 and the test point pad two 5 on the front and back of the PCB board 1 and their internal conductive layers are not parallel, specifically, the internal conductive layers of these pads are not parallel in layout or direction, and the internal conductive layers are arranged at different angles or directions on the front and back of the PCB board to form a non-parallel structure; this non-parallel design is to further optimize the performance of the clamp, such as reducing the influence of parasitic capacitance.

[0038] As preferred, the calibration clamp can be placed front or back, and the impedance element 7 can be inserted into the limiting hole 2 from the front or back of the PCB board 1.

[0039] According to the above-mentioned calibration clamp, in use, the following procedures or stages are included:

[0040] (1) Preparation stage: First, place the calibration clamp on a suitable workbench to ensure the stability and fixation of the clamp. Then, according to the type and size of the impedance element 7, select the appropriate embedding method and the position of the soldering point 6.

[0041] (2) Embedding and soldering: insert the impedance element 7 into the PCB board 1 through the limiting hole 2 and ensure that the terminals of the element are aligned with the soldering points 6. Then, use the soldering tool to solder the terminals of the element with the soldering points 6. During the soldering process, pay attention to maintain the sufficiency and stability of the soldering to avoid problems such as poor soldering or unstable signal transmission.

[0042] (3) Calibration test: During the calibration process, the test probe is used to contact test point pad one 4 and test point pad two 5 respectively, and is connected with the external excitation signal source and signal receiving device. Then, according to the calibration requirements, the excitation signal is applied to the impedance element 7, and the output signal is received and measured by the signal receiving device. By comparing the input and output signals, the impedance value of the impedance element can be calculated, thereby completing the calibration process.

[0043] (4) Data processing and analysis: After the calibration test is completed, the measurement data is processed and analyzed. According to the analysis results, it can be judged whether the impedance element meets the expected requirements, and necessary adjustment and optimization are carried out.

[0044] According to the above embodiment, the calibration fixture adopts a double-layer PCB structure design, the element pad, the test point pad and the welding point all adopt the through-hole form penetrating the front and back surfaces, and are provided with exposed copper layers to enhance the electrical connection stability and test accuracy. The calibration fixture can be placed flexibly on the front and back surfaces, and is suitable for different test requirements. The technical advantages are as follows: 1. The universality and flexibility of the fixture are improved, and it is suitable for calibration of various impedance elements; 2. Through the through-hole design and exposed copper layer, the sufficiency and stability of welding, and the accuracy and reliability of test are ensured; 3. The calibration process is simplified, the calibration efficiency is improved, and the calibration cost is reduced; 4. The structure is compact, easy to store and carry, and convenient for popularization and use in practical application.

[0045] Although the embodiments of the utility model have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and spirits of the utility model, the scope of the utility model is defined by the appended claims and their equivalents.

Claims

1. A calibration fixture for impedance components that reduces parasitic capacitance on PCBs, characterized in that, include: PCB board (1), the PCB board (1) having at least one calibration surface; A limiting hole (2) extends through the PCB board (1) and is used for embedding an impedance element (7); The calibration surface is provided with two component pads (3). The ends of the two component pads (3) near the limiting hole (2) each have a solder point (6), and the ends away from the limiting hole (2) have a measuring point pad one (4) and a measuring point pad two (5), respectively. The solder point (6) is used to connect with the impedance element (7), the measuring point pad one (4) is used to receive external excitation signals, and the measuring point pad two (5) is used to output measurement signals.

2. The impedance component calibration fixture for reducing PCB parasitic capacitance according to claim 1, characterized in that, The PCB board (1) has two calibration surfaces, located on the front and back sides of the PCB board (1) respectively.

3. The impedance component calibration fixture for reducing PCB parasitic capacitance according to claim 2, characterized in that, The component pad (3), the first test pad (4), and the second test pad (5) are all in the form of through holes, which penetrate the front and back of the PCB board (1).

4. The impedance component calibration fixture for reducing PCB parasitic capacitance according to claim 3, characterized in that, The welding point (6) is in the form of a through hole, which is used to weld to the corresponding terminal of the impedance element (7).

5. The impedance component calibration fixture for reducing PCB parasitic capacitance according to claim 2, characterized in that, During calibration, the test pad 1 (4) and the test pad 2 (5) located on the front or back of the PCB board (1) are connected to the external excitation signal source and signal receiving device through test probes to realize signal output data transmission and measurement.

6. The impedance component calibration fixture for reducing PCB parasitic capacitance according to claim 4, characterized in that, Each of the vias has a conductive layer on its sidewall, which serves as a solder point for electrical connection to the impedance element (7) and / or as a test point for signal measurement via a test probe.

7. The impedance component calibration fixture for reducing PCB parasitic capacitance according to claim 6, characterized in that, The component pads (3), the first test pad (4), and the second test pad (5) located on the front and back sides of the PCB board (1) and their internal conductive layers are not parallel.

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