Current mirror circuit for wide power supply voltage domain and radio frequency front-end chip
By adjusting the width-to-length ratio of the transistors in the current mirror circuit, the third and fourth transistors are made to operate in the linear region, thus solving the problem of limited power supply voltage domain and enabling effective operation of the current mirror and improved output impedance under low power supply voltage.
Patent Information
- Application Number
- CN202520064341.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-13
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2035-01-13
AI Technical Summary
Existing current mirror circuits have limited application in the power supply voltage domain, cannot be used in low power supply voltages, and have low output impedance and inaccurate current replication.
A novel current mirror circuit structure is adopted, in which the third and fourth transistors operate in the linear region, and the first and second transistors operate in the saturation region. By adjusting the width-to-length ratio of the transistors, the output impedance is improved and accurate current replication is achieved.
It enables efficient operation of the current mirror under low power supply voltage, improves output impedance and ensures accurate current replication, and is suitable for RF front-end chips with a wide power supply voltage range.
Smart Images
Figure CN223598170U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of current mirror technology, specifically to a current mirror circuit and radio frequency front-end chip for a wide power supply voltage domain. Background Technology
[0002] The radio frequency (RF) front-end chip is a component between the antenna and the digital baseband system. It is a core component of wireless communication equipment and includes modules such as power amplifiers, RF switches, RF filters, and low-noise amplifiers.
[0003] In practical applications, RF front-end chips need to operate within a wide power supply voltage range of 1.6-5V. Internally, they require a current source and a current mirror, with the current mirror needing to accurately replicate the reference current generated by the current source. A good current mirror requires important characteristics such as large output swing, high output impedance, and high precision.
[0004] Existing basic current mirror application circuits, such as Figure 1 As shown, MOSFETs M1 and M2 are guaranteed. MOSFET M1 converts the input current Iref into voltage, and MOSFET M2 converts the converted voltage back into current for output. If the width-to-length ratio of MOSFET M2 is B times that of MOSFET M1, then the output current of MOSFET M2 is B times the input current Iref.
[0005] In practical applications, considering that the VDS (the voltage difference between the drain and source of the MOSFET) of MOSFETs M1 and M2 are not the same, the ratio of the output current of MOSFET M2 to the input current Iref is not precisely B. This problem can be alleviated by appropriately increasing the channel length L, i.e., increasing the output impedance of the MOSFET, making the curve of IDS versus VDS flatter in the saturation region. However, this structure has drawbacks such as low output impedance and inaccurate current replication.
[0006] To ensure that the VDS of MOSFETs M1 and M2 are the same, the following can be used: Figure 2 The conventional cascode current mirror shown is... Figure 2 The current mirror only needs to ensure that the width-to-length ratio of MOSFET M1 and MOSFET M2 is the same as the width-to-length ratio of MOSFET M3 and MOSFET M4.
[0007] in addition Figure 2In this configuration, MOSFET M2 can be considered a common-source amplifier, and MOSFET M4 can be considered a common-gate amplifier. MOSFETs M2 and M4 are connected together to form a common-source, common-gate structure. The output impedance of the common-source, common-gate structure, viewed from point Y, is approximately gm4*ro4*ro2, where gm4 is the transconductance of MOSFET M4, ro4 is the small-signal output impedance of MOSFET M4, and ro2 is the small-signal output impedance of MOSFET M2. The common-source, common-gate structure is equivalent to amplifying the output impedance of MOSFET M2 by gm*ro times. When there is voltage fluctuation at point Y, the voltage at point X is almost unaffected, always maintaining VDS1=VDS2, thus achieving accurate current replication.
[0008] for Figure 2 The main problem with the circuit shown in practical use is the voltage swing. The minimum voltage at point Y, VYmin = VGS2 + VGS4 - VTH4 = 2 * VOD + VTH, significantly reduces the output swing. Here, VGS2 is the gate-source voltage difference of MOSFET M2, VGS4 is the gate-source voltage difference of MOSFET M4, VTH4 is the threshold voltage of MOSFET M4, and VOD = VGS - VTH is the overdrive voltage of the MOSFET. Furthermore, MOSFETs M1 and M3 are two diodes connected in series. When VTH = 0.8V, the circuit cannot operate at VDD = 1.6V. In this case, VDD is limited in low power supply voltage applications and cannot meet the voltage requirements of RF front-end chips. Utility Model Content
[0009] In view of the shortcomings of the prior art, the present invention provides a current mirror circuit and RF front-end chip for a wide power supply voltage domain. The technical problem to be solved is that the power supply voltage domain of the existing current mirror circuit is limited and cannot be used in low power supply voltage.
[0010] To solve the above technical problems, in the first aspect, this utility model provides the following technical solution: a current mirror circuit for a wide power supply voltage domain, comprising a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;
[0011] The first connection terminal of the first transistor M1 is electrically connected to the second connection terminal of the first transistor M1, the second connection terminal of the second transistor M2, the second connection terminal of the third transistor M3, and the second connection terminal of the fourth transistor M4, respectively.
[0012] The third connection terminal of the first transistor M1 is electrically connected to the first connection terminal of the third transistor M3, and the third connection terminal of the second transistor M2 is electrically connected to the first connection terminal of the fourth transistor M4.
[0013] The third connection terminal of the third transistor M3 and the third connection terminal of the fourth transistor M4 are both grounded.
[0014] In one embodiment of the first aspect, the width-to-length ratio of the first transistor M1 is greater than the width-to-length ratio of the third transistor M3.
[0015] In one embodiment of the first aspect, the ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the third transistor M3 is between 1 and 10.
[0016] In one embodiment of the first aspect, the width-to-length ratio of the second transistor M2 is greater than the width-to-length ratio of the fourth transistor M4.
[0017] In one embodiment of the first aspect, the ratio of the width-to-length ratio of the second transistor M2 to the width-to-length ratio of the fourth transistor M4 is between 1 and 10.
[0018] In one embodiment of the first aspect, the first transistor M1 is an NMOS transistor, the drain of the NMOS transistor is the first connection terminal of the first transistor M1, the gate of the NMOS transistor is the second connection terminal of the first transistor M1, and the source of the NMOS transistor is the third connection terminal of the first transistor M1.
[0019] In one embodiment of the first aspect, the second transistor M2 is an NMOS transistor, the drain of the NMOS transistor is the first connection terminal of the second transistor M2, the gate of the NMOS transistor is the second connection terminal of the second transistor M2, and the source of the NMOS transistor is the third connection terminal of the second transistor M2.
[0020] In one embodiment of the first aspect, the third transistor M3 is an NMOS transistor, the drain of the NMOS transistor is the first connection terminal of the third transistor M3, the gate of the NMOS transistor is the second connection terminal of the third transistor M3, and the source of the NMOS transistor is the third connection terminal of the third transistor M3.
[0021] In one embodiment of the first aspect, the fourth transistor M4 is an NMOS transistor, the drain of the NMOS transistor is the first connection terminal of the fourth transistor M4, the gate of the NMOS transistor is the second connection terminal of the fourth transistor M4, and the source of the NMOS transistor is the third connection terminal of the fourth transistor M4.
[0022] Secondly, this utility model also provides an RF front-end chip, characterized in that it includes the aforementioned current mirror circuit for a wide power supply voltage domain.
[0023] The advantages of this invention compared to the prior art are as follows: In actual use, the third transistor M3 and the fourth transistor M4 of this invention operate in the linear region, while the first transistor M1 and the second transistor M2 typically operate in the saturation region. Therefore, the voltage difference between the first connection terminal and the third connection terminal of the third transistor M3 and the fourth transistor M4 is small, and the difference between the Vdsat (saturation voltage of the transistor) of the third transistor M3 and the fourth transistor M4 and the Vdsat of ordinary transistors is not significant, making it suitable for use in low power supply voltage applications.
[0024] In addition, the third transistor M3 and the fourth transistor M4 operate in the linear region and can be equivalent to a common-source amplifier with source negative feedback, thereby improving the output impedance. Attached Figure Description
[0025] Figure 1 Here is the application circuit diagram for an existing basic current mirror;
[0026] Figure 2 This is the application circuit diagram for a conventional cascode current mirror.
[0027] Figure 3 This is a circuit diagram illustrating the application of the current mirror of this invention in an embodiment.
[0028] Figure 4 for Figure 3 The equivalent circuit diagram of the first transistor M1 and the third transistor M3 in the circuit. Detailed Implementation
[0029] The following specific embodiments illustrate an implementation of the current mirror circuit for a wide power supply voltage domain disclosed in this utility model. Those skilled in the art can understand the advantages and effects of this utility model from the content disclosed in this specification. This utility model can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this utility model. Furthermore, the accompanying drawings of this utility model are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this utility model in detail, but the disclosed content is not intended to limit the scope of protection of this utility model.
[0030] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or features, these components or features should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one feature from another. Furthermore, the terms used in this document may, as appropriate, include any combination of one or more related items listed.
[0031] like Figure 1 As shown, this embodiment provides a current mirror circuit for a wide power supply voltage domain, including a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.
[0032] The connection relationship between the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 is as follows:
[0033] The first connection terminal of the first transistor M1 is electrically connected to the second connection terminal of the first transistor M1, the second connection terminal of the second transistor M2, the second connection terminal of the third transistor M3, and the second connection terminal of the fourth transistor M4, respectively.
[0034] The third connection terminal of the first transistor M1 is electrically connected to the first connection terminal of the third transistor M3, and the third connection terminal of the second transistor M2 is electrically connected to the first connection terminal of the fourth transistor M4.
[0035] The third connection terminal of the third transistor M3 and the third connection terminal of the fourth transistor M4 are both grounded.
[0036] In addition, in this embodiment, the width-to-length ratio of the first transistor M1 is greater than the width-to-length ratio of the third transistor M3. Specifically, the width-to-length ratio of the first transistor M1 to the third transistor M3 is between 1 and 10. For example, the width-to-length ratio of the first transistor M1 to the third transistor M3 can be 2, 4, 6, or 8.
[0037] In addition, in this embodiment, the width-to-length ratio of the second transistor M2 is greater than the width-to-length ratio of the fourth transistor M4. Specifically, the width-to-length ratio of the second transistor M2 to the fourth transistor M4 is between 1 and 10. For example, the ratio of the width-to-length ratio of the second transistor M2 to the fourth transistor M4 can be 2, 4, 6, or 8.
[0038] In addition, in this embodiment, the first transistor M1 is an NMOS transistor, the drain of the NMOS transistor is the first connection terminal of the first transistor M1, the gate of the NMOS transistor is the second connection terminal of the first transistor M1, and the source of the NMOS transistor is the third connection terminal of the first transistor M1.
[0039] Similarly, in this embodiment, the second transistor M2 is an NMOS transistor, the drain of the NMOS transistor is the first connection terminal of the second transistor M2, the gate of the NMOS transistor is the second connection terminal of the second transistor M2, and the source of the NMOS transistor is the third connection terminal of the second transistor M2.
[0040] Similarly, in this embodiment, the third transistor M3 is an NMOS transistor, the drain of the NMOS transistor is the first connection terminal of the third transistor M3, the gate of the NMOS transistor is the second connection terminal of the third transistor M3, and the source of the NMOS transistor is the third connection terminal of the third transistor M3.
[0041] Similarly, in this embodiment, the fourth transistor M4 is an NMOS transistor, the drain of the NMOS transistor is the first connection terminal of the fourth transistor M4, the gate of the NMOS transistor is the second connection terminal of the fourth transistor M4, and the source of the NMOS transistor is the third connection terminal of the fourth transistor M4.
[0042] In practical use, Figure 3 The circuit shown works as follows:
[0043] First, the gates of the first transistor M1 and the third transistor M3 are electrically connected together to form a self-cascaded composite transistor. The third transistor M3 and the fourth transistor M4 operate in the linear region, while the first transistor M1 and the second transistor M2 typically operate in the saturation region. Therefore, the voltage difference between the first and third connection terminals of the third transistor M3 and the fourth transistor M4 is small, and the Vdsat (saturation voltage of the transistor) of the third transistor M3 and the fourth transistor M4 is not significantly different from the Vdsat of ordinary transistors, making it suitable for use in low power supply voltage applications.
[0044] Furthermore, the third transistor M3 and the fourth transistor M4 operate in the linear region, such as Figure 4 As shown, the impedance seen from the drain of the third transistor M3 is RM3≈1 / gm3, where gm3 is the transconductance of the third transistor M3. Therefore, the composite transistor can be equivalent to a common-source amplifier with source negative feedback. Its output impedance is gm1*ro1*RM3=gm1*ro1 / gm3≈m*ro1, where m>>1. Thus, the output impedance is increased by about m times, and the output impedance is improved.
[0045] In addition, this embodiment also provides an RF front-end chip, including the above-described current mirror circuit for a wide power supply voltage domain.
[0046] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.
Claims
1. A current mirror circuit for a wide power supply voltage domain, characterized in that, It includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4; The first connection terminal of the first transistor M1 is electrically connected to the second connection terminal of the first transistor M1, the second connection terminal of the second transistor M2, the second connection terminal of the third transistor M3, and the second connection terminal of the fourth transistor M4, respectively. The third connection terminal of the first transistor M1 is electrically connected to the first connection terminal of the third transistor M3, and the third connection terminal of the second transistor M2 is electrically connected to the first connection terminal of the fourth transistor M4. The third connection terminal of the third transistor M3 and the third connection terminal of the fourth transistor M4 are both grounded.
2. A current mirror circuit for a wide power supply voltage domain according to claim 1, characterized in that, The width-to-length ratio of the first transistor M1 is greater than that of the third transistor M3.
3. A current mirror circuit for a wide power supply voltage domain according to claim 2, characterized in that, The ratio of the width to the length of the first transistor M1 to the width to the length of the third transistor M3 is between 1 and 10.
4. A current mirror circuit for a wide power supply voltage domain according to claim 1, characterized in that, The width-to-length ratio of the second transistor M2 is greater than that of the fourth transistor M4.
5. A current mirror circuit for a wide power supply voltage domain according to claim 1, characterized in that, The ratio of the width to the length of the second transistor M2 to the ratio of the width to the length of the fourth transistor M4 is between 1 and 10.
6. A current mirror circuit for a wide power supply voltage domain according to claim 1, characterized in that, The first transistor M1 is an NMOS transistor. The drain of the NMOS transistor is the first connection terminal of the first transistor M1, the gate of the NMOS transistor is the second connection terminal of the first transistor M1, and the source of the NMOS transistor is the third connection terminal of the first transistor M1.
7. A current mirror circuit for a wide power supply voltage domain according to claim 1, characterized in that, The second transistor M2 is an NMOS transistor. The drain of the NMOS transistor is the first connection terminal of the second transistor M2, the gate of the NMOS transistor is the second connection terminal of the second transistor M2, and the source of the NMOS transistor is the third connection terminal of the second transistor M2.
8. A current mirror circuit for a wide power supply voltage domain according to claim 1, characterized in that, The third transistor M3 is an NMOS transistor. The drain of the NMOS transistor is the first connection terminal of the third transistor M3, the gate of the NMOS transistor is the second connection terminal of the third transistor M3, and the source of the NMOS transistor is the third connection terminal of the third transistor M3.
9. A current mirror circuit for a wide power supply voltage domain according to claim 1, characterized in that, The fourth transistor M4 is an NMOS transistor. The drain of the NMOS transistor is the first connection terminal of the fourth transistor M4, the gate of the NMOS transistor is the second connection terminal of the fourth transistor M4, and the source of the NMOS transistor is the third connection terminal of the fourth transistor M4.
10. A radio frequency front-end chip, characterized in that, Includes a current mirror circuit for a wide power supply voltage range as described in any one of claims 1-9.