Linear voltage regulator and radio frequency power amplifier

Abstract

The utility model provides a linear voltage regulator and a radio frequency power amplifier, and the linear voltage regulator comprises a current source generation circuit, an enhancement circuit and a linear voltage stabilizing circuit. The current source generation circuit is used for generating a fixed current source, the enhancement circuit is used for generating voltage overcharge when the linear voltage stabilizer establishes a transient state, and the linear voltage stabilizing circuit is used for generating stable adjusting voltage. After the linear voltage regulator is applied to the radio frequency power amplifier, the linear voltage regulator can generate voltage overcharge at the starting moment of the radio frequency power amplifier, equivalently, the bias voltage of the radio frequency power amplifier at the starting moment is improved, so that the effect of improving the linearity of the radio frequency power amplifier is achieved; therefore, the requirement of the radio frequency power amplifier for linearity at the starting moment is met.

Description

TECHNICAL FIELD

[0001] The utility model relates to wireless communication technical field especially relates to a linear voltage stabilizer and radio frequency power amplifier. BACKGROUND

[0002] In wireless radio frequency communication system, the main function of radio frequency power amplifier is to realize radio frequency signal as far as possible small distortion amplification, but its linearity will be influenced by the adjustment voltage, namely the higher the adjustment voltage, its linearity is better, on the contrary, the lower the adjustment voltage, its linearity is worse.

[0003] In prior art, radio frequency power amplifier mainly includes input matching circuit, power amplifier, output matching circuit and linear voltage stabilizer for generating stable adjustment voltage value.

[0004] Although the linear voltage stabilizer in prior art can provide stable adjustment voltage for radio frequency power amplifier, for time division communication system, the opening stage of radio frequency power amplifier will cause that the adjustment voltage generated by its linear voltage stabilizer cannot meet the demand of radio frequency power amplifier for linearity because of the internal heat distribution not yet stable. SUMMARY

[0005] In view of the above problems of prior art, the utility model provides a new linear voltage stabilizer and radio frequency power amplifier to solve the problem that the adjustment voltage generated by the linear voltage stabilizer of radio frequency power amplifier in prior art cannot meet the demand of radio frequency power amplifier for linearity in the opening stage.

[0006] In order to solve the above technical problem, first, the utility model provides a linear voltage stabilizer, which comprises current source generating circuit, enhancement circuit and linear voltage stabilization circuit, the current source generating circuit is used to generate fixed current source, the enhancement circuit is used to realize that the linear voltage stabilizer generates voltage overcharge when establishing transient state, and the linear voltage stabilization circuit is used to generate stable adjustment voltage.

[0007] The first input end of the current source generating circuit is used to connect reference voltage, and the second input end of the current source generating circuit is used to connect power supply voltage.

[0008] The input end of the enhancement circuit is connected to the output end of the current source generating circuit.

[0009] The first input end of the linear voltage stabilization circuit is used to connect reference voltage, the second input end of the linear voltage stabilization circuit is used to connect power supply voltage, the third input end of the linear voltage stabilization circuit is connected to the output end of the enhancement circuit, and the output end of the linear voltage stabilization circuit is used to output adjustment voltage.

[0010] Preferably, the current source generating circuit comprises a first resistor, a first capacitor, a first operational amplifier, a second resistor, a second capacitor, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a third resistor, a third capacitor and a fifth field effect transistor;

[0011] A first end of the first resistor is a first input end of the current source generating circuit;

[0012] A first end of the first capacitor is connected to a second end of the first resistor, and a second end of the first capacitor is grounded;

[0013] A negative input end of the first operational amplifier is connected to the second end of the first resistor;

[0014] A first end of the second resistor is connected to an output end of the first operational amplifier;

[0015] A first end of the second capacitor is connected to a second end of the second resistor, and a second end of the second capacitor is connected to a positive input end of the first operational amplifier;

[0016] A gate of the first field effect transistor is connected to the output end of the first operational amplifier;

[0017] A source of the second field effect transistor is connected to a drain of the first field effect transistor, and a drain of the second field effect transistor is connected to the second end of the second capacitor;

[0018] A gate of the third field effect transistor is connected to the gate of the first field effect transistor, and a source of the third field effect transistor is connected to the source of the first field effect transistor and serves as a second input end of the current source generating circuit;

[0019] A gate of the fourth field effect transistor is connected to a gate of the second field effect transistor, a source of the fourth field effect transistor is connected to a drain of the third field effect transistor, and a drain of the fourth field effect transistor serves as an output end of the current source generating circuit;

[0020] A first end of the third resistor is connected to the drain of the second field effect transistor, and a second end of the third resistor is grounded;

[0021] A first end of the third capacitor is connected to the drain of the fourth field effect transistor, and a second end of the third capacitor is grounded;

[0022] A gate of the fifth field effect transistor is used for connecting a first enable signal, a drain of the fifth field effect transistor is connected to the drain of the fourth field effect transistor, and a source of the fifth field effect transistor is grounded.

[0023] Preferably, the enhancement circuit comprises a sixth field effect transistor and a fourth resistor.

[0024] a gate of the sixth field effect transistor is connected to an input end of the enhancement circuit, and a source of the sixth field effect transistor is connected to an output end of the enhancement circuit;

[0025] a first end of the fourth resistor is connected to a drain of the sixth field effect transistor, and a second end of the fourth resistor is grounded.

[0026] Preferably, the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor and the sixth field effect transistor are P-type field effect transistors, and the fifth field effect transistor is an N-type field effect transistor.

[0027] Preferably, the current source generating circuit comprises a first sub-resistor, a first sub-capacitor, a first sub-operational amplifier, a second sub-resistor, a second sub-capacitor, a first sub-field effect transistor, a second sub-field effect transistor, a third sub-field effect transistor, a fourth sub-field effect transistor, a third sub-resistor, a seventh field effect transistor, an eighth field effect transistor, a third sub-capacitor and a fifth sub-field effect transistor.

[0028] a first end of the first sub-resistor is connected to a first input end of the current source generating circuit;

[0029] a first end of the first sub-capacitor is connected to a second end of the first sub-resistor, and a second end of the first sub-capacitor is grounded.

[0030] a negative input end of the first sub-operational amplifier is connected to the second end of the first sub-resistor.

[0031] a first end of the second sub-resistor is connected to an output end of the first sub-operational amplifier.

[0032] a first end of the second sub-capacitor is connected to a second end of the second sub-resistor, and a second end of the second sub-capacitor is connected to a positive input end of the first sub-operational amplifier.

[0033] a gate of the first sub-field effect transistor is connected to the output end of the first sub-operational amplifier.

[0034] a source of the second sub-field effect transistor is connected to a drain of the first sub-field effect transistor, and a drain of the second sub-field effect transistor is connected to the second end of the second sub-capacitor.

[0035] a gate of the third sub-field effect transistor is connected to a gate of the first sub-field effect transistor, and a source of the third sub-field effect transistor is connected to a source of the first sub-field effect transistor and is commonly connected to a second input end of the current source generating circuit.

[0036] The gate of the fourth sub field effect transistor is connected to the gate of the second sub field effect transistor, and the source of the fourth sub field effect transistor is connected to the drain of the third sub field effect transistor;

[0037] The first end of the third sub resistance is connected to the drain of the second sub field effect transistor, and the second end of the third sub resistance is grounded;

[0038] The drain of the seventh field effect transistor is connected to the drain of the fourth sub field effect transistor and the gate of the seventh field effect transistor respectively, and the source of the seventh field effect transistor is grounded;

[0039] The gate of the eighth field effect transistor is connected to the gate of the seventh field effect transistor, the drain of the eighth field effect transistor is used as the output end of the current source generation circuit, and the source of the eighth field effect transistor is grounded;

[0040] The first end of the third sub capacitor is connected to the drain of the eighth field effect transistor, and the second end of the third sub capacitor is grounded;

[0041] The fifth sub field effect transistor is used for connecting a second enable signal, the drain of the fifth sub field effect transistor is connected to the drain of the eighth field effect transistor, and the source of the fifth sub field effect transistor is used for connecting a bias voltage.

[0042] Preferably, the enhancement circuit comprises a sixth sub field effect transistor and a fourth sub resistance;

[0043] The gate of the sixth sub field effect transistor is used as the input end of the enhancement circuit, and the source of the sixth sub field effect transistor is grounded;

[0044] The first end of the fourth sub resistance is connected to the drain of the sixth sub field effect transistor, and the second end of the fourth sub resistance is used as the output end of the enhancement circuit.

[0045] Preferably, the first sub field effect transistor, the second sub field effect transistor, the third sub field effect transistor, the fourth sub field effect transistor, and the fifth sub field effect transistor are all P-type field effect transistors; the seventh field effect transistor, the eighth field effect transistor, and the sixth sub field effect transistor are all N-type field effect transistors.

[0046] Preferably, the linear voltage stabilizing circuit comprises a fifth resistance, a fourth capacitor, a second operational amplifier, a sixth resistance, a fifth capacitor, a ninth field effect transistor, a seventh resistance, and an eighth resistance;

[0047] The first end of the fifth resistance is used as the first input end of the linear voltage stabilizing circuit;

[0048] The first end of the fourth capacitor is connected to the second end of the fifth resistance, and the second end of the fourth capacitor is grounded;

[0049] a negative input end of the second operational amplifier is connected to a second end of the fifth resistor;

[0050] a first end of the sixth resistor is connected to an output end of the second operational amplifier;

[0051] a first end of the fifth capacitor is connected to a second end of the sixth resistor;

[0052] a gate of the ninth field effect transistor is connected to the output end of the second operational amplifier, a source of the ninth field effect transistor is used as a second input end of the linear voltage stabilizer, and a drain of the ninth field effect transistor is used as an output end of the linear voltage stabilizer;

[0053] a first end of the seventh resistor is connected to a second end of the fifth capacitor and a drain of the ninth field effect transistor, a second end of the seventh resistor is connected to a positive input end of the second operational amplifier, and the positive input end of the second operational amplifier is used as a third input end of the linear voltage stabilizer;

[0054] a first end of the eighth resistor is connected to a second end of the seventh resistor, and a second end of the eighth resistor is grounded.

[0055] Preferably, the ninth field effect transistor is a P-type field effect transistor.

[0056] In a second aspect, the utility model provides a radio frequency power amplifier, it includes the linear voltage stabilizer as described above.

[0057] Compared with the prior art, the linear voltage stabilizer in the utility model is provided with an enhancement circuit between the current source generating circuit and the linear voltage stabilizer, and the enhancement circuit is used to realize voltage overcharge of the linear voltage stabilizer in the transient state, so that when the linear voltage stabilizer is applied to the radio frequency power amplifier, the linear voltage stabilizer can generate voltage overcharge at the starting moment of the radio frequency power amplifier, which is equivalent to improving the bias voltage of the radio frequency power amplifier at the starting moment, so as to improve the linearity of the radio frequency power amplifier, thereby meeting the demand of the radio frequency power amplifier for linearity at the starting moment. BRIEF DESCRIPTION OF DRAWINGS

[0058] The utility model will become more apparent and more easily understood by the detailed description in conjunction with the following drawings. In the drawings:

[0059] Figure 1 the output waveform diagram of the linear voltage stabilizer provided by the prior art;

[0060] Figure 2The circuit principle diagram of the linear voltage stabilizer is provided for the embodiment one of the utility model.

[0061] Figure 3 The circuit principle diagram of the linear voltage stabilizer is provided for the embodiment two of the utility model.

[0062] Figure 4 The output waveform diagram of the linear voltage stabilizer is provided for the embodiment one or the embodiment two of the utility model.

[0063] Among them, 100, linear voltage stabilizer;1, current source generation circuit;2, enhance short circuit;3, linear voltage stabilizer circuit. DETAILED DESCRIPTION

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application; the description and the drawings are to be regarded as illustrative in nature and are not intended to limit the application; the terminology used in the description and the claims of the present application, and the above description of the drawings, includes the terms "comprising", "having" and "including" and their derivatives, which are intended to be inclusive in a manner similar to the term "consisting of". The terms "first", "second", and the like, as used in the description and the claims of this application, are used for distinguishing between similar elements and not necessarily for describing a specific sequential or chronological order.

[0065] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0066] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the utility model.

[0067] Embodiment one

[0068] The utility model embodiment provides a kind of linear voltage stabilizer 100, combines Figure 2 As shown in the drawing, its current source generation circuit 1, enhancement circuit 2 and linear voltage stabilizer circuit 3;Current source generation circuit 1 is used to generate fixed current source, enhancement circuit 2 is used to realize that linear voltage stabilizer 100 generates voltage overcharge when establishing transient, linear voltage stabilizer circuit 3 is used to generate stable regulating voltage Vreg.

[0069] The first input terminal of the current source generating circuit 1 is used for connecting a reference voltage VBG, and the second input terminal of the current source generating circuit 1 is used for connecting a power supply voltage VDD.

[0070] The current source generating circuit 1 comprises a first resistor R1, a first capacitor C1, a first operational amplifier OP1, a second resistor R2, a second capacitor C2, a first field effect transistor MP1, a second field effect transistor MP2, a third field effect transistor MP3, a fourth field effect transistor MP4, a third resistor R3, a third capacitor C3, and a fifth field effect transistor MN5.

[0071] The first terminal of the first resistor R1 is used as the first input terminal of the current source generating circuit 1.

[0072] The first terminal of the first capacitor C1 is connected to the second terminal of the first resistor R1, and the second terminal of the first capacitor C1 is grounded.

[0073] The negative input terminal of the first operational amplifier OP1 is connected to the second terminal of the first resistor R1.

[0074] The first terminal of the second resistor R2 is connected to the output terminal of the first operational amplifier OP1.

[0075] The first terminal of the second capacitor C2 is connected to the second terminal of the second resistor R2, and the second terminal of the second capacitor C2 is connected to the positive input terminal of the first operational amplifier OP1.

[0076] The gate of the first field effect transistor MP1 is connected to the output terminal of the first operational amplifier OP1.

[0077] The source of the second field effect transistor MP2 is connected to the drain of the first field effect transistor MP1, and the drain of the second field effect transistor MP2 is connected to the second terminal of the second capacitor C2.

[0078] The gate of the third field effect transistor MP3 is connected to the gate of the first field effect transistor MP1, and the source of the third field effect transistor MP3 is connected to the source of the first field effect transistor MP1, which are used as the second input terminal of the current source generating circuit 1.

[0079] The gate of the fourth field effect transistor MP4 is connected to the gate of the second field effect transistor MP2, the source of the fourth field effect transistor MP4 is connected to the drain of the third field effect transistor MP3, and the drain of the fourth field effect transistor MP4 is used as the output terminal of the current source generating circuit 1.

[0080] The first terminal of the third resistor R3 is connected to the drain of the second field effect transistor MP2, and the second terminal of the third resistor R3 is grounded.

[0081] The first terminal of the third capacitor C3 is connected to the drain of the fourth field effect transistor MP4, and the second terminal of the third capacitor C3 is grounded.

[0082] The gate of the fifth field effect transistor MN5 is used for connecting a first enable signal ENB, the drain of the fifth field effect transistor MN5 is connected to the drain of the fourth field effect transistor MP4, and the source of the fifth field effect transistor MN5 is grounded.

[0083] The enhancement circuit 2 is also called overcharge generation circuit; the input end of the enhancement circuit 2 is connected to the output end of the current source generation circuit 1.

[0084] The enhancement circuit 2 comprises a sixth field effect transistor MP6 and a fourth resistor R4.

[0085] The gate of the sixth field effect transistor MP6 is used as the input end of the enhancement circuit 2, and the source of the sixth field effect transistor MP6 is used as the output end of the enhancement circuit 2.

[0086] The first end of the fourth resistor R4 is connected to the drain of the sixth field effect transistor MP6, and the second end of the fourth resistor R4 is grounded.

[0087] The first field effect transistor MP1, the second field effect transistor MP2, the third field effect transistor MP3, the fourth field effect transistor MP4 and the sixth field effect transistor MP6 are all P-type field effect transistors; and the fifth field effect transistor MN5 is an N-type field effect transistor.

[0088] The first input end of the linear voltage regulator circuit 3 is used for connecting a reference voltage VBG, the second input end of the linear voltage regulator circuit 3 is used for connecting a power supply voltage VDD, the third input end of the linear voltage regulator circuit 3 is connected to the output end of the enhancement circuit 2, and the output end of the linear voltage regulator circuit 3 is used for outputting an adjustment voltage Vreg.

[0089] The linear voltage regulator circuit 3 comprises a fifth resistor R5, a fourth capacitor C4, a second operational amplifier OP2, a sixth resistor R6, a fifth capacitor C5, a ninth field effect transistor MP9, a seventh resistor R7 and an eighth resistor R8.

[0090] The first end of the fifth resistor R5 is used as the first input end of the linear voltage regulator circuit 3.

[0091] The first end of the fourth capacitor C4 is connected to the second end of the fifth resistor R5, and the second end of the fourth capacitor C4 is grounded.

[0092] The negative phase input end of the second operational amplifier OP2 is connected to the second end of the fifth resistor R5.

[0093] The first end of the sixth resistor R6 is connected to the output end of the second operational amplifier OP2.

[0094] The first end of the fifth capacitor C5 is connected to the second end of the sixth resistor R6.

[0095] The gate of the ninth field effect transistor MP9 is connected to the output of the second operational amplifier OP2, the source of the ninth field effect transistor MP9 is the second input of the linear voltage regulator circuit 3, and the drain of the ninth field effect transistor MP9 is the output of the linear voltage regulator circuit 3.

[0096] The first end of the seventh resistor R7 is connected to the second end of the fifth capacitor C5, the first end of the seventh resistor R7 is connected to the drain of the ninth field effect transistor MP9, the second end of the seventh resistor R7 is connected to the non-inverting input of the second operational amplifier OP2, and the non-inverting input of the second operational amplifier OP2 is the third input of the linear voltage regulator circuit 3.

[0097] The first end of the eighth resistor R8 is connected to the second end of the seventh resistor R7, and the second end of the eighth resistor R8 is grounded; in this embodiment, the second end of the eighth resistor R8 is connected to the second end of the fourth resistor R4 and then grounded.

[0098] The ninth field effect transistor MP9 is a P-type field effect transistor.

[0099] In the current source circuit, the first resistor R1 and the first capacitor C1 form a low-pass circuit for filtering and stabilizing voltage; the second resistor R2 and the second capacitor C2 are used for Miller compensation to ensure the stability of the feedback loop; the first field effect transistor MP1 and the second field effect transistor MP2 form a common-source and common-gate configuration to reduce the channel modulation effect and improve the current accuracy; the first field effect transistor MP1, the second field effect transistor MP2, the third field effect transistor MP3, and the fourth field effect transistor MP4 form a PMOS current mirror circuit, the first operational amplifier OP1 and the PMOS current mirror circuit form a negative feedback; and the reference voltage VBG generates a fixed current source on the third resistor R3.

[0100] In the enhancement circuit 2, the gate voltage of the sixth field effect transistor MP6 comes from the third capacitor C3, and the fifth field effect transistor MN5 functions as a switch and starts to work when the first enable signal ENB is switched from high level to low level.

[0101] In the linear voltage regulator circuit 3, the fifth resistor R5 and the fourth capacitor C4 are used for low-pass filtering; the sixth resistor R6 and the fifth capacitor C5 function as Miller compensation to ensure the stability of the negative feedback loop; the second operational amplifier OP2, the ninth field effect transistor MP9, the seventh resistor R7, the eighth resistor R8, the fourth resistor R4, and the sixth field effect transistor MP6 form the linear voltage regulator circuit 3 of the negative feedback loop.

[0102] The linear regulator 100 ultimately outputs an adjustment voltage Vreg, the overcharge amplitude and time of which are controllable. In the initial stage of enabling, the voltage at the upper plate of the third capacitor C3 starts from 0V, is charged by the current source, and finally reaches the power supply voltage VDD. The charging time of the third capacitor C3 is linearly related to the current of the current source, and the time for the overcharge voltage to be generated is ΔT. In this stage, the sixth field-effect transistor MP6 goes from being turned on to being turned off, and the resistance Ron of the sixth field-effect transistor MP6 increases from small to large, as shown in the following formula (1). As the voltage at the upper plate of the third capacitor C3 increases, the driving voltage Vgs of the sixth field-effect transistor MP6 decreases, and the resistance of the sixth field-effect transistor MP6 increases, eventually becoming the output voltage Vreg_start of the linear regulator circuit 3, as shown in the following formula (2). In addition, as the resistance of the sixth field-effect transistor MP6 increases, the adjustment voltage Vreg decreases until the third capacitor C3 is charged to the point where the sixth field-effect transistor MP6 is turned off, at which point the adjustment voltage Vreg decreases to the voltage value Vreg_stable calculated by the following formula (3).

[0103]

[0104] The linear regulator 100 in this embodiment mainly utilizes the characteristic that the resistance of the field-effect transistor is controlled by the gate-source voltage. An enhancement circuit 2 is added, that is, a feedback resistor branch is added, so as to realize the waveform of voltage enhancement during the turn-on stage, so as to meet the requirements of the power amplifier for bias voltage and linearity during the turn-on stage.

[0105] Figure 1 The output waveform of a linear regulator in the prior art shows that it does not improve the bias voltage and linearity during the turn-on phase. This means that the linear regulator cannot meet the linearity requirements of the RF power amplifier. Figure 4 The output waveform of the linear regulator 100 in this embodiment is shown in the figure. It can be seen from the figure that at the moment of bias voltage establishment, a voltage overcharge of ΔV amplitude with a controllable time length ΔT will occur. During this stage, the bias voltage of the RF power amplifier can be increased, and its linearity during the turn-on stage can also be improved, thereby meeting the linearity requirements of the RF power amplifier.

[0106] Compared with the prior art, the linear voltage stabilizer 100 in the embodiment can make the linear voltage stabilizer 100 produce voltage overcharge at the starting moment of the radio frequency power amplifier, which is equivalent to increasing the bias voltage of the radio frequency power amplifier at the starting moment, so as to improve the linearity of the radio frequency power amplifier, thereby meeting the requirement of the radio frequency power amplifier for linearity at the starting moment.

[0107] Embodiment two

[0108] The embodiment is different from the above-mentioned embodiment one in that Figure 3 As shown in the figure, the current source generating circuit 1 comprises a first sub-resistor R11, a first sub-capacitor C11, a first sub-operational amplifier OP11, a second sub-resistor R21, a second sub-capacitor C21, a first sub-field effect transistor MP11, a second sub-field effect transistor MP21, a third sub-field effect transistor MP31, a fourth sub-field effect transistor MP41, a third sub-resistor R31, a seventh field effect transistor MN7, an eighth field effect transistor MN8, a third sub-capacitor C31 and a fifth sub-field effect transistor MP51.

[0109] The first end of the first sub-resistor R11 is used as the first input end of the current source generating circuit 1.

[0110] The first end of the first sub-capacitor C11 is connected to the second end of the first sub-resistor R11, and the second end of the first sub-capacitor C11 is grounded.

[0111] The negative phase input end of the first sub-operational amplifier OP11 is connected to the second end of the first sub-resistor R11.

[0112] The first end of the second sub-resistor R21 is connected to the output end of the first sub-operational amplifier OP11.

[0113] The first end of the second sub-capacitor C21 is connected to the second end of the second sub-resistor R21, and the second end of the second sub-capacitor C21 is connected to the positive phase input end of the first sub-operational amplifier OP11.

[0114] The gate of the first sub-field effect transistor MP11 is connected to the output end of the first sub-operational amplifier OP11.

[0115] The source of the second sub-field effect transistor MP21 is connected to the drain of the first sub-field effect transistor MP11, and the drain of the second sub-field effect transistor MP21 is connected to the second end of the second sub-capacitor C21.

[0116] The gate of the third sub field effect transistor MP31 is connected to the gate of the first sub field effect transistor MP11, and the source of the third sub field effect transistor MP31 and the source of the first sub field effect transistor MP11 are adjacent and jointly serve as the second input terminal of the current source generating circuit 1.

[0117] The gate of the fourth sub field effect transistor MP41 is connected to the gate of the second sub field effect transistor MP21, and the source of the fourth sub field effect transistor MP41 is connected to the drain of the third sub field effect transistor MP31.

[0118] The first end of the third sub resistor R31 is connected to the drain of the second sub field effect transistor MP21, and the second end of the third sub resistor R31 is grounded.

[0119] The drain of the seventh field effect transistor MN7 is connected to the drain of the fourth sub field effect transistor MP41 and the gate of the seventh field effect transistor MN7 respectively, and the source of the seventh field effect transistor MN7 is grounded.

[0120] The gate of the eighth field effect transistor MN8 is connected to the gate of the seventh field effect transistor MN7, the drain of the eighth field effect transistor MN8 serves as the output terminal of the current source generating circuit 1, and the source of the eighth field effect transistor MN8 is grounded.

[0121] The first end of the third sub capacitor C31 is connected to the drain of the eighth field effect transistor MN8, and the second end of the third sub capacitor C31 is grounded.

[0122] The fifth sub field effect transistor MP51 is used for connecting the second enable signal ENA, the drain of the fifth sub field effect transistor MP51 is connected to the drain of the eighth field effect transistor MN8, and the source of the fifth sub field effect transistor MP51 is used for connecting the bias voltage VBIAS.

[0123] The enhancement circuit 2 comprises a sixth sub field effect transistor MN61 and a fourth sub resistor R41.

[0124] The gate of the sixth sub field effect transistor MN61 serves as the input terminal of the enhancement circuit 2, and the source of the sixth sub field effect transistor MN61 is grounded. In the embodiment, the second end of the eighth resistor R8 is connected to the source of the sixth sub field effect transistor MN61 and then grounded.

[0125] The first end of the fourth sub resistor R41 is connected to the drain of the sixth sub field effect transistor MN61, and the second end of the fourth sub resistor R41 serves as the output terminal of the enhancement circuit 2.

[0126] The first sub field effect transistor MP11, the second sub field effect transistor MP21, the third sub field effect transistor MP31, the fourth sub field effect transistor MP41, and the fifth sub field effect transistor MP51 are all P-type field effect transistors; the seventh field effect transistor MN7, the eighth field effect transistor MN8, and the sixth sub field effect transistor MN61 are all N-type field effect transistors.

[0127] In the current source circuit, the first sub-resistor R11 and the first sub-capacitor C11 form a low-pass circuit for filtering and stabilizing voltage; the second sub-resistor R21 and the second sub-capacitor C21 are used for Miller compensation to ensure the stability of the feedback loop; the first sub-MOS transistor MP11 and the second sub-MOS transistor MP21 form a common-source common-gate configuration to reduce the channel modulation effect and improve the current accuracy; the first sub-MOS transistor MP1, the second sub-MOS transistor MP2, the third sub-MOS transistor MP3 and the fourth sub-MOS transistor MP4 form a PMOS current mirror circuit, the first sub-operational amplifier OP11 and the PMOS current mirror circuit form a negative feedback; the reference voltage VBG generates a fixed current source on the third sub-resistor R31.

[0128] In the enhancement circuit 2, the gate voltage of the sixth sub-MOS transistor MN61 comes from the third sub-capacitor C31, and the fifth sub-MOS transistor MP51 acts as a switch and starts to work when the second enable signal ENA is switched from low to high level, and when the second enable signal ENA is low, the third sub-capacitor C31 is charged to the bias voltage VBIAS.

[0129] In the linear voltage regulator circuit 3, the fifth resistor R5 and the fourth capacitor C4 are used for low-pass filtering; the sixth resistor R6 and the fifth capacitor C5 are used for Miller compensation to ensure the stability of the negative feedback loop; the second operational amplifier OP2, the ninth MOS transistor MP9, the seventh resistor R7, the eighth resistor R8, the fourth sub-resistor R41 and the sixth sub-MOS transistor MN61 form the linear voltage regulator circuit 3 of the negative feedback loop.

[0130] The linear voltage regulator 100 finally outputs the adjustment voltage Vreg, and the overcharge amplitude and time are controllable; in the initial stage of enable, the upper plate point of the third sub-capacitor C31 is the bias voltage VBIAS, which is finally charged to 0V, and the discharge time of the third sub-capacitor C31 is linearly related to the current size of the current source, and the time of finally generating the overcharge voltage is ΔT; in this stage, the sixth sub-MOS transistor MN61 is turned on to off, and the resistance Ron of the sixth sub-MOS transistor MN61 increases from small to large, as shown in the above formula (1); and as the voltage of the upper plate of the third sub-capacitor C31 decreases, the driving voltage Vgs of the sixth sub-MOS transistor MN61 decreases, and the resistance of the sixth sub-MOS transistor MN61 increases, and finally the output voltage Vreg_start of the linear voltage regulator circuit 3 is as shown in the above formula (2); in addition, as the resistance of the sixth sub-MOS transistor MN61 increases, the adjustment voltage Vreg decreases, until the third sub-capacitor C31 is discharged to below the threshold voltage of the sixth MOS transistor MP6, and the adjustment voltage Vreg is reduced to the voltage value Vreg_stable calculated by the above formula (3).

[0131] The technical effects achieved by the linear voltage stabilizer 100 in this embodiment are the same as those achieved by the linear voltage stabilizer 100 in Embodiment 1, and are not repeated here.

[0132] Embodiment Three

[0133] This embodiment provides a radio frequency power amplifier, which comprises the linear voltage stabilizer 100 in Embodiment 1 or Embodiment 2. Since the radio frequency power amplifier in this embodiment contains the linear voltage stabilizer 100 in Embodiment 1 or Embodiment 2, it can also achieve the technical effects achieved by the linear voltage stabilizer 100 in Embodiment 1 or Embodiment 2, and is not repeated here.

[0134] It should be noted that the various embodiments described above with reference to the drawings are merely intended to illustrate the present application and not to limit the scope of the present application. Those skilled in the art should understand that modifications or equivalent replacements made to the present application without departing from the spirit and scope of the present application shall be covered within the scope of the present application. In addition, unless otherwise indicated by the context, the singular form of a word includes the plural form, and vice versa. Furthermore, unless specifically stated, all or part of any embodiment can be used in conjunction with all or part of any other embodiment.

Claims

1. A linear voltage regulator, characterized in that, The linear regulator includes a current source generating circuit, an enhancement circuit, and a linear regulating circuit; the current source generating circuit generates a fixed current source, the enhancement circuit enables the linear regulator to generate voltage overcharge during transient establishment, and the linear regulating circuit generates a stable adjustment voltage. The first input terminal of the current source generating circuit is used to connect to a reference voltage, and the second input terminal of the current source generating circuit is used to connect to a power supply voltage. The input terminal of the enhancement circuit is connected to the output terminal of the current source generating circuit. The first input terminal of the linear voltage regulator circuit is used to connect to the reference voltage, the second input terminal of the linear voltage regulator circuit is used to connect to the power supply voltage, the third input terminal of the linear voltage regulator circuit is connected to the output terminal of the enhancement circuit, and the output terminal of the linear voltage regulator circuit is used to output the adjustment voltage.

2. The linear regulator as described in claim 1, characterized in that, The current source generating circuit includes a first resistor, a first capacitor, a first operational amplifier, a second resistor, a second capacitor, a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a third resistor, a third capacitor, and a fifth field-effect transistor; The first end of the first resistor serves as the first input terminal of the current source generating circuit. The first terminal of the first capacitor is connected to the second terminal of the first resistor, and the second terminal of the first capacitor is grounded. The negative inverting input terminal of the first operational amplifier is connected to the second terminal of the first resistor; The first end of the second resistor is connected to the output terminal of the first operational amplifier; The first terminal of the second capacitor is connected to the second terminal of the second resistor, and the second terminal of the second capacitor is connected to the non-inverting input terminal of the first operational amplifier. The gate of the first field-effect transistor is connected to the output terminal of the first operational amplifier; The source of the second field-effect transistor is connected to the drain of the first field-effect transistor, and the drain of the second field-effect transistor is connected to the second terminal of the second capacitor; The gate of the third field-effect transistor is connected to the gate of the first field-effect transistor, and the source of the third field-effect transistor is connected to the source of the first field-effect transistor and together serve as the second input terminal of the current source generation circuit. The gate of the fourth field-effect transistor is connected to the gate of the second field-effect transistor, the source of the fourth field-effect transistor is connected to the drain of the third field-effect transistor, and the drain of the fourth field-effect transistor serves as the output terminal of the current source generating circuit. The first end of the third resistor is connected to the drain of the second field-effect transistor, and the second end of the third resistor is grounded. The first terminal of the third capacitor is connected to the drain of the fourth field-effect transistor, and the second terminal of the third capacitor is grounded. The gate of the fifth field-effect transistor is used to connect to the first enable signal, the drain of the fifth field-effect transistor is connected to the drain of the fourth field-effect transistor, and the source of the fifth field-effect transistor is grounded.

3. The linear voltage regulator as described in claim 2, characterized in that, The enhancement circuit includes a sixth field-effect transistor and a fourth resistor; The gate of the sixth field-effect transistor serves as the input terminal of the enhancement circuit, and the source of the sixth field-effect transistor serves as the output terminal of the enhancement circuit. The first end of the fourth resistor is connected to the drain of the sixth field-effect transistor, and the second end of the fourth resistor is grounded.

4. The linear regulator as described in claim 3, characterized in that, The first field-effect transistor, the second field-effect transistor, the third field-effect transistor, the fourth field-effect transistor, and the sixth field-effect transistor are all P-type field-effect transistors; the fifth field-effect transistor is an N-type field-effect transistor.

5. The linear regulator as described in claim 1, characterized in that, The current source generating circuit includes a first sub-resistor, a first sub-capacitor, a first sub-operational amplifier, a second sub-resistor, a second sub-capacitor, a first sub-field-effect transistor, a second sub-field-effect transistor, a third sub-field-effect transistor, a fourth sub-field-effect transistor, a third sub-resistor, a seventh sub-field-effect transistor, an eighth sub-field-effect transistor, a third sub-capacitor, and a fifth sub-field-effect transistor. The first end of the first sub-resistor serves as the first input end of the current source generating circuit. The first terminal of the first sub-capacitor is connected to the second terminal of the first sub-resistor, and the second terminal of the first sub-capacitor is grounded. The negative inverting input terminal of the first sub-operational amplifier is connected to the second terminal of the first sub-resistor; The first terminal of the second sub-resistor is connected to the output terminal of the first sub-operational amplifier; The first end of the second sub-capacitor is connected to the second end of the second sub-resistor, and the second end of the second sub-capacitor is connected to the non-inverting input of the first sub-operational amplifier; The gate of the first sub-field-effect transistor is connected to the output terminal of the first sub-operational amplifier; The source of the second sub-field-effect transistor is connected to the drain of the first sub-field-effect transistor, and the drain of the second sub-field-effect transistor is connected to the second terminal of the second sub-capacitor. The gate of the third sub-field-effect transistor is connected to the gate of the first sub-field-effect transistor, and the source of the third sub-field-effect transistor is connected to the source of the first sub-field-effect transistor and together serve as the second input terminal of the current source generation circuit. The gate of the fourth sub-field-effect transistor is connected to the gate of the second sub-field-effect transistor, and the source of the fourth sub-field-effect transistor is connected to the drain of the third sub-field-effect transistor. The first terminal of the third sub-resistor is connected to the drain of the second sub-field-effect transistor, and the second terminal of the third sub-resistor is grounded. The drain of the seventh field-effect transistor is connected to the drain of the fourth sub-field-effect transistor and the gate of the seventh field-effect transistor, respectively, and the source of the seventh field-effect transistor is grounded. The gate of the eighth field-effect transistor is connected to the gate of the seventh field-effect transistor, the drain of the eighth field-effect transistor serves as the output terminal of the current source generating circuit, and the source of the eighth field-effect transistor is grounded. The first terminal of the third sub-capacitor is connected to the drain of the eighth field-effect transistor, and the second terminal of the third sub-capacitor is grounded. The fifth sub-field-effect transistor's gate is used to connect to the second enable signal, the drain of the fifth sub-field-effect transistor is connected to the drain of the eighth field-effect transistor, and the source of the fifth sub-field-effect transistor is used to connect to the bias voltage.

6. The linear regulator as described in claim 5, characterized in that, The enhancement circuit includes a sixth sub-field-effect transistor and a fourth sub-resistor; The gate of the sixth sub-field-effect transistor serves as the input terminal of the enhancement circuit, and the source of the sixth sub-field-effect transistor is grounded. The first end of the fourth sub-resistor is connected to the drain of the sixth sub-field-effect transistor, and the second end of the fourth sub-resistor serves as the output terminal of the enhancement circuit.

7. The linear regulator as described in claim 6, characterized in that, The first sub-field-effect transistor, the second sub-field-effect transistor, the third sub-field-effect transistor, the fourth sub-field-effect transistor, and the fifth sub-field-effect transistor are all P-type field-effect transistors; the seventh field-effect transistor, the eighth field-effect transistor, and the sixth sub-field-effect transistor are all N-type field-effect transistors.

8. The linear regulator as described in any one of claims 1 to 7, characterized in that, The linear voltage regulator circuit includes a fifth resistor, a fourth capacitor, a second operational amplifier, a sixth resistor, a fifth capacitor, a ninth field-effect transistor, a seventh resistor, and an eighth resistor; The first terminal of the fifth resistor serves as the first input terminal of the linear voltage regulator circuit. The first terminal of the fourth capacitor is connected to the second terminal of the fifth resistor, and the second terminal of the fourth capacitor is grounded. The negative inverting input terminal of the second operational amplifier is connected to the second terminal of the fifth resistor; The first end of the sixth resistor is connected to the output end of the second operational amplifier; The first terminal of the fifth capacitor is connected to the second terminal of the sixth resistor; The gate of the ninth field-effect transistor is connected to the output terminal of the second operational amplifier, the source of the ninth field-effect transistor serves as the second input terminal of the linear voltage regulator circuit, and the drain of the ninth field-effect transistor serves as the output terminal of the linear voltage regulator circuit. The first end of the seventh resistor is connected to the second end of the fifth capacitor, the first end of the seventh resistor is connected to the drain of the ninth field-effect transistor, and the second end of the seventh resistor is connected to the non-inverting input of the second operational amplifier. The non-inverting input of the second operational amplifier serves as the third input of the linear voltage regulator circuit. The first end of the eighth resistor is connected to the second end of the seventh resistor, and the second end of the eighth resistor is grounded.

9. The linear regulator as described in claim 8, characterized in that, The ninth field-effect transistor is a P-type field-effect transistor.

10. A radio frequency power amplifier, characterized in that, The radio frequency power amplifier includes a linear regulator as described in any one of claims 1 to 9.

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