Chip packaging structure and packaging module

Abstract

According to the chip packaging structure and the packaging module provided by the utility model, a lead bonding process is replaced by a re-wiring layer and a flip-chip process, so that the heat-conducting property and the through-current capability of an existing packaging product are greatly optimized; the first double-sided copper-clad ceramic substrate is connected with the first lead frame, so that the first lead frame is wrapped in the plastic package body by the first double-sided copper-clad ceramic substrate, and the first double-sided copper-clad ceramic substrate can be used as an inner insulation structure of a package device; and the first double-sided copper-clad ceramic substrate and the heat dissipation substrate at the bottom layer are matched to serve as a double-sided heat dissipation structure of the packaging device, so that the packaging structure disclosed by the invention can be adaptive to the packaging structure in the shape of an existing transistor in appearance, and an internal insulation and double-sided heat dissipation structure is additionally arranged, so that the heat dissipation performance of the packaging structure is greatly improved; the requirements of high power, high voltage and high current on rapid heat dissipation of the device are met; according to the invention, the design of the first lead frame better embodies the flexibility of the packaging design, so as to adapt to the omnibearing requirements of packaging miniaturization, different sizes and diversification.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor packaging, and in particular to a chip packaging structure and a packaging module. BACKGROUND

[0002] Traditional chip packaging often uses a wire bonding process to achieve electrical connection between the chip and the exposed pins. However, the current-carrying capacity of the package is limited by factors such as solder window size, wire diameter and length, wire material, frame thickness, frame pin size, etc., making it difficult for the wire bonding process to meet the reliability requirements of long-time, high-voltage, large-current, and strong heat dissipation of high-power devices.

[0003] Therefore, flip chip packaging technology has emerged. Flip chip packaging technology is a packaging technology that connects a chip to a carrier. Flip chip packaging technology replaces the traditional wire bonding process and has the advantages of stronger current-carrying capacity, lower parasitic inductance, and superior heat dissipation performance. However, existing flip chip packaging is small in size. If the size of the chip is increased to improve product performance, it will exceed the packaging specifications. If it needs to be used in a high-voltage environment, the pin gap cannot meet the technical specifications of strong electrical clearance and large creepage distance. Therefore, existing flip chip packaging still remains in the development of medium and low voltage devices and has no obvious breakthrough and iteration. Secondly, existing flip chip packaging technology uses single-sided exposed solder metal parts for heat dissipation and heat dissipation, which has low heat dissipation efficiency, greatly limits the device heat dissipation speed, and thus affects the device operation performance and has the risk of internal burning.

[0004] Therefore, there is a need to develop a packaging structure with good electrical conductivity, thermal conductivity, and improved packaging design flexibility. INVENTION CONTENTS

[0005] The embodiments of the present disclosure provide a chip packaging structure and a packaging module for improving product packaging heat dissipation performance and current-carrying capacity and improving the flexibility of product packaging design.

[0006] The chip packaging structure provided by the embodiments of the present disclosure has the following specific solutions:

[0007] In one aspect, the present disclosure provides a chip packaging structure, comprising: a plastic package body, and a heat dissipation substrate, a chip, a redistribution layer, a conductive column, a first lead frame and a first double-sided copper clad ceramic substrate arranged in the plastic package body in sequence; wherein,

[0008] The chip is welded on one side of the heat dissipation substrate, the redistribution layer is connected with the chip, the conductive column is connected with the redistribution layer, the first lead frame includes a connecting structure and a pin extending from the side surface of the plastic package body to the outside of the plastic package body, and the connecting structure is connected with the conductive column; the first double-sided copper clad ceramic substrate is connected with the connecting structure.

[0009] The plastic package exposes a side of the heat dissipation substrate away from the chip and a side of the first double-sided copper clad ceramic substrate away from the heat dissipation substrate.

[0010] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, the heat dissipation substrate is a second lead frame, and the chip is welded on one side of a conductive base island of the second lead frame.

[0011] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, the heat dissipation substrate is a second double-sided copper clad ceramic substrate.

[0012] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, the second double-sided copper clad ceramic substrate comprises a first ceramic substrate and a first copper layer and a second copper layer located on opposite sides of the first ceramic substrate.

[0013] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, the redistribution layer comprises a plurality of metal blocks, and each metal block is connected with at least one conductive column.

[0014] The first lead frame comprises a plurality of connection structures corresponding to each metal block, and a pin connected with each connection structure; the connection structure comprises a connection part connected with the conductive column corresponding to the metal block at the corresponding position.

[0015] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, the first double-sided copper clad ceramic substrate comprises a second ceramic substrate and a third copper layer and a fourth copper layer located on opposite sides of the second ceramic substrate, and the third copper layer comprises a patterned copper layer corresponding to the connection structure, and the copper layer is connected with the connection structure.

[0016] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, further comprising: a first dielectric layer between the chip and the redistribution layer, a second dielectric layer between the redistribution layer and the conductive column, and a solder between the conductive column and the first lead frame.

[0017] The redistribution layer is connected with the chip through a via hole penetrating the first dielectric layer, the conductive column is connected with the redistribution layer through a via hole penetrating the second dielectric layer, and the connection structure is connected with the conductive column through the solder.

[0018] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, the heat dissipation substrate and the plastic package have a first through hole in the edge area.

[0019] In some embodiments, in the chip package structure provided by the embodiments of the present disclosure, the material of the redistribution layer is copper, the conductive column is a copper column or a solder column, the material of the first lead frame is copper, and the material of the plastic package is epoxy resin.

[0020] In another aspect, the embodiments of the present disclosure provide a package module, which comprises the chip package structure provided by the embodiments of the present disclosure, and the first through hole is arranged at the edge area of the heat dissipation substrate and the plastic package.

[0021] In some embodiments, in the package module provided by the embodiments of the present disclosure, further comprising: a heat sink arranged on the side of the first double-sided copper-clad ceramic substrate and the plastic package away from the heat dissipation substrate, and a PCB board arranged on the side of the heat dissipation substrate away from the chip;

[0022] The pin is connected with the PCB board, the first through hole further penetrates the PCB board and the heat sink, and the PCB board, the heat dissipation substrate, the plastic package and the heat sink are fixed by a first bolt arranged in the first through hole.

[0023] In some embodiments, in the package module provided by the embodiments of the present disclosure, the number of the chip package structures is at least two, and the at least two chip package structures share the same PCB board and share the same heat sink. The PCB board and the heat sink have a second through hole in the area between the two chip package structures, and the two chip package structures are fixed by a second bolt arranged in the second through hole.

[0024] The beneficial effects of the present disclosure are as follows:

[0025] This disclosure provides a chip packaging structure and packaging module. By connecting the chip to the bottom heat dissipation substrate, the chip to the redistribution layer, the redistribution layer to the conductive pillars, and the conductive pillars to the upper first lead frame, the pins of the first lead frame extend out of the plastic package and can serve as I / O ports of the packaged device. Therefore, this disclosure uses the redistribution layer and flip-chip process to replace the traditional wire bonding process, which greatly optimizes the thermal conductivity and current carrying capacity of existing chip packaging products. Furthermore, the first double-sided copper-clad ceramic substrate of this disclosure is connected to the upper first lead frame. In this way, the first double-sided copper-clad ceramic substrate encapsulates the first lead frame within the molding compound. On one hand, the first double-sided copper-clad ceramic substrate serves as the internal insulation structure of the packaged device; on the other hand, the top layer of the first double-sided copper-clad ceramic substrate, together with the bottom heat dissipation substrate, forms a double-sided heat dissipation structure for the packaged device. Therefore, the chip packaging structure provided by this disclosure can be adapted to the appearance of existing transistor-shaped packaging structures. Moreover, by adding internal insulation and a double-sided heat dissipation structure to the transistor-shaped packaging structure, the heat dissipation performance of the chip packaging structure is greatly improved, meeting the requirements of high power, high voltage, and high current for rapid heat dissipation of devices. In addition, the design of the upper first lead frame in the chip packaging structure provided by this disclosure better reflects the flexibility of the packaging design, adapting to the comprehensive needs of miniaturization, different sizes, and diversified market demands. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram of yet another chip packaging structure provided in this disclosure embodiment;

[0028] Figure 3 This is a planar schematic diagram of the second lead frame;

[0029] Figure 4 This is a planar schematic diagram of the first lead frame;

[0030] Figure 5 This is a planar schematic diagram of the third copper layer;

[0031] Figure 6 This is a planar schematic diagram of the fourth copper layer;

[0032] Figure 7 This is yet another schematic diagram of a chip packaging structure provided in an embodiment of the present disclosure;

[0033] Figure 8 for Figure 7 The diagram shows a top view of the chip packaging structure.

[0034] Figure 9Another schematic view of the chip packaging structure provided by the embodiment of the present disclosure is shown in FIG. 6;

[0035] Figure 10 A front view of the chip packaging structure is shown in FIG. 7; Figure 9

[0036] Figure 11 A front view of the chip packaging structure is shown in FIG. 7; Figure 9

[0037] Figure 12 Another schematic view of the packaging module provided by the embodiment of the present disclosure is shown in FIG. 8;

[0038] Figure 13 Another schematic view of the packaging module provided by the embodiment of the present disclosure is shown in FIG. 8;

[0039] Figure 14 A top view of the packaging module provided by the embodiment of the present disclosure is shown in FIG. 9;

[0040] Figure 15A A front view of the chip packaging structure is shown in FIG. 7; Figure 9

[0041] Figure 15B Another schematic view of the chip packaging structure in the packaging process is shown in FIG. 10; Figure 9

[0042] Another schematic view of the chip packaging structure in the packaging process is shown in FIG. 10; Figure 15C Figure 9 Another schematic view of the chip packaging structure in the packaging process is shown in FIG. 10;

[0043] Figure 15D Figure 9 Another schematic view of the chip packaging structure in the packaging process is shown in FIG. 10;

[0044] Figure 15E Another schematic view of the chip packaging structure in the packaging process is shown in FIG. 10; Figure 9

[0045] Another schematic view of the chip packaging structure in the packaging process is shown in FIG. 10; Figure 15F Figure 9 Another schematic view of the chip packaging structure in the packaging process is shown in FIG. 10;

[0046] Figure 16 A structure example of the second lead frame is shown in FIG. 11;

[0047] Figure 17 A structure example of the first lead frame is shown in FIG. 12. DETAILED DESCRIPTION

[0048] ​​​​​​For the purposes of the present disclosure, the goals, technical solutions, and advantages of the embodiments will be more clearly understood from the following description of the embodiments of the present disclosure, taken in conjunction with the accompanying drawings. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, and the like are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. A sharp angle illustrated can typically be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region that is to be constructed and / or manufactured. Rather, the shapes are intended to illustrate the general location of the region and the relative proximity or distance between regions. Similarly, the same or similar reference numerals are used to represent the same or similar elements or components throughout the description of the figures. To keep the following description of embodiments of the present disclosure clear and concise, detailed descriptions of known functions and constructions are omitted from the present disclosure.

[0049] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The use of the terms "first", "second", and the like do not imply any order, quantity, or importance, but are used to distinguish one element from another. The terms "include", "comprise", and the like are used synonymously with the term "comprising" and are intended to mean the open-ended term "comprising" and not the closed term "consisting of". The terms "connected", "coupled", and the like are not limited to direct or physical connections or couplings, but can include indirect or wireless connections or couplings. The terms "inner", "outer", "upper", "lower", and the like are used for clarity and example only and not by way of limitation. The relative position of elements can change when the absolute position of the described object changes.

[0050] In the following description, when a component or layer is referred to as "on" or "connected to" another component or layer, the component or layer may be directly on or directly connected to the other component or layer, or there may be intermediate components or intermediate layers. When a component or layer is referred to as "located on one side of" another component or layer, the component or layer may be directly on or directly connected to the other component or layer, or there may be intermediate components or intermediate layers. However, when a component or layer is referred to as "directly on" or "directly connected to" another component or layer, there are no intermediate components or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0051] This disclosure provides a chip packaging structure, such as... Figure 1 and Figure 2 As shown, it includes: a molding compound 1, and a heat dissipation substrate 2, a chip 3, a redistribution layer 4, conductive pillars 5, a first lead frame 6, and a first double-sided copper-clad ceramic substrate 7, which are sequentially stacked within the molding compound 1; specifically, the molding compound 1 can be made of epoxy resin, the chip 3 can be a SiC or GaN-based power device, the redistribution layer 4 can be made of copper, the conductive pillars 5 can be copper pillars or solder pillars, and the first lead frame 6 can be made of copper; wherein...

[0052] Chip 3 is soldered to one side of heat dissipation substrate 2, redistribution layer 4 is connected to chip 3, conductive pillar 5 is connected to redistribution layer 4, first lead frame 6 includes connection structure 61 and pins 62 extending from the side of molded body 1 to the outside of molded body 1, connection structure 61 is connected to conductive pillar 5; first double-sided copper-clad ceramic substrate 7 is connected to connection structure 61.

[0053] The molding compound 1 exposes the side of the heat dissipation substrate 2 away from the chip 3 and the side of the first double-sided copper-clad ceramic substrate 7 away from the heat dissipation substrate 2.

[0054] The chip packaging structure provided in this disclosure connects the chip to a bottom heat dissipation substrate, the chip to a redistribution layer, the redistribution layer to conductive pillars, and the conductive pillars to an upper first lead frame. The pins of the first lead frame extend out of the plastic package and can serve as I / O ports for the packaged device. Therefore, this disclosure uses a redistribution layer and flip-chip technology to replace the traditional wire bonding process, greatly optimizing the thermal conductivity and current carrying capacity of existing chip packaging products. Furthermore, the first double-sided copper-clad ceramic substrate is connected to the upper first lead frame, thus encapsulating the first lead frame within the plastic package. On one hand, the first double-sided copper-clad ceramic substrate serves as the internal insulation structure of the packaged device; on the other hand, the top first double-sided copper-clad ceramic substrate, combined with the bottom heat dissipation substrate, forms a double-sided heat dissipation structure for the packaged device. Therefore, the chip packaging structure provided in this disclosure can be adapted to the appearance of existing transistor-shaped packaging structures. Moreover, by adding internal insulation and a double-sided heat dissipation structure to the transistor-shaped packaging structure, the heat dissipation performance of the chip packaging structure is greatly improved, meeting the requirements for rapid heat dissipation of devices under high power, high voltage, and high current. In addition, the design of the first lead frame in the upper layer of the chip packaging structure provided in this disclosure can better reflect the flexibility of the packaging design, so as to adapt to the all-round needs of packaging miniaturization, different sizes and diversified market demands.

[0055] Specifically, the chip packaging structure and process provided in this disclosure can meet more stringent reliability and harsher working environment requirements, thereby demonstrating its strong thermal conduction (heat conduction and heat dissipation) and current carrying capacity to meet the development trend of high requirements for packaging technology of third-generation semiconductor (SiC&GaN) power devices; and the chip packaging structure provided in this disclosure can be matched with MSL1 packaging requirements, with higher reliability performance.

[0056] In some embodiments, in the chip packaging structure provided in the present disclosure, such as Figure 1 As shown, the heat dissipation substrate 2 can be a second lead frame, such as... Figure 3 As shown, Figure 3 This is a planar schematic diagram of the second lead frame, which includes a conductive base island 21, with the chip 3 soldered to one side of the conductive base island 21. In this way, the bottom second lead frame, together with the top first double-sided copper-clad ceramic substrate 7, forms a double-sided heat dissipation structure for the packaged device, greatly improving the heat dissipation performance of the chip package structure and meeting the requirements of high power, high voltage, and high current for rapid heat dissipation of the device. For packaged products with different molding thicknesses and sizes, this disclosure can improve heat dissipation performance by 10% to 30%.

[0057] Optionally, the second lead frame is made of copper, and the conductive base island can be rectangular in shape.

[0058] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, as shown in Figure 2 The heat dissipation substrate 2 can be a second double-sided copper clad ceramic substrate, which includes a first ceramic substrate 22 and a first copper layer 23 and a second copper layer 24 located on opposite sides of the first ceramic substrate 22. In this way, the second double-sided copper clad ceramic substrate on the bottom layer and the first double-sided copper clad ceramic substrate 7 on the top layer can realize complete insulation inside the package. For example, when the chip 3 of the present disclosure is a GaN-based lateral conduction device, although the back surface of the chip 3 close to the heat dissipation substrate 2 is not conductive, there will actually be a small amount of leakage. Therefore, the second double-sided copper clad ceramic substrate of the present disclosure can prevent leakage.

[0059] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, as shown in Figure 1 and Figure 2 The redistribution layer 4 can include a plurality of metal blocks, and each metal block is connected with at least one conductive pillar 5. In this way, the redistribution layer 4 can re-arrange and combine the scattered same-polarity pads on the side of the chip 3 away from the heat dissipation substrate 2 into larger pads, facilitating subsequent soldering.

[0060] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, as shown in Figure 1 , Figure 2 and Figure 4 As shown in Figure 4 , it is a plan view of the first lead frame 6. The first lead frame 6 can include a plurality of connection structures 61 corresponding to each metal block of the redistribution layer 4, and a pin 62 connected with each connection structure 61. The connection structure 61 can include a connection part 611 connected with each conductive pillar 5 in the corresponding position. Specifically, the connection structure 61 of the first lead frame 6 usually needs to cooperate with the layout of the conductive pillar 5, that is, the same-polarity conductive pillars 5 connected with the same metal block of the redistribution layer 4 are one-to-one corresponding to the connection part 611 of the same connection structure 61 and are soldered.

[0061] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, as shown in Figure 1 , Figure 2 and Figure 4 The number of pins 62 can be flexibly selected according to actual needs. The embodiments of the present disclosure take five pins 62 as an example.

[0062] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, as shown in Figure 1 and Figure 2As shown, the first double-sided copper-clad ceramic substrate 7 includes a second ceramic substrate 71 and a third copper layer 72 and a fourth copper layer 73 located on opposite sides of the second ceramic substrate 71, and the second ceramic substrate 71 can play an insulating role as an interlayer. Figure 5 and Figure 6 As shown, Figure 5 is a plan view of the third copper layer 72, Figure 6 is a plan view of the fourth copper layer 73, and in order to distinguish the chip electrodes, the third copper layer 72 connected with the first lead frame 6 needs to form corresponding patterns according to the structure of the first lead frame 6, and the fourth copper layer 73 can be a full-surface copper without patterning, for example, the third copper layer 72 includes a patterned copper cladding 721 corresponding to the connection structure 61, and the copper cladding 721 is connected with the connection structure 61.

[0063] In some embodiments, in the above chip packaging structure provided by the embodiments of the present disclosure, as shown in Figure 7 and Figure 8 As shown, Figure 7 is another schematic view of the chip packaging structure provided by the embodiments of the present disclosure, Figure 8 is a top view of the chip packaging structure as shown in Figure 7 is a top view of the chip packaging structure as shown in Figure 7 is to show that one metal block of the redistribution layer 4 is connected with the plurality of conductive pillars 5 and the patterned copper cladding 721 structure of the third copper layer 72.

[0064] In some embodiments, in the above chip packaging structure provided by the embodiments of the present disclosure, as shown in Figure 1 and Figure 2 As shown, the chip packaging structure further includes a first dielectric layer 8 between the chip 3 and the redistribution layer 4, a second dielectric layer 9 between the redistribution layer 4 and the conductive pillar 5, and a solder 10 between the conductive pillar 5 and the first lead frame 6; optionally, the first dielectric layer 8 and the second dielectric layer 9 can both be polymer films, and the first dielectric layer 8 and the second dielectric layer 9 can play a buffering and insulating role as an interlayer.

[0065] In some embodiments, in the above chip packaging structure provided by the embodiments of the present disclosure, as shown in Figure 1 and Figure 2 As shown, the redistribution layer 4 is connected with the chip 3 through a via penetrating the first dielectric layer 8, the conductive pillar 5 is connected with the redistribution layer 4 through a via penetrating the second dielectric layer 9, and the connection structure 61 of the first lead frame 6 is connected with the conductive pillar 5 through the solder 10. In this way, the electrical connection between the chip 3 and the external circuit can be realized.

[0066] Optionally, the solder 10 can be an Ag layer formed by a silver sintering process, and the solder 10 can also be a tin paste.

[0067] In some embodiments, in the chip packaging structure provided by the embodiments of the present disclosure, as shown in Figures 9-11 , Figure 9 another schematic view of the chip packaging structure provided by the embodiments of the present disclosure, Figure 10 is shown, Figure 9 a rear view of the chip packaging structure shown in Figure 11 a front view of the chip packaging structure shown in Figure 9 , the heat dissipation substrate 2 (for example, a second lead frame) and the plastic package 1 have a first through hole H1 in the edge area. The first through hole H1 can be used when multiple chip packaging structures are connected, or a large heat sink can be shared to fix multiple chip packaging structures.

[0068] Based on the same utility model concept, the embodiments of the present disclosure also provide a packaging module, which includes the above-mentioned chip packaging structure provided by the embodiments of the present disclosure, as shown in Figure 12 , the heat dissipation substrate 2 (for example, a second lead frame) and the plastic package 1 have a first through hole H1 in the edge area.

[0069] In some embodiments, in the packaging module provided by the embodiments of the present disclosure, as shown in 12, it further includes a heat sink 20 located on the side of the first double-sided copper clad ceramic substrate 7 and the plastic package 1 away from the heat dissipation substrate 2 (for example, a second lead frame), and a PCB board 30 (printed circuit board) located on the side of the heat dissipation substrate 2 away from the chip 3;

[0070] , the pin 62 and the PCB board 30 can be connected by using a patch welding process, the first through hole H1 also penetrates the PCB board 30 and the heat sink 20, and the PCB board 30, the heat dissipation substrate 2, the plastic package 1 and the heat sink 20 are fixed by the first bolt 40 located in the first through hole H1.

[0071] In some embodiments, in the packaging module provided by the embodiments of the present disclosure, as shown in 13 and Figure 14 , Figure 13 another schematic view of the packaging module provided by the embodiments of the present disclosure, Figure 14 a top view of the packaging module provided by the embodiments of the present disclosure, the number of chip packaging structures can be at least two, and the at least two chip packaging structures share the same PCB board 30 and the same heat sink 20, the PCB board 30 and the heat sink 20 have a second through hole H2 in the area between the two chip packaging structures, and the two chip packaging structures are fixed by the second bolt 50 located in the second through hole H2.

[0072] Next, taking the structure shown in Figure 9 as an example, the packaging process of the chip packaging structure provided by the embodiments of the present disclosure is described, and the specific steps are as follows:

[0073] (1), asFigure 15A Wafer (chip 3) cleaning: The wafer raw material is subjected to ore-clean and SRD pretreatment, and then plasma cleaning is performed to remove impurities on the wafer surface.

[0074] (2), as shown in Figure 15B Manufacture of redistribution layer 4 (copper material) and conductive pillar 5 (copper pillar or soldering tin pillar): The same polarity pads on the upper surface of chip 3 are redistributed and combined into larger pads through redistribution layer 4, which facilitates subsequent soldering. The conductive pillar 5 serves as a bridge for electrical connection between the electrodes of chip 3 after redistribution through redistribution layer 4 and the upper layer of first lead frame (as the lead I / O port of the packaged finished device).

[0075] (3), as shown in Figure 15C The chip 3 is soldered to the heat dissipation substrate 2 (i.e. the second lead frame) using a silver sintering process. The second lead frame is usually rectangular in shape and mainly made of copper. The structure of the second lead frame can be designed according to actual needs, as shown in Figure 16 Figure 16 The structure of the second lead frame is shown in the figure. The second lead frame usually includes a conductive base island 21 and a first connecting rib 25. The conductive base island 21 is the area for soldering the chip 3, and the first connecting rib 25 is the connecting area for increasing the rigidity of the frame. In the subsequent cutting / cutting process, the first connecting rib 25 will be cut off to separate the packaged device into single chip packaging structure.

[0076] (4), as shown in Figure 15D The conductive pillar 5 is soldered to the first lead frame 6 using a silver sintering process. The first lead frame 6 usually needs to cooperate with the layout of the conductive pillar 5. The first lead frame 6 can be designed according to actual needs, as shown in Figure 17 Figure 17 The structure of the first lead frame 6 is shown in the figure. The first lead frame 6 usually includes a connecting structure 61, a pin 62 and a second connecting rib 63 (reinforcing rib). The conductive pillars 5 of the same polarity are soldered to the same connecting structure 61, and the connecting structures 61 of different polarities are connected through the second connecting rib 63.

[0077] (5), as shown in Figure 15E The first double-sided copper clad ceramic substrate 7 is soldered to the first lead frame 6 using a silver sintering process. The first double-sided copper clad ceramic substrate 7 serves as an insulating interlayer. In order to distinguish the electrodes of chip 3, the soldering surface of the first double-sided copper clad ceramic substrate 7 and the first lead frame 6 needs to form a corresponding pattern according to the structure of the first lead frame 6. The side of the first double-sided copper clad ceramic substrate 7 away from the heat dissipation substrate 2 is a whole copper surface without patterning.

[0078] (6), as shown in Figure 15F Figure 15E ​​​The shown package functional area completely wraps the formed plastic package 1, and the plastic package 1 exposes the side of the heat dissipation substrate 2 away from the chip 3 and the side of the first double-sided copper clad ceramic substrate 7 away from the heat dissipation substrate 2.

[0079] (7), as Figure 9 shown, the second lead frame of the bottom layer is cut, and the first lead frame 6 of the upper layer is cut and formed into a rib, that is, the second rib 63 structure is cut off, and the pin 62 extended to the outside of the plastic package 1 is bent and formed, that is, the packaged finished device is separated into a single chip package structure.

[0080] Through the above steps (1)-(7), the Figure 9 shown chip package structure

[0081] The chip package structure and the packaging module provided by the embodiment of the present disclosure, by setting the chip connected with the heat dissipation substrate of the bottom layer, the chip connected with the redistribution layer, the redistribution layer connected with the conductive column, the conductive column connected with the first lead frame of the upper layer, and the pin of the first lead frame extended out of the plastic package as the lead-out I / O port of the packaged device, therefore, the present disclosure adopts the redistribution layer and the flip technology to replace the traditional lead bonding technology, which greatly optimizes the heat dissipation performance and flow capacity of the existing chip package product. Moreover, the first double-sided copper clad ceramic substrate of the present disclosure is connected with the first lead frame of the upper layer, so that the first double-sided copper clad ceramic substrate wraps the first lead frame in the plastic package, on the one hand, the first double-sided copper clad ceramic substrate can be used as the internal insulation structure of the packaged device, and on the other hand, the first double-sided copper clad ceramic substrate of the top layer and the heat dissipation substrate of the bottom layer are matched as the double-sided heat dissipation structure of the packaged device, therefore, the chip package structure provided by the present disclosure can adapt to the existing transistor-shaped package structure in appearance, and the internal insulation and double-sided heat dissipation structure are added on the basis of the transistor-shaped package structure, which greatly improves the heat dissipation performance of the chip package structure and meets the requirements of high power, high voltage and strong current for rapid heat dissipation of the device. In addition, the design of the first lead frame of the upper layer in the chip package structure provided by the present disclosure can better reflect the flexibility of the packaging design to adapt to the full range of requirements of packaging miniaturization, different sizes and market demand diversification.

[0082] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the present disclosure.

[0083] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A chip package structure, characterized by, The chip package structure comprises: a plastic package body, and a heat dissipation substrate, a chip, a redistribution layer, a conductive column, a first lead frame and a first double-sided copper clad ceramic substrate which are sequentially stacked in the plastic package body; wherein the chip is welded on one side of the heat dissipation substrate, the redistribution layer is connected with the chip, the conductive column is connected with the redistribution layer, the first lead frame comprises a connecting structure and a pin which extends from the side of the plastic package body to the outside of the plastic package body, and the connecting structure is connected with the conductive column; the first double-sided copper clad ceramic substrate is connected with the connecting structure; the plastic package body exposes one side of the heat dissipation substrate away from the chip and one side of the first double-sided copper clad ceramic substrate away from the heat dissipation substrate.

2. The chip package structure of claim 1, wherein, The heat dissipation substrate is a second lead frame, and the second lead frame comprises a conductive base island, and the chip is welded on one side of the conductive base island.

3. The chip package structure of claim 1, wherein, The heat dissipation substrate is a second double-sided copper clad ceramic substrate.

4. The chip package structure of claim 3, wherein, The second double-sided copper clad ceramic substrate comprises a first ceramic substrate and a first copper layer and a second copper layer located on opposite sides of the first ceramic substrate.

5. The chip package structure of claim 1, wherein, The redistribution layer comprises a plurality of metal blocks, and each metal block is connected with at least one conductive column; the first lead frame comprises a plurality of connecting structures corresponding to each metal block and the pin connected with each connecting structure; the connecting structure comprises a connecting part connected with the conductive column corresponding to the metal block at the corresponding position.

6. The chip package structure of claim 5, wherein, The first double-sided copper clad ceramic substrate comprises a second ceramic substrate and a third copper layer and a fourth copper layer located on opposite sides of the second ceramic substrate, the third copper layer comprises a patterned copper clad corresponding to the connecting structure, and the copper clad is connected with the connecting structure.

7. The chip package structure of any one of claims 1-6, wherein, Further comprising: a first dielectric layer between the chip and the redistribution layer, a second dielectric layer between the redistribution layer and the conductive column, and solder between the conductive column and the first lead frame; wherein the redistribution layer is connected with the chip through a via penetrating the first dielectric layer, the conductive column is connected with the redistribution layer through a via penetrating the second dielectric layer, and the connecting structure is connected with the conductive column through the solder.

8. The chip package structure of any one of claims 1-6, wherein, The heat dissipation substrate and the plastic package body have a first through hole in the edge area.

9. The chip package structure of any one of claims 1-6, wherein, The material of the redistribution layer is copper, the conductive column is a copper column or a solder column, the material of the first lead frame is copper, and the material of the plastic package body is epoxy resin.

10. A packaging module, characterized by The chip package structure comprises:

11. The package module of claim 10, wherein the first and second package modules are mounted on a same substrate. a chip package structure as claimed in any one of claims 1-9, and the heat dissipation substrate and the plastic package body have a first through hole in the edge area. Further comprising: a heat sink located on the side of the first double-sided copper clad ceramic substrate and the plastic package body away from the heat dissipation substrate, and a PCB board located on the side of the heat dissipation substrate away from the chip; wherein the pin is connected with the PCB board, the first through hole further penetrates the PCB board and the heat sink, and the PCB board, the heat dissipation substrate, the plastic package body and the heat sink are fixed by a first bolt located in the first through hole.

12. The package module of claim 11, wherein the first and second package modules are mounted on a single substrate. The number of the chip package structures is at least two, at least two of the chip package structures share the same PCB board and share the same heat sink, the PCB board and the heat sink have a second through hole in the area between the two chip package structures, and the two chip package structures are fixed by a second bolt located in the second through hole.

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