Semiconductor test structure and semiconductor device structure
By using a semiconductor test structure to test the resistance of the active region, the problem of difficulty in monitoring the health of the gate pitch is solved, thereby improving the nickel sputtering effect and optimizing the chip design.
Patent Information
- Application Number
- CN202422920561.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2034-11-28
AI Technical Summary
In existing technologies, as chip integration increases, the gate pitch decreases, leading to a weakening of nickel sputtering effect, the inability to form NiSi, and limited ion implantation effect. Traditional PSE health assessment methods are complex and difficult to monitor gate pitch health.
A semiconductor test structure is provided, including a substrate, a gate group, and a conductive group. It is connected to an active region via a tester, and the resistance value of the active region is tested using the gate structure and conductive parts to determine the PSE health and optimize the chip design and manufacturing process.
By detecting the resistance value of the active region, the health level of the gate spacing (PSE) can be accurately assessed, solving the problem of difficulty in monitoring the health level of the gate spacing in traditional technologies, improving the nickel sputtering effect, and optimizing the chip design and manufacturing process.
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Figure CN223598723U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of semiconductor, in particular to semiconductor test structure and semiconductor device structure. BACKGROUND
[0002] With the development of semiconductor technology, chip tends to miniaturization, centralization development. With the improvement of chip integration, the gate spacing of transistor is also reduced, however, when the gate spacing is reduced, the effect of nickel sputtering is weakened, which will lead to NiSi unable to form, and the ion implantation effect is limited, leading to the gate region ion concentration injection becomes light.
[0003] In order to determine the minimum gate spacing allowed by the active area, the PSE (Poly Space Effect) health degree is used to evaluate in the traditional technology, but the evaluation method is complex. UTILITY MODEL CONTENT
[0004] Therefore, it is necessary to provide a semiconductor test structure and semiconductor device structure for the problem of complex evaluation method of PSE health degree.
[0005] In a first aspect, the application provides a semiconductor test structure for testing an active area, the semiconductor test structure comprising: a substrate; a gate group arranged on the substrate, the gate group comprising a plurality of gate structures, the plurality of gate structures being arranged; and a conductive group arranged on the substrate, the conductive group comprising a first conductive part and a second conductive part, the first conductive part being used to connect a first end of the active area and a first end of a testing machine, and the second conductive part being used to connect a second end of the active area and a second end of the testing machine.
[0006] In one embodiment, the gate structure has an extension direction, the extension directions of the plurality of gate structures are parallel to each other, and the arrangement direction of the plurality of gate structures is perpendicular to the extension direction of the gate structure. In this way, the gate structures are arranged on the substrate in sequence, which is convenient for placing in the test position and adjusting the position.
[0007] In one embodiment, the distance between the two adjacent gate structures in the gate group is equal. In this way, the test structure can be used to test a plurality of active areas.
[0008] In one embodiment, the active region is a first conductive type doped region or a second conductive type doped region formed by ion implantation. The active region can be an N-type ion doped region or a P-type ion doped region. In one embodiment, the gate structure includes a reference gate, a sidewall formed on a sidewall of the reference gate, and a dielectric layer formed on a bottom of the reference gate. In this way, the gate structure on the semiconductor test structure is consistent with a subsequently formed gate structure on the active region, improving the accuracy of PSE health determination.
[0009] In one embodiment, the first conductive part and / or the second conductive part has a height equal to a height of the gate group. In this way, when the semiconductor test structure is placed in a test position of a chip, the gate structure is on the active region, and the first conductive part and the second conductive part are electrically connected to the active region, facilitating resistance value testing of the active region by a test machine.
[0010] In one embodiment, the first conductive part and / or the second conductive part includes a conductive member and a conductive contact disposed on the conductive member, the conductive member being at least partially electrically connected to the active region, and the conductive contact being used to connect the test machine. The test machine is electrically connected to the active region through the conductive contact, avoiding direct contact between the test machine and the active region to prevent damage to the active region.
[0011] In one embodiment, the active region includes a P-type doped region or an N-type doped region.
[0012] In one embodiment, a space is formed between two adjacent gate structures, and the number of the conductive groups is a plurality, and the first conductive part and the second conductive part in one conductive group are disposed on two sides of one space, respectively. In this way, the active region can be placed in any space, and the conductive group in any space can be electrically connected to the active region.
[0013] In a second aspect, the application further provides a semiconductor device structure, including: the semiconductor test structure; and a test machine for testing resistance of the active region.
[0014] The semiconductor test structure includes a gate group and a conductive group, the gate group includes a plurality of gate structures, and when the active region is tested, the semiconductor test structure is placed on the active region so that the active region is located between two adjacent gate structures. In this way, the gate structure will affect the resistance value of the active region, and the conductive group is connected with the active region and the tester at the same time. When the resistance value of the active region is tested by the tester, the affected degree of the active region can be judged according to the measured resistance value, the PSE health degree can be judged, and then the chip design and manufacturing process can be optimized. The unexpected beneficial effects of the present application are that: through the semiconductor test structure of the embodiment, the PSE health degree of each position of the wafer can be detected by placing the semiconductor test structure at different positions of the wafer, the problem that the gate spacing health degree is difficult to monitor in the prior art is solved, and then the nickel sputtering effect is improved. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 It is a structural schematic diagram of the semiconductor test structure in one embodiment.
[0016] Figure 2 It is a curve diagram of the resistance value of the active region changing with the gate spacing in a nickel sputtering process in one embodiment.
[0017] Figure 3 It is a curve diagram of the resistance value of the active region changing with the gate spacing in a nickel sputtering process in one embodiment.
[0018] Figure 4 It is a side view of the semiconductor test structure and the active region position in one embodiment.
[0019] BRIEF DESCRIPTION OF DRAWINGS:
[0020] 10, active region; 11, substrate; 12, shallow trench isolation structure; 20, semiconductor test structure; 21, base; 22, gate group; 221, gate structure; 2211, reference gate; 2212, side wall; 2213, dielectric layer; 231, first conductive part; 232, second conductive part; 233, conductive contact; X, extension direction; Y, arrangement direction. DETAILED DESCRIPTION
[0021] In order to make the above-mentioned purposes, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below. In the following description, a large number of specific details are set forth in order to fully understand the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.
[0022] In the description of the utility model, it is understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the utility model.
[0023] In addition, the terms "first" and "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the utility model, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise specifically limited.
[0024] In the utility model, unless otherwise specifically defined and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrated; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the communication or interaction relationship between two elements, unless otherwise specifically limited. For ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.
[0025] In the utility model, unless otherwise specifically defined and limited, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact between the first and second features through intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.
[0026] It is to be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can be present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0027] The PSE of the field effect transistor as a layout parasitic effect has a very obvious influence on the threshold voltage, parasitic capacitance and saturation current. The PSE is the effect of the polysilicon gate pitch on the performance of the field effect transistor. With the decrease of the device size, the polysilicon gate pitch is also correspondingly reduced, and the adverse effect of the PSE on the device performance is more and more obvious, and therefore it is necessary to develop a kind of PSE degree after the gate structure is formed in the active area in the process.
[0028] Referring to Figure 1 , Figure 1 The utility model discloses a structure schematic diagram of semiconductor test structure 20 in one embodiment of the utility model, and the utility model discloses an embodiment provides semiconductor test structure 20 for testing active area 10, and semiconductor test structure 20 includes: base 21, gate group 22 is configured to base 21, and gate group 22 includes multiple gate structures 221, and multiple gate structures 221 are arranged, and conductive group is configured to base 21, and conductive group includes first conductive part 231 and second conductive part 232, and first conductive part 231 is used to connect the first end of active area 10 and the first end of testing machine, and second conductive part 232 is used to connect the second end of active area 10 and the second end of testing machine.
[0029] Exemplarily, base 21 can be silicon substrate, and gate structure 221 is formed on silicon substrate. Exemplarily, first conductive part 231 and second conductive part 232 can be conductive column deposited on silicon substrate, and the material can be tungsten, titanium nitride and the like.
[0030] Exemplarily, multiple gate structures 221 are formed on base 21, and multiple gate structures 221 are arranged, so that multiple gate structures 221 form intervals between each other, and any interval can be arranged on both sides of active area 10, facilitating resistance test of testing machine to active area 10.
[0031] Exemplarily, the test machine is a series of equipment for the automatic test of semiconductor chips. It is usually composed of multiple test function modules and performs test tasks through the control of an upper computer. For example, it is used for testing the functionality of semiconductor chips, including the combination of software and hardware. In the embodiment, the test machine is used for testing the resistance value of the active region 10. In addition, the test machine can also test the circuit function and electrical performance parameters of the semiconductor device (the chip to be tested), including direct current parameters (such as voltage and current), alternating current parameters (such as time, duty cycle, frequency, etc.), and functional tests.
[0032] When the active region 10 is tested, the gate group 22 is arranged on the active region 10, so that the active region 10 is located between two adjacent gate structures 221. The two gate structures 221 are arranged on both sides of the active region 10, forming a structure similar to a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). At this time, due to the existence of the gate structure, the two adjacent gate structures 221 will interfere with the resistance value of the active region 10, and the distance between the two gate structures 221 will affect the resistance value of the active region 10 differently. At the same time, the first conductive part 231 of the conductive group is connected to the first end of the active region 10 and the first end of the test machine, and the second conductive part 232 is connected to the second end of the active region 10 and the second end of the test machine. In this way, the test machine can apply a voltage to the active region 10 to test the resistance value of the active region 10, and then compare the measured resistance value with the theoretical value to determine the degree of influence of the active region 10, so as to determine the PSE health degree.
[0033] In the above semiconductor test structure 20, the gate group 22 and the conductive group are arranged on the substrate 21. The gate group 22 includes multiple gate structures 221. When the active region 10 is tested, the semiconductor test structure 20 is placed on the active region 10, so that the active region 10 is located between two adjacent gate structures 221. In this way, the gate structure 221 will affect the resistance value of the active region 10, and the conductive group is connected to the active region 10 and the test machine. When the test machine tests the resistance value of the active region 10, it can determine the degree of influence of the active region 10 according to the measured resistance value, determine the PSE health degree, and then optimize the chip design and manufacturing process. The unexpected beneficial effects of the embodiment are that the semiconductor test structure of the embodiment can detect the PSE health degree of each position of the wafer by being placed at different positions of the wafer, solve the problem that it is difficult to monitor the gate pitch health degree in the traditional technology, and thus help to improve the nickel sputtering effect.
[0034] For example, an active region refers to the area in a semiconductor device where an active device is used. It can be a well region or a region isolated by STI (Shallow Trench Isolation) to control current flow. Active regions primarily refer to MOSFETs, and different doping can form n-type or p-type active regions. An active region is divided into a source region and a drain region (with the same doping type). Before interconnection, the two active regions are indistinguishable. Optionally, active region 10 includes a P-type doped region or an N-type doped region.
[0035] See Figure 2 , Figure 2 The graph shows the variation of the active region resistance 10 with gate pitch under the same nickel sputtering process. Figure 2 It can be seen that when the gate pitch is large, such as greater than D-0.02μm, the resistance of the active region 10 changes very little. However, as the gate pitch decreases to a certain value, such as less than D-0.02μm, the resistance continuously increases with the decrease in gate pitch. This is because when the gate pitch is too small, the nickel sputtering process cannot form NiSi on the active region 10, resulting in an abnormal increase in the resistance of the active region 10. Therefore, it shows that by detecting the resistance value of the active region 10, it is possible to determine whether NiSi has been formed on the active region 10, and further determine the thickness of the NiSi formation. Here, D on the horizontal axis represents the value of DRC (Design Rule Check).
[0036] See Figure 3 , Figure 3 The graph shows the relationship between the resistance of the active region 10 and the gate pitch during a nickel-free sputtering process. As the gate pitch decreases, the implanted ion concentration gradually decreases, leading to a decrease in the conductivity of the active region 10 and a gradual increase in its resistance. Furthermore, as the gate pitch decreases sequentially from D+0.04μm to D-0.04μm, the resistance of the active region 10 increases sequentially. This indicates that the gate pitch affects the resistance of the active region 10, and there is a certain functional relationship between the gate pitch and the active region 10. By detecting the resistance of the active region 10, the degree of influence on the active region 10 can be reflected. In this graph, D on the horizontal axis represents the DRC (Design Rule Check) value.
[0037] Therefore, the resistance value measured by the active region 10 can reflect the influence of the gate pitch on the active region 10. After determining the allowable resistance value range of the active region 10, the resistance value of the active region 10 obtained by the testing machine can be compared with the allowable resistance value range. If the measured resistance value is within the allowable resistance value range, it is considered that the gate pitch on the corresponding semiconductor test structure 20 is feasible. If the measured resistance value is outside the allowable resistance value range, it is considered that the requirement cannot be met and the semiconductor process needs to be optimized.
[0038] Continuing to refer to Figure 1 In an exemplary embodiment, the gate structure 221 has an extension direction X, the extension directions X of the plurality of gate structures 221 are parallel to each other, and the arrangement direction Y of the plurality of gate structures 221 is perpendicular to the extension direction X of the gate structure 221. The plurality of gate structures 221 are arranged in sequence along the arrangement direction Y, and a gap is formed between the adjacent two gate structures 221. The plurality of gate structures 221 form a plurality of gaps, and the active region 10 can be located in any formed gap, so as to evaluate the influence of the resistance value of the active region 10 between any adjacent gate structures 221.
[0039] The active region 10 is parallel to the gate structure 221 and located between the adjacent two gate structures 221. The first conductive part 231 and the second conductive part 232 are respectively located at the two ends of the active region 10. In this way, the active region 10 and the gate structure 221 form a structure similar to MOSFET, which can simulate the PSE health degree of the active region 10 after forming MOSFET.
[0040] In an exemplary embodiment, the pitch of the adjacent two gate structures 221 in the gate group 22 is equal. In this way, the semiconductor test structure can be placed at different positions of the wafer to monitor the performance of the active region 10 at different positions and reflect the PSE degree of different regions.
[0041] For example, a plurality of semiconductor test structures of different specifications can be provided to determine the test structure used according to the actual process. For example, three types of semiconductor test structures with gate structure 221 pitches of 40 nm, 50 nm and 60 nm are provided, and the gate pitch in the semiconductor process is designed to be 50 nm. The active region 10 can be tested by the gate structure 221 with a pitch of 50 nm. If the measured resistance value of the active region 10 is within the allowable resistance value range, it is considered that the gate pitch of 50 nm is feasible in the entire process. In another process, the active region 10 corresponds to a gate pitch of 60 nm, and the semiconductor test structure 20 with a gate pitch of 60 nm provided by the embodiment is used for testing.
[0042] In some embodiments, the active region is a first conductivity type doped region or a second conductivity type doped region formed by ion implantation. For example, the first conductivity type can be N-type, and the second conductivity type is P-type. The active region can be formed on the substrate by an ion implantation process.
[0043] See Figure 4 , Figure 4 A side view is shown in one embodiment of a semiconductor test structure 20 performing a resistance test on an active region 10. (See diagram below.) Figure 4 As shown, there is a gap between two adjacent gate structures 221, and the active region 10 is located below the gap, forming a structure similar to a MOSFET. Therefore, the spacing of the gate structures 221 interferes with the active region 10, affecting its resistance value. Furthermore, different spacings of the gate structures 221 result in different degrees of influence on the resistance value of the active region 10. The active region 10 is electrically connected to the conductive group. A tester is electrically connected to the active region 10 to test its resistance value, thereby assessing the degree of influence of the gate structure 221 spacing on the active region 10. This provides more accurate test results and helps optimize the chip design and manufacturing process.
[0044] For example, the gate structure 221 includes a reference gate 2211, sidewalls 2212 formed on the sidewalls of the reference gate 2211, and a dielectric layer 2213 formed on the bottom of the reference gate 2211. The gate in the semiconductor test structure 20 is different from the gate subsequently formed in the active region 10, and is therefore defined as the reference gate. Furthermore, considering that sidewalls are formed on both sides of the gate in subsequent gate processes, the semiconductor test structure in this embodiment also forms sidewalls on both sides of the reference gate. Thus, the gate structure 221 in the semiconductor test structure 20 is consistent with the gate subsequently formed in the active region 10, more accurately representing the influence of the gate structure 221 on the resistance value of the active region 10.
[0045] Exemplarily, the active region 10 is formed on the substrate 11, such as by ion implantation. Exemplarily, the shape of the substrate 11 can be any shape, such as circular, square, or rectangular, as long as the active region 10 can be formed. This embodiment does not specifically limit the shape of the substrate 11. Exemplarily, the semiconductor substrate 10 can be made of silicon, germanium, gallium arsenide (GaAs), silicon carbide (SiC), etc.
[0046] Multiple active regions 10 are separated by a shallow trench isolation structure 12. Exemplarily, the shallow trench isolation structure 12 is used to create isolation between the active regions 10, preventing mutual interference and crosstalk between electronic devices. In one feasible implementation, the shallow trench isolation structure 12 is fabricated by forming shallow, wide channels on a substrate using chemical vapor deposition or other methods, and then filling these channels with a specific insulating material. After filling, the channel surfaces are planarized.
[0047] Referring to Figure 4 In one example embodiment, the first conductive part 231 and / or the second conductive part 232 has a height equal to that of the gate group 22. In this way, when the semiconductor test structure 20 is placed at a designated position of the chip, the active region 10 is located at the interval between two adjacent gate structures 221, and the first conductive part 231 and the second conductive part 232 can be in contact with the active region 10, so that the tester can perform resistance testing on the active region 10.
[0048] In one example embodiment, the first conductive part 231 and / or the second conductive part 232 comprises a conductive member and a conductive contact 233 arranged on the conductive member, the conductive member is at least partially electrically connected to the active region 10, and the conductive contact 233 is used to connect the tester.
[0049] The tester is connected to the conductive member through the conductive contact 233, avoiding direct contact with the active region 10 and damaging the active region. In this way, the tester and the active region 10 are in conduction, and the tester can apply voltage / current to the active region 10 to test the resistance value of the active region 10.
[0050] In one example embodiment, the interval is formed between two adjacent gate structures 221, and the number of conductive groups is multiple, and the first conductive part and the second conductive part in one conductive group are arranged on both sides of one interval, respectively. In this way, the active region 10 is placed in any interval, and the tester can be in conduction with the active region 10, so as to test the resistance of the active region 10.
[0051] In addition, the application also provides a semiconductor device structure, comprising: a semiconductor test structure 20; and a tester, the tester is used to test the resistance of the active region 10. When testing the active region 10, the semiconductor test structure 20 is placed on the active region 10, so that the active region 10 is located at the interval between two adjacent gate structures 221. In this way, the gate structure 221 will affect the resistance value of the active region 10, and the conductive group simultaneously connects the active region 10 and the tester, and when the tester tests the resistance value of the active region 10, the affected degree of the active region 10 can be judged according to the measured resistance value, the PSE health degree can be judged, and the chip design and manufacturing process can be optimized. The unexpected beneficial effects of the application are: through the semiconductor test structure of the embodiment, the PSE health degree of each position of the wafer can be detected when the semiconductor test structure is placed at different positions of the wafer, the problem that it is difficult to monitor the gate interval health degree in the traditional technology is solved, and the nickel sputtering effect is improved.
[0052] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as the combination of the technical features does not exist in contradiction, it shall be considered as within the scope of the present disclosure.
[0053] The above-described embodiments only express several implementation manners of the present application, the description is relatively specific and detailed, but it shall not be understood as a limitation on the scope of the present application patent. It should be pointed out that, for ordinary skilled in the art, under the premise of not departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application patent shall be subject to the appended claims.
Claims
1. A semiconductor test structure, characterized by, A semiconductor test structure for testing an active region, the semiconductor test structure comprising: a substrate; a gate group configured on the substrate, the gate group comprising a plurality of gate structures arranged in a plurality of rows; a conductive group configured on the substrate, the conductive group comprising a first conductive part and a second conductive part, the first conductive part configured to connect a first end of the active region and a first end of a testing machine, the second conductive part configured to connect a second end of the active region and a second end of the testing machine.
2. The semiconductor test structure of claim 1, wherein, The gate structures have an extending direction, the extending directions of the gate structures are parallel to each other, and the arrangement direction of the gate structures is perpendicular to the extending direction of the gate structures.
3. The semiconductor test structure according to claim 1 or 2, characterized in that, The distance between two adjacent gate structures in the gate group is equal.
4. The semiconductor test structure of claim 1, wherein, The active region is a first conductive type doped region or a second conductive type doped region formed by ion implantation.
5. The semiconductor test structure of claim 1, wherein, The gate structure comprises a reference gate, a sidewall formed on a sidewall of the reference gate, and a dielectric layer formed on a bottom of the reference gate.
6. The semiconductor test structure of claim 1, wherein, The height of the first conductive part and / or the second conductive part is equal to the height of the gate group.
7. The semiconductor test structure of claim 1, wherein, The first conductive part and / or the second conductive part comprises a conductive member and a conductive contact configured on the conductive member, the conductive member is at least partially electrically connected to the active region, and the conductive contact is configured to connect the testing machine.
8. The semiconductor test structure of claim 1, wherein, The active region comprises a P-type doped region or an N-type doped region.
9. The semiconductor test structure of claim 1, wherein, The distance between two adjacent gate structures forms a gap, the number of the conductive groups is a plurality, and the first conductive part and the second conductive part in one conductive group are respectively configured on two sides of one gap.
10. A semiconductor device structure, characterized by, The semiconductor test structure of any one of claims 1-9; The testing machine is configured to test the resistance of the active region.