Image sensor pixel unit and electronic device

Abstract

The embodiment of the utility model discloses an image sensor pixel unit and electronic equipment, and the pixel unit comprises a photodiode, a reset transistor, a positive feedback transistor and a phase inverter. One end of the photodiode is grounded, and the other end of the photodiode is connected with the reset transistor and the input end of the phase inverter; the source end of the reset transistor is connected with a power signal, the drain end of the reset transistor is connected with the photodiode, and the grid end of the reset transistor is connected with a reset signal; the positive feedback transistor is connected with the photodiode in parallel, the drain end of the positive feedback transistor is connected with the connection node, the source end of the positive feedback transistor is grounded, and the grid end of the positive feedback transistor is connected with the output end of the phase inverter; the input end of the phase inverter is connected with the other end of the photodiode, and the output end of the phase inverter is connected with the gate end of the positive feedback transistor.

Description

Technical Field

[0001] This disclosure relates to the field of image sensor technology, and in particular to an image sensor pixel unit and electronic device. Background Technology

[0002] Image sensors have been widely used in digital cameras, mobile phones, medical devices, automobiles, drones, and machine recognition, especially with the rapid development of Complementary Metal-Oxide-Semiconductor (CMOS) image sensor technology, which has led to higher demands on the output image quality of image sensors. CMOS image sensors can be divided into two categories based on their signal acquisition methods: one method involves setting the exposure time for each pixel and then measuring the change in voltage signal; the second method involves setting the voltage change for each pixel and then measuring the exposure time, and this type of image sensor is called a pulse sequence image sensor.

[0003] In a pulse sequence image sensor, during continuous exposure, each pixel unit outputs a pulse signal when the photoelectric signal accumulates to a specific threshold, resetting the pixel to begin accumulating photoelectric signals again. The illumination intensity at each pixel unit can be expressed by the frequency of its emitted pulse signal. Utility Model Content

[0004] This disclosure provides an image sensor pixel unit and an electronic device.

[0005] In one aspect of this disclosure, an image sensor pixel unit is provided, including: a photodiode, a reset transistor, a positive feedback transistor, and an inverter;

[0006] One end of the photodiode is grounded, and the other end is connected to the input terminal of the reset transistor and the inverter.

[0007] The source terminal of the reset transistor is connected to the power supply signal, the drain terminal is connected to the photodiode, and the gate terminal is connected to the reset signal.

[0008] The positive feedback transistor is connected in parallel with the photodiode. The drain terminal of the positive feedback transistor is connected to the connection node, the source terminal is grounded, and the gate terminal is connected to the output terminal of the inverter. The connection node is the connection point between the photodiode and the reset transistor.

[0009] The input terminal of the inverter is connected to the other end of the photodiode, and the output terminal of the inverter is connected to the gate terminal of the positive feedback transistor.

[0010] Optionally, the positive feedback transistor is an N-type transistor, and the control signal is inversely related to the voltage signal.

[0011] Optionally, the inverter includes a first transistor and a second transistor, the gate terminals of the first transistor and the second transistor are connected to serve as the input terminal of the inverter; the drain terminal of the first transistor is connected to the source terminal of the second transistor to serve as the output terminal of the inverter; the source terminal of the first transistor is connected to a power supply signal, and the drain terminal of the second transistor is grounded.

[0012] Optionally, the inverter includes a first transistor and a plurality of second transistors. The gate terminals of the first transistor and each of the plurality of second transistors are connected to serve as the input terminal of the inverter. The drain terminal of the first transistor is connected to the source terminal of each of the second transistors to serve as the output terminal of the inverter. The source terminal of the first transistor is connected to a power supply signal, and the drain terminal of each of the second transistors is grounded.

[0013] Optionally, it also includes: at least one switch;

[0014] The source terminals of every two second transistors are connected via the switch, and the number of second transistors connected to the drain terminal of the first transistor is controlled by the on / off state of the at least one switch.

[0015] Optionally, the inverter includes a plurality of first transistors and a second transistor. The gate terminals of each of the plurality of first transistors are connected to the gate terminal of the second transistor to serve as the input terminal of the inverter. The drain terminal of each of the first transistors is connected to the source terminal of the second transistor to serve as the output terminal of the inverter. The source terminal of each of the first transistors is connected to a power supply signal, and the drain terminal of the second transistor is grounded.

[0016] Optionally, it also includes: at least one switch;

[0017] The drain terminals of every two first transistors are connected by a switch, and the number of first transistors connected to the source terminal of the second transistor is controlled by the on / off state of at least one of the switches.

[0018] Optionally, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0019] In another aspect of the present disclosure, an electronic device is provided, including: a processor, and a memory communicatively connected to the processor, and further including the image sensor pixel unit described in any of the above embodiments;

[0020] The memory stores computer-executed instructions;

[0021] The processor executes computer execution instructions stored in the memory to control the image sensor pixel units.

[0022] Optionally, the electronic device may be included as any of the following: image data acquisition device, audio / video player, navigation device, entertainment device, communication device, roadside traffic facility, device in motor vehicle, industrial testing device, flight equipment, medical device, security device.

[0023] The image sensor pixel unit and electronic device provided in the above embodiments of this disclosure include: a photodiode, a reset transistor, a positive feedback transistor, and an inverter; one end of the photodiode is grounded, and the other end is connected to the input terminals of the reset transistor and the inverter; the source terminal of the reset transistor is connected to a power supply signal, the drain terminal is connected to the photodiode, and the gate terminal is connected to a reset signal; the positive feedback transistor is connected in parallel with the photodiode, the drain terminal of the positive feedback transistor is connected to the connection node, the source terminal is grounded, and the gate terminal is connected to the output terminal of the inverter; the connection node is the connection point between the photodiode and the reset transistor; the input terminal of the inverter is connected to the other end of the photodiode, and the output terminal of the inverter is connected to the gate terminal of the positive feedback transistor. By adding a positive feedback transistor and an inverter to the pixel unit, when the voltage signal generated by the photodiode drops to a specific threshold, a positive feedback process is triggered, causing the voltage signal to quickly drop to zero. This allows for accurate detection of the moment when the voltage signal drops to a specific threshold, improving the accuracy of the pulse signal obtained by the pixel unit.

[0024] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0025] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0026] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0027] Figure 1 This is a schematic diagram of the circuit structure of an image sensor pixel unit provided in an exemplary embodiment of the present disclosure;

[0028] Figure 2 This is a schematic diagram of the circuit structure of an image sensor pixel unit provided in another exemplary embodiment of this disclosure;

[0029] Figure 3The circuit simulation results of voltage variation according to the embodiments of this disclosure are shown, along with a comparative schematic diagram with the case without positive feedback.

[0030] Figure 4a This is a schematic diagram of the circuit structure of an image sensor pixel unit provided in yet another exemplary embodiment of this disclosure;

[0031] Figure 4b This is a schematic diagram of the circuit structure of an image sensor pixel unit provided in an exemplary embodiment of the present disclosure;

[0032] Figure 5 This is a circuit simulation diagram of the signal when different numbers of second transistors are connected in parallel in the inverter of the pixel unit in the embodiments of this disclosure;

[0033] Figure 6a This is a schematic diagram of the circuit structure of an image sensor pixel unit provided in yet another exemplary embodiment of the present disclosure;

[0034] Figure 6b This is a schematic diagram of the circuit structure of an image sensor pixel unit provided in another exemplary embodiment of the present disclosure;

[0035] Figure 7 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed herein. Detailed Implementation

[0036] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0037] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0038] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0039] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0040] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0041] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0042] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0043] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0044] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0045] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0046] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0047] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0048] In developing this disclosure, the inventors discovered that, typically, comparators and other circuit structures are needed inside or around the pulse pixel unit to determine whether the signal has reached a threshold, thereby deciding whether to output a pulse. Compared to the pixel unit structure, the comparator circuit structure is more complex. Placing the comparator within each pixel increases the pixel area, making large-scale integration more difficult; while placing the comparator around the pixel reduces the signal output rate. Therefore, pulse pixels based on traditional comparator circuits cannot simultaneously achieve both ultra-large-scale integration and ultra-high speed.

[0049] To address the aforementioned problems, the inventors proposed a novel structure for image sensor pixel units.

[0050] Figure 1 This is a schematic diagram of the circuit structure of an image sensor pixel unit provided in an exemplary embodiment of this disclosure. Figure 1 As shown, the sensor pixel unit (hereinafter referred to as pixel unit) provided in this embodiment includes: a photodiode 110, a reset transistor 120, a positive feedback transistor 130, and an inverter 140;

[0051] One end of the photodiode 110 is grounded to GND, and the other end is connected to the reset transistor 120. The photodiode 110 is used to receive light signals during the exposure time to generate voltage signals; the signal is output through the connection node pd between the photodiode 110 and the reset transistor 120.

[0052] A photodiode is a photodetector that converts light into current or voltage signals depending on the application; in this embodiment, it is converted into a voltage signal. The die typically uses a PN junction with photosensitive characteristics, making it highly sensitive to changes in light. It exhibits unidirectional conductivity, and its electrical properties change with varying light intensity. Therefore, the voltage or current in a circuit can be altered using the intensity of light.

[0053] The source terminal of the reset transistor 120 is connected to the power supply signal Vdd, the drain terminal is connected to the photodiode, and the gate terminal is connected to the reset signal RST. The reset transistor 120 is used to control the reset of the photodiode 110 according to its conduction status. When the reset transistor 120 is on, the other end of the photodiode 110 is directly connected to the power supply signal Vdd to reset the photodiode 110, and the voltage at the connection node of the photodiode 110 is set to the power supply voltage (high level). When the reset transistor 120 is off, the other end of the photodiode 110 is not connected to the power supply signal Vdd, and it enters the exposure stage. At this time, the photodiode 110 receives light and generates photocharge. The photocharge is collected at the connection node, causing the power supply voltage at the connection node to drop after reset, thus obtaining a voltage signal, which is then output through the connection node.

[0054] In some alternative embodiments, the reset transistor 120 is turned on or off according to the control of a reset signal. The reset signal is provided by an external circuit. Optionally, in response to the reset transistor 120 being an N-type transistor, the external circuit provides a high-level reset signal at a preset period. By sending a high-level reset signal to the gate terminal of the reset transistor, the reset transistor is turned on, thereby controlling the photodiode to reset. In response to the reset transistor 120 being a P-type transistor, the external circuit provides a low-level reset signal at a preset period. By sending a low-level reset signal to the gate terminal of the reset transistor, the reset transistor is turned on, thereby controlling the photodiode to reset.

[0055] The positive feedback transistor 130 is connected in parallel with the photodiode 110. The drain terminal of the positive feedback transistor 130 is connected to the connection node pd, the source terminal is grounded, and the gate terminal is connected to the output terminal of the inverter 140. The connection node is the connection point between the photodiode and the reset transistor.

[0056] In this embodiment, a path is established between the connection node pd and the ground terminal GND through the positive feedback transistor 130. When the positive feedback transistor 130 is turned on, the connection node pd is grounded, and the voltage signal quickly drops to 0 level. In this embodiment, a control signal can be obtained by processing the voltage signal through an inverter. The control signal is used to control whether the positive feedback transistor 130 is turned on. For example, the voltage signal can be reversed by an inverter located inside or outside the pixel unit, and the control signal output by the inverter can be used to control the conduction of the positive feedback transistor 130.

[0057] In some optional examples, the positive feedback transistor is an N-type transistor, and the control signal is inverted compared to the voltage signal. In this case, an odd number of inverters (e.g., 1, 3, 5, etc.) are connected in series inside or outside the pixel unit. When the voltage signal drops to a preset threshold, it manifests as a low-level signal. After processing by the odd number of inverters, the output is a high-level control signal. This control signal is input to the gate of the positive feedback transistor 130, turning it on and enabling accurate positioning of the time when the voltage signal drops to the preset threshold. In this example, the inverters invert the voltage signal to a normal high-level signal while simultaneously controlling the exposure time, i.e., controlling the pixel unit sensitivity, by using more inverters. More inverters result in a slower voltage signal drop and lower pixel unit sensitivity; fewer inverters result in a faster voltage signal drop and higher pixel unit sensitivity.

[0058] In some alternative examples, the positive feedback transistor is a P-type transistor, and the control signal is in the same direction as the voltage signal. An even number of inverters (e.g., 2, 4, 6, etc.) are connected in series inside or outside the pixel unit. When the voltage signal drops to a preset threshold, it manifests as a low-level signal. After processing by the inverters, the output is a low-level control signal. This control signal is input to the gate of the positive feedback transistor 130 (which is an N-type transistor), turning it on and enabling accurate positioning of the time when the voltage signal drops to the preset threshold. In this example, the inverters not only reshape the voltage signal into a normal low-level signal but also control the exposure time, i.e., control the pixel unit sensitivity, by adjusting the number of inverters. For example, more inverters result in a slower voltage signal drop and lower pixel unit sensitivity; fewer inverters result in a faster voltage signal drop and higher pixel unit sensitivity.

[0059] The input terminal of inverter 140 is connected to connection node pd, and the output terminal is connected to the gate terminal of positive feedback transistor 130.

[0060] That is, in this embodiment, the voltage signal is connected to the positive feedback transistor 130 through the inverter 140, so as to realize the pixel sensitivity control inside the pixel unit without the need for external signal input.

[0061] The inverter 140 is used to reverse the voltage signal generated by the photodiode within a preset time to obtain a control signal that is opposite to the voltage signal, and to control whether the positive feedback transistor is turned on through the control signal.

[0062] In this embodiment, the output terminal of the inverter can be used as the output terminal of the pixel unit to output a pulse signal.

[0063] This embodiment reverses the voltage signal generated by the photodiode by inverting an inverter inside the pixel unit. The resulting signal serves as a pulse signal output by the pixel unit after processing. This means that whenever the photogenerated charge of the photodiode accumulates to a certain level, causing the voltage signal at the connection node to drop to a preset threshold, a high-level pulse signal is output. The timing of this pulse signal output indicates the light intensity received by the pixel unit. The reversed signal also serves as a control signal for the positive feedback transistor 130, controlling its conduction. When the control signal is high, the positive feedback transistor 130 is turned on, causing the voltage signal to drop rapidly. This allows for accurate positioning of the signal flip-over time, improving the pixel unit's sensitivity to light intensity recognition.

[0064] In this embodiment, the preset time can be determined according to the circuit structure of the inverter. The preset time can be adjusted by using inverters with different structures. Different preset times correspond to different sensitivities, thereby enabling the sensitivity of the pixel unit to be adjusted.

[0065] The image sensor pixel unit provided in the above embodiments of this disclosure includes: a photodiode, a reset transistor, a positive feedback transistor, and an inverter; one end of the photodiode is grounded, and the other end is connected to the input terminals of the reset transistor and the inverter; the source terminal of the reset transistor is connected to a power supply signal, the drain terminal is connected to the photodiode, and the gate terminal is connected to a reset signal; the positive feedback transistor is connected in parallel with the photodiode, the drain terminal of the positive feedback transistor is connected to the connection node, the source terminal is grounded, and the gate terminal is connected to the output terminal of the inverter; the connection node is the connection point between the photodiode and the reset transistor; the input terminal of the inverter is connected to the other end of the photodiode, and the output terminal of the inverter is connected to the gate terminal of the positive feedback transistor. By adding a positive feedback transistor to the pixel unit, when the voltage signal generated by the photodiode drops to a specific threshold, a positive feedback process is triggered, causing the voltage signal to quickly drop to zero. This allows for accurate detection of the moment when the voltage signal drops to a specific threshold, improving the accuracy of the pulse signal obtained by the pixel unit.

[0066] Figure 2 This is a schematic diagram of the circuit structure of an image sensor pixel unit provided in another exemplary embodiment of this disclosure. The preset time is a first preset time; as shown... Figure 2 As shown, in the pixel unit of this embodiment, the inverter 140 includes a first transistor 141 and a second transistor 142.

[0067] The gate terminals of the first transistor 141 and the second transistor 142 are connected to form the input terminal of the inverter; the drain terminal of the first transistor 141 is connected to the source terminal of the second transistor 142 to form the output terminal of the inverter 140; the source terminal of the first transistor 141 is connected to the power supply signal, and the drain terminal of the second transistor 142 is grounded.

[0068] In this embodiment, when the voltage signal input to the inverter drops to a preset threshold, it is represented by a low level. At this time, the first transistor is turned on, connecting the power supply signal to the inverter output terminal, and the output power supply signal through the inverter is a high level; the second transistor is turned off. Conversely, when the voltage signal input to the inverter is higher than the preset threshold, it is represented by a high level. At this time, the second transistor is turned on, connecting the ground terminal to the inverter output terminal, and the output of the inverter is a 0 level, i.e., a high level; the first transistor is turned off.

[0069] Therefore, in this embodiment, the input voltage signal is reversed and sorted by an inverter. The signal output by the inverter is a 0 and 1 pulse signal, and the pulse signal is used as the control signal to control the positive feedback transistor 130.

[0070] Optionally, the first transistor is a P-type transistor, and the second transistor is an N-type transistor. When the input voltage is much lower or much higher than the threshold voltage, the inverter's output signal has a high switching rate; conversely, when the input voltage is near the threshold voltage, the output signal's switching rate is low. Therefore, inverters are mainly used to process 0 and 1 signals in digital circuits, while the signals in pixel units are continuous analog signals, making direct inverter processing performance poor. Therefore, in this embodiment, the inverter composed of one N-type MOSFET and one P-type MOSFET connected in series can also be used as a comparator, and its simple structure makes it easy to integrate into the pixel unit.

[0071] In the pixel unit provided in this embodiment, during operation, a low-level reset signal RST is first provided to the reset transistor 120 (in this example, the reset transistor is a P-type transistor), controlling the reset transistor 120 to conduct and reset the photodiode 110. The voltage signal Vpd is reset to the power supply signal VDD (high level). At this time, the first transistor is turned off, the second transistor is turned on, and the output signal Vs output by the comparator of the pixel unit is low level, and the positive feedback transistor 130 is turned off. After the reset is completed, the reset signal RST is set to high level, the reset transistor 120 is turned off, and the exposure stage begins. At this time, the photodiode 110 receives light and excites electrons to generate photogenerated charge. The photogenerated charge is collected at the connection node pd, causing the voltage signal Vpd to decrease. When the voltage signal Vpd decreases to a certain level (preset threshold), the first transistor starts to conduct, and the second transistor gradually starts to turn off. The current through the first transistor increases, and the current through the second transistor decreases, thereby causing the output signal Vs to start to rise. The rise in output signal Vs turns on positive feedback transistor 130, accelerating the fall of voltage signal Vpd and further promoting the rise of output signal Vs, thus completing the positive feedback process of the circuit signal. This positive feedback process ends when voltage signal Vpd drops to zero and output signal Vs rises to VDD, at which point it is considered that the pixel unit has emitted a pulse signal. By detecting the moment when output signal Vs rises to a high level through external circuitry, the light intensity received by the pixel unit can be reflected. (Refer to...) Figure 3 The diagram illustrates the circuit simulation results of voltage changes according to an embodiment of this disclosure, and a comparison with the case without positive feedback. It can be seen that after the pixel unit is reset, the voltage signal Vpd gradually decreases during exposure, and the voltage decreases with increasing light intensity (e.g., ...). Figure 3 As shown by the middle arrow, the direction of the arrow indicates that the light intensity is increasing (i.e., in the diagram, the earlier the voltage signal Vpd drops, the greater the light intensity corresponding to the pixel unit). The faster the voltage signal Vpd drops, the more rapid the drop. When the voltage signal Vpd drops to a preset threshold, a positive feedback process is triggered, and the voltage signal Vpd is quickly pulled down to zero, while the output signal Vs is quickly pulled up to a high level. However, without a positive feedback design, i.e., without the positive feedback transistor 130, as... Figure 3 As shown, the rate of change of the output signal Vs is significantly slower, and the rate at which the output signal Vs rises varies under different light intensities, making it difficult to accurately detect when the voltage signal Vpd drops to the preset threshold. This embodiment improves the accuracy of the pixel unit signal through a positive feedback design.

[0072] Figure 4a This is a schematic diagram of the circuit structure of an image sensor pixel unit provided in yet another exemplary embodiment of this disclosure. The preset time is a second preset time; as shown... Figure 4aAs shown, in the pixel unit of this embodiment, the inverter 140 includes a first transistor 141 and a plurality of second transistors 142.

[0073] The gate of each of the first transistor 141 and the plurality of second transistors 142 is connected to serve as the input terminal of the inverter 140; the drain terminal of the first transistor 141 is connected to the source terminal of each of the second transistors 142 to serve as the output terminal of the inverter 140; the source terminal of the first transistor 141 is connected to the power supply signal, and the drain terminal of each of the second transistors 142 is grounded.

[0074] Optionally, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0075] The pixel unit structure provided in this disclosure allows for adjustment of the preset threshold value for triggering positive feedback by adjusting the number of transistors in the inverter, thereby achieving adjustable sensitivity. The more second transistors included in the inverter, the smaller the preset threshold for triggering positive feedback, and the lower the sensitivity of the pixel unit. Connecting a fixed number of second transistors provides a lower sensitivity compared to connecting a single second transistor. Optionally, to achieve adjustable sensitivity of the pixel unit, other methods can be used, such as... Figure 4b The pixel unit structure provided in the illustrated embodiment further includes at least one switch 150;

[0076] The source terminals of every two second transistors 142 are connected via a switch 150, and the number of second transistors 142 connected to the drain terminal of the first transistor 141 is controlled by the on / off state of at least one switch 150.

[0077] In this embodiment, the opening and closing of each switch can be controlled by an external circuit. When a switch is closed, the inverter includes one first transistor and two second transistors. The more switches are closed, the more second transistors are connected in parallel in the inverter. The more second transistors (nMOSFETs) connected in parallel, the more current flows through the output signal Vs before positive feedback is triggered, requiring more current to be injected from the first transistors to trigger positive feedback, i.e., more exposure is needed to trigger positive feedback. Conversely, the fewer second transistors (nMOSFETs) connected in parallel, the less exposure is needed to trigger positive feedback. The sensitivity of the pixel unit can be adjusted by changing the number of second transistors connected to the circuit. Figure 5 This is a circuit simulation diagram of the signal when different numbers of second transistors are connected in parallel in the inverter of the pixel unit according to an embodiment of this disclosure. Figure 5 As shown, under the same lighting conditions, the more parallel second transistors there are, the lower the voltage signal Vpd when positive feedback is triggered, and the later the output signal Vs jumps to a high level, meaning the lower the sensitivity of the pixel unit.

[0078] Figure 6a This is a schematic diagram of the circuit structure of an image sensor pixel unit provided in another exemplary embodiment of this disclosure. The preset time is a second preset time; as shown... Figure 6a As shown, in the pixel unit of this embodiment, the inverter 140 includes a plurality of first transistors 141 and a second transistor 142.

[0079] The gate terminals of each of the multiple first transistors 141 and the second transistor 142 are connected to serve as the input terminal of the inverter 140; the drain terminal of each first transistor 141 is connected to the source terminal of the second transistor 142 to serve as the output terminal of the inverter 140; the source terminal of each first transistor 141 is connected to the power supply signal, and the drain terminal of the second transistor 142 is grounded.

[0080] Optionally, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0081] This embodiment is the same as the above. Figure 4a The provided embodiment is similar, also adjusting the specific value of the preset threshold for triggering positive feedback by adjusting the number of transistors in the inverter, thereby achieving adjustable sensitivity. The difference is that in this embodiment, the number of the first transistor is adjusted. Similarly, to achieve adjustable sensitivity of pixel units, other methods can also be used... Figure 6b The pixel unit structure provided in the illustrated embodiment further includes at least one switch 150;

[0082] The drain terminals of every two first transistors 141 are connected via a switch 150, and the number of first transistors 141 connected to the source terminal of the second transistor 142 is controlled by the on / off state of at least one switch 150.

[0083] In this embodiment, the opening and closing of each switch can be controlled by an external circuit. When a switch is closed, the inverter includes two first transistors and one second transistor. The more switches are closed, the more first transistors are connected in parallel in the inverter. The more first transistors (pMOSFETs) connected in parallel, the more current flows through the output signal Vs before triggering positive feedback, requiring more current injection from the first transistors to trigger positive feedback, i.e., more exposure is needed to trigger positive feedback. Conversely, the fewer first transistors (pMOSFETs) connected in parallel, the less exposure is needed to trigger positive feedback. The sensitivity of the pixel unit can be adjusted by changing the number of first transistors connected in the circuit. A circuit simulation diagram of the signal when different numbers of first transistors are connected in parallel in the inverter of the pixel unit in this embodiment can be found in the following example. Figure 5 As shown. Figure 5As shown (the only difference is that the first transistor is connected in parallel), under the same lighting conditions, the more first transistors are connected in parallel, the lower the voltage signal Vpd when positive feedback is triggered, and the later the output signal Vs jumps to a high level, that is, the lower the sensitivity of the pixel unit.

[0084] In addition, this disclosure also provides an electronic device, including:

[0085] The processor, and the memory communicatively connected to the processor, further include the image sensor pixel unit described in any of the above embodiments;

[0086] The memory stores computer-executed instructions;

[0087] The processor executes computer execution instructions stored in the memory to control the image sensor pixel units.

[0088] The electronic devices provided in this disclosure can be included in any of the following: image data acquisition devices, audio / video players, navigation devices, entertainment devices, communication devices, roadside traffic facilities, devices in motor vehicles, industrial testing equipment, flight equipment, medical devices, security equipment, etc.

[0089] The electronic equipment provided in this disclosure can be applied to any of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial testing equipment, flight equipment, medical equipment, security equipment, etc.

[0090] Figure 7 This is a schematic diagram illustrating the structure of an application embodiment of the electronic device disclosed herein. Below, reference is made to… Figure 7 This describes an electronic device according to embodiments of the present disclosure. The electronic device may be either or both of a first device and a second device, or a standalone device independent of them, which may communicate with the first device and the second device to receive acquired input signals from them.

[0091] like Figure 7 As shown, the electronic device includes one or more processors and memory.

[0092] A processor can be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and can control other components in an electronic device to perform desired functions.

[0093] The memory can store one or more computer program products, and the memory can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products can be stored on the computer-readable storage medium, and the processor can run the computer program products to implement the image sensor pixel units and / or other desired functions of the various embodiments of this disclosure described above.

[0094] In one example, the electronic device may also include input devices and output devices, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0095] In addition, the input device may also include, for example, a keyboard, a mouse, etc.

[0096] This output device can output various information to the outside, including determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0097] Of course, for the sake of simplicity, Figure 7 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0098] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the image sensor pixel units according to the various embodiments of this disclosure described in the foregoing portion of this specification.

[0099] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0100] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform the image sensor pixel units according to various embodiments of this disclosure as described in the foregoing portion of this specification.

[0101] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0102] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0103] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0104] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0105] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0106] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0107] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0108] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A pixel unit for an image sensor, characterized in that, include: Photodiodes, reset transistors, positive feedback transistors, and inverters; One end of the photodiode is grounded, and the other end is connected to the input terminal of the reset transistor and the inverter. The source terminal of the reset transistor is connected to the power supply signal, the drain terminal is connected to the photodiode, and the gate terminal is connected to the reset signal. The positive feedback transistor is connected in parallel with the photodiode. The drain terminal of the positive feedback transistor is connected to the connection node, the source terminal is grounded, and the gate terminal is connected to the output terminal of the inverter. The connection node is the connection point between the photodiode and the reset transistor. The input terminal of the inverter is connected to the other end of the photodiode, and the output terminal of the inverter is connected to the gate terminal of the positive feedback transistor.

2. The pixel unit according to claim 1, characterized in that, The positive feedback transistor is an N-type transistor.

3. The pixel unit according to claim 1, characterized in that, The inverter includes a first transistor and a second transistor. The gate terminals of the first transistor and the second transistor are connected to form the input terminal of the inverter. The drain terminal of the first transistor is connected to the source terminal of the second transistor to form the output terminal of the inverter. The source terminal of the first transistor is connected to the power supply signal, and the drain terminal of the second transistor is grounded.

4. The pixel unit according to claim 1, characterized in that, The inverter includes a first transistor and a plurality of second transistors. The gate terminals of the first transistor and each of the plurality of second transistors are connected to serve as the input terminal of the inverter. The drain terminal of the first transistor is connected to the source terminal of each of the plurality of second transistors to serve as the output terminal of the inverter. The source terminal of the first transistor is connected to the power supply signal, and the drain terminal of each second transistor is grounded.

5. The pixel unit according to claim 4, characterized in that, Also includes: At least one switch; The source terminals of every two second transistors are connected via the switch, and the number of second transistors connected to the drain terminal of the first transistor is controlled by the on / off state of the at least one switch.

6. The pixel unit according to claim 1, characterized in that, The inverter includes a plurality of first transistors and a second transistor. The gate terminals of each of the plurality of first transistors are connected to the gate terminals of the second transistor to serve as the input terminal of the inverter. The drain terminal of each of the first transistors is connected to the source terminal of the second transistor to serve as the output terminal of the inverter. The source terminal of each of the first transistors is connected to a power supply signal, and the drain terminal of the second transistor is grounded.

7. The pixel unit according to claim 6, characterized in that, Also includes: At least one switch; The drain terminals of every two first transistors are connected by a switch, and the number of first transistors connected to the source terminal of the second transistor is controlled by the on / off state of at least one of the switches.

8. The pixel unit according to any one of claims 3-7, characterized in that, The first transistor is a P-type transistor, and the second transistor is an N-type transistor.

9. An electronic device, characterized in that, Includes: a processor, and a memory communicatively connected to the processor, and further includes the image sensor pixel unit as described in any one of claims 1-8; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to control the image sensor pixel units.

10. The device according to claim 9, characterized in that, The electronic device is included in any of the following: image data acquisition device, audio / video player, navigation device, entertainment device, communication device, roadside traffic facility, device in motor vehicle, industrial testing device, flight equipment, medical device, security device.

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